Datasheet

MAX1415/MAX1416
16-Bit, Low-Power, 2-Channel,
Sigma-Delta ADCs
8 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS—MAX1416 (continued)
(V
DD
= 5V, GND = 0, V
REF+
= 2.5V, V
REF-
= GND, f
CLKIN
= 2.4576MHz, CLKDIV bit = 0, C
REF+
to GND = 0.1µF, C
REF-
to GND =
0.1µF, T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Unbuffered, f
CLKIN
= 1MHz, gain = 1 to 128 0.45
Buffered, f
CLKIN
= 1MHz, gain = 1 to 128 0.78
Gain = 1 to 4 0.6
Unbuffered,
f
CLKIN
= 2.4576MHz
Gain = 8 to 128 0.6
Gain = 1 to 4 0.95
Buffered,
f
CLKIN
= 2.4576MHz
Gain = 8 to 128 1.1
mA
Power-Supply Current (Note 12) I
DD
Power-down mode (Note 13) 16 µA
Power-Supply Rejection Ratio PSRR V
DD
= 4.75V to 5.25V (Note 14) dB
EXTERNAL-CLOCK SPECIFICATIONS
CLKIN Frequency f
CLKIN
(Note 15) 400 2500 kHz
Duty Cycle 40 60 %
INTERNAL-CLOCK TIMING SPECIFICATIONS
MAX1416AE__,
f
CLK
= 1MHz (CLK = 0)
or 2.4576MHz (CLK = 1)
T
A
= -40°C to
+85°C
±4
MAX1416C__,
f
CLK
= 1MHz (CLK = 0)
or 2.4576MHz (CLK = 1)
T
A
= 0°C to
+70°C
±4
T
A
= -40°C to 0°C±7
Internal-Clock Frequency f
CLK
MAX1416E__,
f
CLK
= 1MHz (CLK = 0)
or 2.4576MHz (CLK = 1)
T
A
= 0°C to + 85°C ±4
%
Typical Conversion-Time
Variation
∆t
CONV
t
CONV
= 1/ODR,
CLK = 0 (1MHz), INTCLK = 1
±0.5 %
TIMING CHARACTERISTICS—MAX1416
(Note 16) (Figures 8, 9)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DRDY High Time
500 /
f
CLKIN
s
Reset Pulse-Width Low 100 ns
DRDY Fall to CS Fall Setup Time t
1
0ns
CS Fall to SCLK Rise Setup Time t
2
120 ns
SCLK Fall to DOUT Valid Delay t
3
080ns
SCLK Pulse-Width High t
4
100 ns
SCLK Pulse-Width Low t
5
100 ns
CS Rise to SCLK Rise Hold Time t
6
0ns
Bus Relinquish Time After SCLK
Rising Edge
t
7
60 ns
SCLK Fall to DRDY Rise Delay t
8
100 ns