Datasheet

MAX1415/MAX1416
16-Bit, Low-Power, 2-Channel,
Sigma-Delta ADCs
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ELECTRICAL CHARACTERISTICS—MAX1415 (continued)
(V
DD
= 3V, GND = 0, V
REF+
= 1.225V, V
REF-
= GND, external f
CLKIN
= 2.4576MHz, CLKDIV bit = 0, C
REF+
to GND = 0.1µF, C
REF-
to
GND = 0.1µF, T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Typical Conversion-Time
Variation
∆t
CONV
t
CONV
= 1/ODR ±0.5 %
ELECTRICAL CHARACTERISTICS—MAX1416
(V
DD
= 5V, GND = 0, V
REF+
= 2.5V, V
REF-
= GND, f
CLKIN
= 2.4576MHz, CLKDIV bit = 0, C
REF+
to GND = 0.1µF, C
REF-
to GND =
0.1µF, T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DC ACCURACY
Resolution (No Missing Codes) 16 Bits
Output Noise (Tables 1, 3) µV
Integral Nonlinearity INL Gain = 1, bipolar mode, unbuffered ±0.0015 %FSR
Unipolar Offset Error After calibration (Note 1) µV
Unipolar Offset Drift (Note 2) 0.5 µV/°C
Bipolar Zero Error After calibration (Note 1) µV
Gain = 1 to 4 0.5
Bipolar Zero Drift (Note 2)
Gain = 8 to 128 0.1
µV/°C
TIMING CHARACTERISTICS—MAX1415
(Note 16) (Figures 8, 9)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DRDY High Time
500/
f
CLKIN
s
Reset Pulse-Width Low 100 ns
DRDY Fall to CS Fall Setup Time t
1
0ns
CS Fall to SCLK Rise Setup Time t
2
120 ns
SCLK Fall to DOUT Valid Delay t
3
0 100 ns
SCLK Pulse-Width High t
4
100 ns
SCLK Pulse-Width Low t
5
100 ns
CS Rise to SCLK Rise Hold Time t
6
0ns
Bus Relinquish Time After SCLK
Rising Edge
t
7
100 ns
SCLK Fall to DRDY Rise Delay t
8
100 ns
DIN to SCLK Setup Time t
9
30 ns
DIN to SCLK Hold Time t
10
20 ns