Datasheet

MAX1407/MAX1408/MAX1409/MAX1414
Low-Power, 16-Bit Multichannel DAS with
Internal Reference,10-Bit DACs, and RTC
6 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(DV
DD
= AV
DD
= +2.7V to 3.6V, 4.7µF at REF, internal V
REF
, 18nF between CPLL and AV
DD
, 32.768kHz crystal across CLKIN and
CLKOUT, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX U N I T S
D0 Output Low Voltage
(MAX1407/MAX1408/MAX1414
only)
I
SINK
= 200µA, DV
DD
= +2.7V to +3.6V 0.7 mV
D0 Output High Voltage
(MAX1407/MAX1408/MAX1414
only)
I
S OU RC E
= 2m A, D V
D D
= + 2.7V to + 3.6V
DV
DD
- 0.1
V
POWER REQUIREMENTS
Run, Idle, and Standby mode 2.7 3.6
Supply Voltage Range V
DD
Sleep mode 1.8 3.6
V
MAX1407/MAX1414 1.15
MAX1408 1.03
Run mode
MAX1409 1.09
mA
MAX1407/MAX1414 650
MAX1408 530Idle mode
MAX1409 590
Standby mode
MAX1407/MAX1408/
MAX1409/MAX1414
330
Supply Current (Note 5) I
DD
Sleep mode
V
DD
= 2.7V
MAX1407/MAX1408/
MAX1409/MAX1414
1.7 2.5
µA
TIMING CHARACTERISTICS
(MAX1407/MAX1408/MAX1409/MAX1414: AV
DD
= DV
DD
= 2.7V to 3.6V, T
A
= T
MIN
to T
MAX,
unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
TIMING PARAMETERS
SCLK Operating Frequency f
SCLK
2.1 MHz
SCLK Cycle Time t
CYC
476 ns
SCLK Pulse Width High t
CH
190 ns
SCLK Pulse Width Low t
CL
190 ns
DIN to SCLK Setup t
DS
100 ns
DIN to SCLK Hold t
DH
0ns
SCLK Fall to Output Data Valid t
DO
C
L
= 50pF (see load circuit) 200 ns
CS Fall to Output Enable t
DV
C
L
= 50pF (see load circuit) 240 ns
CS Rise to Output Disable t
TR
C
L
= 50pF (see load circuit) 240 ns
CS to SCLK Rise Setup t
CSS
100 ns
CS to SCLK Rise Hold t
CSH
0ns