Datasheet

MAX1407/MAX1408/MAX1409/MAX1414
Low-Power, 16-Bit Multichannel DAS with
Internal Reference,10-Bit DACs, and RTC
36 ______________________________________________________________________________________
POWER2 REGISTER (11001)
DA1E: DAC1 Power Enable. A logic 1 powers DAC1,
while a logic 0 powers it down. The output buffer goes
high impedance in power-down mode.
DA2E: DAC2 Power Enable. A logic 1 powers DAC2,
while a logic 0 powers it down. The output buffer goes
high impedance in power-down mode.
SHDE: Shutdown Enable bar. If SHDE is set to 1,
SHDN is pulled high. A wake-up event such as an
assertion of WU1 or WU2, a time-of-day alarm, or by
writing to the Power1, Power2, Standby, Idle, or Run
registers sets this bit to 1 and drives SHDN high. If the
SHDE bit is set to 0 in Standby, Idle, or Run mode and
the PLL is still operational (PLLE = 1), the SHDN pin will
remain high until 2.93ms (t
DPD
) after PLLE is set to 0.
PLLE: Phase-Locked Loop Power Enable. A logic 1
powers the PLL and enables FOUT while a logic 0 pow-
ers down the PLL and disables FOUT. A wake-up event
sets this bit to 1. See Wake-Up section.
LVDE: +2.7V Voltage Monitor Power Enable. A logic 1
powers the +2.7V voltage comparator circuitry, while a
logic 0 powers down the +2.7V voltage comparator cir-
cuitry. A wake-up event sets LVDE to 1. See Wake-Up
section.
LSDE: +1.8V Voltage Monitor Power Enable. A logic 1
powers the +1.8V voltage comparator circuitry, while a
logic 0 powers down the +1.8V voltage comparator cir-
cuitry. See Wake-Up section.
SDCE: Signal-Detect Comparator Power Enable. A
logic 1 powers the signal-detect comparator while a
logic 0 powers down this comparator.
D0E: D0 Enable bit. A logic 0 three-states the D0
ouput. When D0E is set to “1”, the output of D0 is con-
tolled by the state of DBIT in the MUX register.
Programming the device in different modes does not
alter the state of this bit.
VM: RESET Voltage Monitor Threshold Selection bit. A
logic 0 selects a +2.7V threshold while a logic 1 selects
a +1.8V threshold for the RESET Voltage Monitor. The
VM bit effects the LVDE and LSDE bits in different
modes of operation (see Table 8).
BIASE: Bias Enable. A logic 1 powers up the master
bias circuit block. A wake-up event sets this bit to a
logic 1. See Wake-Up section.
SLEEP REGISTER (11010)
Addressing the Sleep register places the MAX1407/
MAX1408/MAX1409/MAX1414 in Sleep mode. This
occurs after the last bit of the command byte is clocked
into the device. It requires an 8-bit write, no data bits
are needed. Sleep mode powers down all functional
blocks except for the crystal oscillator, RTC, alarm, ser-
ial interface, wake-up circuitry, and RESET voltage
monitor. While in Sleep mode, pulling either WU1 or
WU2 low or an alarm event places the device into
Standby mode.
STANDBY REGISTER (11011)
Addressing the Standby register places the MAX1407/
MAX1408/MAX1409/MAX1414 in Standby mode. This
occurs after the last bit of the address byte is clocked
into the device. It requires an 8-bit write, no data bits
are needed. Standby mode powers up the same blocks
as Sleep mode, as well as the master bias circuitry, the
PLL, and the Low V
DD
Voltage Monitor. FOUT is also
enabled and SHDN is set high in Standby mode.
IDLE REGISTER (11100)
Addressing the Idle register places the MAX1407/
MAX1408/MAX1409/MAX1414 in Idle mode. This
occurs after the last bit of the address byte is clocked
into the device. Requires an 8-bit write, no data bits are
needed. In Idle mode, all circuits are powered up with
the exception of the ADC and the ADC Input Buffers.
RUN REGISTER (11101)
Addressing the Run register puts the MAX1407/
MAX1408/MAX1409/MAX1414 into Run mode. This
occurs after the last bit of the address byte is clocked
into the device. Requires an 8-bit write, no data bits are
needed. All the functional blocks are powered up in
Run mode.
FIRST BIT (MSB) (LSB)
NAME SHDE PLLE LVDE LSDE SDCE D0E VM BIASE
DEFAULT 11100001