Datasheet

RS-485 Transceivers with Low-Voltage
Logic Interface
V
ID
R
B
A
RECEIVER
OUTPUT
ATE
Figure 6. Receiver Propagation Delay Test Circuit
A
B
RO
V
OH
V
L/2
t
RPLH
t
RPHL
V
OL
+1V
-1V
THE RISE TIME AND FALL TIME OF INPUTS A AND B < 4ns
Figure 7. Receiver Propagation Delays
Test Circuits and Waveforms (continued)
S1 OPEN
S2 CLOSED
S3 = +1.5V
RO
V
L
0
0
V
OH
V
OH
/2
S1 OPEN
S2 CLOSED
S3 = +1.5V
t
RHZ
V
L
0
0
V
OH
0.25V
V
L
/2
S1 CLOSED
S2 OPEN
S3 = -1.5V
V
L
0
V
OL
V
L
V
L
/2
S1 CLOSED
S2 OPEN
S3 = -1.5V
t
RLZ
V
L
0
V
OL
V
L
0.25V
GENERATOR
V
L
+1.5V
1kΩ
C
L
15pF
S2
S1
50Ω
S3
-1.5V
R
V
ID
RE
RO
RE
RO
RE
RO
RE
t
RZH
, t
RZH(SHDN)
t
RZL
, t
RZL(SHDN)
(V
OL
+ V
L
)/2
V
L
/2
R
RO
RE
Figure 8. Receiver Enable and Disable Times
MAX13430E–MAX13433E
10
Maxim Integrated