Datasheet

+5.0V, ±15kV ESD-Protected, Fail-Safe,
Hot-Swap, RS-485/RS-422 Transceivers
Test Circuits and Waveforms (continued)
V
ID
R
B
A
RECEIVER
OUTPUT
ATE
Figure 6. Receiver Propagation Delay Test Circuit
A
B
RO
V
OH
V
CC
/2
t
RPLH
t
RPHL
V
OL
+1V
-1V
THE RISE TIME AND FALL TIME OF INPUTS A AND B < 4ns
Figure 7. Receiver Propagation Delays
S1 OPEN
S2 CLOSED
S3 = +1.5V
RO
V
CC
0
0
V
OH
V
OH
/ 2
S1 OPEN
S2 CLOSED
S3 = +1.5V
t
RHZ
V
CC
0
0
V
OH
0.25V
V
CC
/2
S1 CLOSED
S2 OPEN
S3 = -1.5V
V
CC
0
V
OL
V
CC
V
CC
/2
S1 CLOSED
S2 OPEN
S3 = -1.5V
t
RLZ
V
CC
0
V
OL
V
CC
0.25V
GENERATOR
V
CC
+1.5V
1kΩ
C
L
15pF
S2
S1
50Ω
S3
-1.5V
R
V
ID
RE
RO
RE
RO
RE
RO
RE
t
RZH
, t
RZH(SHDN)
t
RZL
, t
RZL(SHDN)
(V
OL
+ V
CC
) / 2
V
CC
/2
Figure 8. Receiver Enable and Disable Times
Maxim Integrated
11
MAX13080E–MAX13084E/
MAX13086E–MAX13089E