Datasheet

MAX13000E–MAX13005E
Ultra-Low-Voltage Level Translators
12 ______________________________________________________________________________________
Test Circuits/Timing Diagrams
Figure 1a. Driving I/OVL
Figure 1b. Timing for Driving I/OV
L
MAX13000E
C
I/OVCC
EN
I/OV
L_
R
S
SOURCE
V
L
V
CC
I/OV
CC
UNUSED I/Os ARE GROUNDED.
90%
50%
10%
I/OV
CC_
I/OV
L_
t
RISE/FALL
I/O
VL-VCC
t
RVCC
t
FVCC
90%
50%
10%
I/O
VL-VCC
t
RISE/FALL
< 3ns (MAX13003E/MAX13004E/MAX13005E)
t
RISE/FALL
< 80ns (MAX13000E/MAX13001E/MAX13002E)
Figure 2a. Driving I/OV
CC
Figure 2b. Timing for Driving I/OV
CC
MAX13000E
C
I/OVL
EN
I/OV
L_
R
S
SOURCE
UNUSED I/Os ARE GROUNDED.
V
L
V
CC
I/OV
CC
90%
50%
10%
I/OV
CC_
I/OV
L_
t
RISE/FALL
I/O
VCC-VL
I/O
VCC-VL
t
RVL
t
FVL
90%
50%
10%
t
RISE/FALL
< 3ns (MAX13003E/MAX13004E/MAX13005E)
t
RISE/FALL
< 80ns (MAX13000E/MAX13001E/MAX13002E)