Datasheet

To power-up from a software-initiated power-down, a
START condition followed by the correct slave address
must be received (with R/W = 0). The MAX127/MAX128
power-up after receiving the next bit.
For hardware-controlled power-down (FULLPD), pull
SHDN low. When hardware shutdown is asserted, it
becomes effective immediately and any conversion in
progress is aborted.
Choosing Power-Down Modes
The bandgap reference and reference buffer remain
active in STBYPD mode, maintaining the voltage on the
4.7μF capacitor at REF. This is a “DC” state that does not
degrade after standby power-down of any duration.
In FULLPD mode, only the bandgap reference is active.
Connect a 33μF capacitor between REF and AGND to
maintain the reference voltage between conversions and
to reduce transients when the buffer is enabled and dis-
abled. Throughput rates down to 1ksps can be achieved
without allotting extra acquisition time for reference recov-
ery prior to conversion. This allows conversion to begin
immediately after power-down ends. If the discharge of
the REF capacitor during FULLPD exceeds the desired
limits for accuracy (less than a fraction of an LSB), run a
STBYPD power-down cycle prior to starting conversions.
Take into account that the reference buffer recharges the
bypass capacitor at an 80mV/ms slew rate, and add 50μs
for settling time.
Auto-Shutdown
Selecting STBYPD on every conversion automatically
shuts the MAX127/MAX128 down after each conversion
without requiring any start-up time on the next conversion.
Figure 11a. Internal Reference Figure 12. Reference-Adjust Circuit
Figure 11b. External Reference, Reference at REF
REF
10kΩ
2.5V
REFADJ
C
REF
4.7µF
MAX127
MAX128
A
V
= 1.638
0.01µF
REF
V
DD
10kΩ
2.5V
4.096V
REFADJ
C
REF
4.7µF
MAX127
MAX128
A
V
= 1.638
REF
2.5V
2.5V
REFADJ
10kΩ
C
REF
4.7µF
MAX127
MAX128
A
V
= 1.638
0.01µF
Figure 11c. External Reference, Reference at REFADJ
100kΩ
510kΩ
24kΩ
REFADJ
+5V
MAX127
MAX128
0.01µF
MAX127/MAX128 Multirange, +5V, 12-Bit DAS with
2-Wire Serial Interface
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