Datasheet
MAX1274/MAX1275
1.8Msps, Single-Supply, Low-Power,
True-Differential, 12-Bit ADCs
4 _______________________________________________________________________________________
Note 1: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the gain error and the offset
error have been nulled.
Note 2: No missing codes over temperature.
Note 3: Conversion time is defined as the number of clock cycles (16) multiplied by the clock period.
Note 4: At sample rates below 10ksps, the input full-linear bandwidth is reduced to 5kHz.
Note 5: The listed value of three SCLK cycles is given for full-speed continuous conversions. Acquisition time begins on the 14th ris-
ing edge of SCLK and terminates on the next falling edge of CNVST. The IC idles in acquisition mode between conversions.
Note 6: Undersampling at the maximum signal bandwidth requires the minimum jitter spec for SINAD performance.
Note 7: Digital supply current is measured with the V
IH
level equal to V
L
, and the V
IL
level equal to GND.
TIMING CHARACTERISTICS
(V
DD
= +5V ±5%, V
L
= V
DD
, V
REF
= 4.096V, f
SCLK
= 28.8MHz, 50% duty cycle, T
A
= -40°C to +85°C, unless otherwise noted. Typical
values are at T
A
= +25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SCLK Pulse-Width High t
CH
V
L
= 1.8V to V
DD
15.6 ns
SCLK Pulse-Width Low t
CL
V
L
= 1.8V to V
DD
15.6 ns
C
L
= 30pF, V
L
= 4.75V to V
DD
14
C
L
= 30pF, V
L
= 2.7V to V
DD
17
SCLK Rise to DOUT Transition t
DOUT
C
L
= 30pF, V
L
= 1.8V to V
DD
24
ns
DOUT Remains Valid After SCLK
Rise
t
DHOLD
V
L
= 1.8V to V
DD
4ns
CNVST Fall to SCLK Fall t
SETUP
V
L
= 1.8V to V
DD
10 ns
CNVST Pulse Width t
CSW
V
L
= 1.8V to V
DD
20 ns
Power-Up Time; Full Power-Down t
PWR-UP
2ms
Restart Time; Partial Power-Down t
RCV
16 Cycles
CNVST
SCLK
DOUT
t
DHOLD
t
DOUT
t
SETUP
t
CSW
t
CL
t
CH
Figure 1. Detailed Serial-Interface Timing
GND
6kΩ
C
L
DOUT
DOUT
C
L
GND
V
L
a) HIGH-Z TO V
OH
, V
OL
TO V
OH
,
AND V
OH
TO HIGH-Z
b) HIGH-Z TO V
OL
, V
OH
TO V
OL
,
AND V
OL
TO HIGH-Z
6kΩ
Figure 2. Load Circuits for Enable/Disable Times