Datasheet

MAX1246/MAX1247
+2.7V, Low-Power, 4-Channel,
Serial 12-Bit ADCs in QSOP-16
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= +2.7V to +3.6V (MAX1246); V
DD
= +2.7V to +5.25V (MAX1247); COM = 0V; f
SCLK
= 2.0MHz; external clock (50% duty cycle);
15 clocks/conversion cycle (133ksps); MAX1246—4.7µF capacitor at VREF pin; MAX1247—external reference, VREF = 2.5V applied
to VREF pin; T
A
= T
MIN
to T
MAX
; unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CONVERSION RATE
Internal clock, SHDN = FLOAT 5.5 7.5
Internal clock, SHDN = V
DD
35 65
Conversion Time (Note 5) t
CONV
External clock = 2MHz, 12 clocks/
conversion
6
µs
Track/Hold Acquisition Time t
ACQ
1.5 µs
Aperture Delay 30 ns
Aperture Jitter
<50
ps
SHDN = FLOAT 1.8
Internal Clock Frequency
SHDN = V
DD
0.225
MHz
0.1 2.0
External Clock Frequency
Data transfer only 0 2.0
MHz
ANALOG/COM INPUTS
Unipolar, COM = 0V
0 to VREF
Input Voltage Range, Single-
Ended and Differential (Note 6)
Bi p ol ar , C OM = V RE F / 2
±VREF / 2
V
Multiplexer Leakage Current On/off leakage current, V
CH
_ = 0V or V
DD
±0.01
±1 µA
Input Capacitance 16 pF
INTERNAL REFERENCE (MAX1246 only, reference buffer enabled)
VREF Output Voltage T
A
= +25°C
2.480 2.500 2.520
V
VREF Short-Circuit Current 30 mA
MAX1246_C
±30 ±50
MAX1246_E
±30 ±60
VREF Temperature Coefficient
MAX1246_M
±30 ±80
ppm/°C
Load Regulation (Note 8) 0mA to 0.2mA output load
±0.35
mV
Internal compensation mode 0
Capacitive Bypass at VREF
External compensation mode 4.7
µF
Capacitive Bypass at REFADJ
0.047
µF
REFADJ Adjustment Range V
BST
= V
LX
= V
IN
= 28V, V
FB
= 1.5V
±1.5
%
EXTERNAL REFERENCE AT VREF (Buffer disabled)
VREF Input Voltage Range
(Note 9)
1.0
VDD +
50mV
V
VREF Input Current VREF = 2.5V
100 150
V
VREF Input Resistance 18 25 kΩ
Shutdown VREF Input Current
0.01 100
µA
REFADJ Buffer Disable
Threshold
VDD -
0.5
V