Datasheet

14 _____________________________________________________________________________________
MAX11661–MAX11666
500ksps, Low-Power,
Serial 12-/10-/8-Bit ADCs
ELECTRICAL CHARACTERISTICS (MAX11661) (continued)
(V
DD
= 2.2V to 3.6V. f
SCLK
= 8MHz, 50% duty cycle, 500ksps. C
DOUT
= 10pF, T
A
= -40NC to +125NC, unless otherwise noted. Typical
values are at T
A
= +25NC.) (Note 1)
Note 1: Limits at T
A
= -40NC are guaranteed by design and not production tested.
Note 2: All timing specifications given are with a 10pF capacitor.
Note 3: Guaranteed by design in characterization; not production tested.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DIGITAL OUTPUT (DOUT)
Output High Voltage V
OH
I
SOURCE
= 200µA
0.85 x
V
VDD
V
Output Low Voltage V
OL
I
SINK
= 200µA
0.15 x
V
VDD
V
High-Impedance Leakage
Current
I
OL
Q1.0 FA
High-Impedance Output
Capacitance
C
OUT
4 pF
POWER SUPPLY
Positive Supply Voltage V
DD
2.2 3.6 V
Positive Supply Current
(Full-Power Mode)
I
VDD
V
AIN
= V
GND
1.76 mA
Positive Supply Current
(Full-Power Mode), No Clock
I
VDD
1.48 mA
Power-Down Current I
PD
Leakage only 1.3 10
FA
Line Rejection V
DD
= 2.2V to 3.6V 0.17 LSB/V
TIMING CHARACTERISTICS (Note 2)
Quiet Time t
Q
(Note 3) 4 ns
CS Pulse Width
t
1
(Note 3) 10 ns
CS Fall to SCLK Setup
t
2
(Note 3) 5 ns
CS Falling Until DOUT High-
Impedance Disabled
t
3
(Note 3) 1 ns
Data Access Time After SCLK
Falling Edge
t
4
Figure 2, V
DD
= 2.2V to 3.6V 15 ns
SCLK Pulse Width Low t
5
Percentage of clock period (Note 3) 40 60 %
SCLK Pulse Width High t
6
Percentage of clock period (Note 3) 40 60 %
Data Hold Time From SCLK
Falling Edge
t
7
Figure 3 5 ns
SCLK Falling Until DOUT High
Impedance
t
8
Figure 4 (Note 3) 2.5 14 ns
Power-Up Time Conversion cycle (Note 3) 1 Cycle