Datasheet

MAX11634–MAX11637
12-Bit, 300ksps ADCs with Differential
Track/Hold, and Internal Reference
_______________________________________________________________________________________ 5
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Externally clocked conversion 208
SCLK Clock Period t
CP
Data I/O 100
ns
SCLK Pulse-Width High t
CH
40 ns
SCLK Pulse-Width Low t
CL
40 ns
SCLK Fall to DOUT Transition t
DOT
C
LOAD
= 30pF 40 ns
CS Rise to DOUT Disable t
DOD
C
LOAD
= 30pF 40 ns
CS Fall to DOUT Enable t
DOE
C
LOAD
= 30pF 40 ns
DIN to SCLK Rise Setup t
DS
40 ns
SCLK Rise to DIN Hold t
DH
0 ns
CS Low to SCLK Setup t
CSS0
40 ns
CS High to SCLK Setup t
CSS1
40 ns
CS High After SCLK Hold t
CSH1
0 ns
CS Low After SCLK Hold t
CSH0
0 4 µs
t
CSPW
CKSEL = 00 40 ns
CNVST Pulse-Width Low
CKSEL = 01 1.4 µs
Voltage conversion 7
CS or CNVST Rise to EOC
Low (Note 11)
Reference power-up 65
µs
TIMING CHARACTERISTICS (Figure 1)
Note 11: This time is defined as the number of clock cycles needed for conversion multiplied by the clock period. If the internal
reference needs to be powered up, the total time is additive. The internal reference is always used for temperature
measurements.
Typical Operating Characteristics
(V
DD
= 3V, V
REF
= 2.5V, f
SCLK
= 4.8MHz, C
LOAD
= 30pF, T
A
= +25°C for MAX11635/MAX11637, unless otherwise noted. V
DD
= 5V,
V
REF
= 4.096V, f
SCLK
= 4.8MHz, C
LOAD
= 30pF, T
A
= +25°C for MAX11634/MAX11636, unless otherwise noted.)
INTEGRAL NONLINEARITY
vs. OUTPUT CODE
MAX11634 toc01
OUTPUT CODE (DECIMAL)
INL (LSB)
307220481024
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1.0
-1.0
04096
MAX11634/MAX11636
f
SAMPLE
= 300ksps
INTEGRAL NONLINEARITY
vs. OUTPUT CODE
MAX11634 toc02
OUTPUT CODE (DECIMAL)
INL (LSB)
307220481024
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1.0
-1.0
04096
MAX11635/MAX11637
f
SAMPLE
= 300ksps
DIFFERENTIAL NONLINEARITY
vs. OUTPUT CODE
MAX11634 toc03
OUTPUT CODE (DECIMAL)
DNL (LSB)
307220481024
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1.0
-1.0
0 4096
MAX11634/MAX11636
f
SAMPLE
= 300ksps