Datasheet

4Maxim Integrated
MAX11321–MAX11328
1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
ELECTRICAL CHARACTERISTICS (MAX11322/MAX11325/MAX11328) (continued)
(V
DD
= 2.35V to 3.6V, V
OVDD
= 1.5V to 3.6V, f
SAMPLE
= 1Msps, f
SCLK
= 16MHz, 50% duty cycle, V
REF+
= V
DD
, T
A
= -40NC to +125NC,
unless otherwise noted. Typical values are at T
A
= +25NC.) (Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Input Leakage Current I
IN
V
AIN
= 0V or V
DD
Q0.09 Q1.0 FA
Input Capacitance C
IN
3 pF
DIGITAL OUTPUTS (DOUT, EOC)
Output Voltage Low V
OL
I
SINK
= 200FA
V
OVDD
O 0.15
V
Output Voltage High V
OH
I
SOURCE
= 200FA
V
OVDD
O 0.85
V
Three-State Leakage Current I
L
CS = V
DD
-0.3 Q1.5 FA
Three-State Output Capacitance C
OUT
CS = V
DD
4 pF
POWER REQUIREMENTS
Positive Supply Voltage V
DD
2.35 3.0 3.6 V
Digital I/O Supply Voltage V
OVDD
1.5 3.0 3.6 V
Positive Supply Current I
DD
f
SAMPLE
= 1Msps 1.8 2.5
mAf
SAMPLE
= 0Msps (1Msps devices) 1
Full shutdown 0.0015 0.006
Power Dissipation
Normal mode
(External
Reference)
V
DD
= 3V,
f
SAMPLE
= 1Msps
5.4
mW
V
DD
= 2.35V,
f
SAMPLE
= 1Msps
3.8
AutoStandby
V
DD
= 3V,
f
SAMPLE
= 1Msps
2.6
V
DD
= 2.35V,
f
SAMPLE
= 1Msps
1.6
Full/
AutoShutdown
V
DD
= 3V 4.5
FW
V
DD
= 2.35V 2.1
TIMING CHARACTERISTICS (Figure 1) (Note 11)
SCLK Clock Period t
CP
Externally clocked conversion 62.4 ns
SCLK Duty Cycle t
CH
40 60 %
SCLK Fall to DOUT Transition t
DOT
C
LOAD
=
10pF
V
OVDD
= 1.5V to 2.35V 4 16.5
ns
V
OVDD
= 2.35V to 3.6V 4 15
16th SCLK Fall to DOUT Disable t
DOD
C
LOAD
= 10pF, channel ID on 15 ns
14th SCLK Fall to DOUT Disable C
LOAD
= 10pF, channel ID off 16 ns
SCLK Fall to DOUT Enable t
DOE
C
LOAD
= 10pF 14 ns
DIN to SCLK Rise Setup t
DS
4 ns
SCLK Rise to DIN Hold t
DH
1 ns