Datasheet
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Maxim Integrated
│
4
MAX11200/MAX11210 24-Bit, Single-Channel, Ultra-Low-Power,
Delta-Sigma ADCs with GPIO
Electrical Characteristics (continued)
(V
AVDD
= +3.6V, V
DVDD
= +1.7V, V
REFP
- V
REFN
= V
AVDD
; internal clock, single-cycle mode (SCYCLE = 1), T
A
= T
MIN
to T
MAX
,
unless otherwise noted. Typical values are at T
A
= +25NC under normal conditions, unless otherwise noted.)
Note 2: These specifications are not fully tested and are guaranteed by design and/or characterization.
Note 3: V
AINP
= V
AINN.
Note 4: ppmFSR is parts per million of full scale.
Note 5: Positive full-scale error includes zero-scale errors (unipolar offset error or bipolar zero error) and applies to both unipolar
and bipolar input ranges.
Note 6: For data rates (1, 2.5, 5, 10, 15)sps and (0.83, 2.08, 4.17, 8.33, 12.5)sps.
Note 7: Normal-mode rejection of power line frequencies of 60Hz/50Hz apply only for single-cycle data rates at 15sps/10sps and
lower or continuous data rate of 60sps/50sps.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
POWER REQUIREMENTS
Analog Supply V
AVDD
2.7 3.6 V
Digital Supply V
DVDD
1.7 3.6 V
Total Operating Current AVDD + DVDD
Buffers disabled 235 300
FA
Buffers enabled 255
AVDD Sleep Current 0.15 2 FA
AVDD Operating Current
Buffers disabled 185 235
FA
Buffers enabled 205
DVDD Sleep Current 0.25 2 FA
DVDD Operating Current 50 65 FA
SPI TIMING CHARACTERISTICS
SCLK Frequency f
SCLK
5 MHz
SCLK Clock Period t
CP
200 ns
SCLK Pulse-Width High t
CH
80 ns
SCLK Pulse-Width Low t
CL
60% duty cycle at 5MHz 80 ns
CS Low to 1st SCLK Rise Setup t
CSS0
40 ns
CS High to 17th SCLK Setup t
CSS1
40 ns
CS High After 16th SCLK Falling
Edge Hold
t
CSH1
3 ns
CS Pulse-Width High t
CSW
40 ns
DIN to SCLK Setup t
DS
40 ns
DIN Hold After SCLK t
DH
0 ns
RDY/DOUT Transition Valid After
SCLK Fall
t
DOT
Output transition time, data changes on
falling edge of SCLK
40 ns
RDY/DOUT Remains Valid After
SCLK Fall
t
DOH
Output hold time allows for negative edge
data read
3 ns
RDY/DOUT Valid Before SCLK Rise t
DOL
t
DOL
= t
CL
- t
DOT
40 ns
CS Rise to RDY/DOUT Disable t
DOD
C
LOAD
= 20pF 25 ns
CS Fall to RDY/DOUT Valid t
DOE
Default value of RDY is 1 for minimum
specification; maximum specification for
valid 0 on RDY/DOUT
0 40 ns
DATA Fetch t
DF
Maximum time after RDY asserts to read
DATA register; t
CNV
is the time for one
conversion
0
t
CNV
-
60 x t
CP