Datasheet

12 Maxim Integrated
2Msps/3Msps, Low-Power,
Serial 12-/10-/8-Bit ADCs
MAX11102/03/05/06/10/11/15/16/17
ELECTRICAL CHARACTERISTICS (MAX11111) (continued)
(V
DD
= 2.2V to 3.6V, V
REF
= V
DD
, V
OVDD
= V
DD
, f
SCLK
= 48MHz, 50% duty cycle, 3Msps, C
DOUT
= 10pF, T
A
= -40NC to +125NC,
unless otherwise noted. Typical values are at T
A
= +25NC.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DIGITAL INPUTS (SCLK, CS)
Digital Input High Voltage V
IH
0.75 x
V
OVDD
V
Digital Input Low Voltage V
IL
0.25 x
V
OVDD
V
Digital Input Hysteresis V
HYST
0.15 x
V
OVDD
V
Digital Input Leakage Current I
IL
Inputs at GND or V
DD
0.001 Q1 FA
Digital Input Capacitance C
IN
2 pF
DIGITAL OUTPUT (DOUT)
Output High Voltage V
OH
I
SOURCE
= 200µA (Note 2)
0.85 x
V
OVDD
V
Output Low Voltage V
OL
I
SINK
= 200µA (Note 2)
0.15 x
V
OVDD
V
High-Impedance Leakage
Current
I
OL
Q1.0 FA
High-Impedance Output
Capacitance
C
OUT
4 pF
POWER SUPPLY
Positive Supply Voltage V
DD
2.2 3.6 V
Digital I/O Supply Voltage V
OVDD
1.5 V
DD
V
Positive Supply Current
(Full-Power Mode)
I
VDD
V
AIN_
= V
GND
3.3
mA
I
OVDD
V
AIN_
= V
GND
0.33
Positive Supply Current
(Full-Power Mode), No Clock
I
VDD
1.98 mA
Power-Down Current I
PD
Leakage only 1.3 10 FA
Line Rejection V
DD
= +2.2V to +3.6V, V
REF
= 2.2V 0.17 LSB/V
TIMING CHARACTERISTICS (Note 1)
Quiet Time t
Q
(Note 2) 4 ns
CS Pulse Width t
1
(Note 2) 10 ns
CS Fall to SCLK Setup t
2
(Note 2) 5 ns
CS Falling Until DOUT High-
Impedance Disabled
t
3
(Note 2) 1 ns
Data Access Time After SCLK
Falling Edge (Figure 2)
t
4
V
OVDD
= 2.2V - 3.6V 15
ns
V
OVDD
= 1.5V - 2.2V 16.5
SCLK Pulse Width Low t
5
Percentage of clock period (Note 2) 40 60 %
SCLK Pulse Width High t
6
Percentage of clock period (Note 2) 40 60 %
Data Hold Time From SCLK
Falling Edge
t
7
Figure 3 5 ns
SCLK Falling Until DOUT High-
Impedance
t
8
Figure 4 (Note 2) 2.5 14 ns
Power-Up Time Conversion cycle (Note 2) 1 Cycle