Datasheet

10 Maxim Integrated
2Msps/3Msps, Low-Power,
Serial 12-/10-/8-Bit ADCs
MAX11102/03/05/06/10/11/15/16/17
ELECTRICAL CHARACTERISTICS (MAX11110/MAX11117) (continued)
(V
DD
= 2.2V to 3.6V. MAX11110: f
SCLK
= 32MHz, 50% duty cycle, 2Msps. MAX11117: f
SCLK
= 48MHz, 50% duty cycle, 3Msps.
C
DOUT
= 10pF, T
A
= -40NC to +125NC, unless otherwise noted. Typical values are at T
A
= +25NC.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DIGITAL OUTPUT (DOUT)
Output-High Voltage V
OH
I
SOURCE
= 200µA
0.85 x
V
DD
V
Output-Low Voltage V
OL
I
SINK
= 200µA
0.15 x
V
DD
V
High-Impedance Leakage
Current
I
OL
Q1.0 FA
High-Impedance Output
Capacitance
C
OUT
4 pF
POWER SUPPLY
Positive Supply Voltage V
DD
2.2 3.6 V
Positive Supply Current
(Full-Power Mode)
I
VDD
MAX11117, V
AIN
= V
GND
3.55
mA
MAX11110, V
AIN
= V
GND
2.6
Positive Supply Current
(Full-Power Mode), No Clock
I
VDD
MAX11117 1.98
mA
MAX11110 1.48
Power-Down Current I
PD
Leakage only 1.3 10 FA
Line Rejection V
DD
= +2.2V to +3.6V 0.17 LSB/V
TIMING CHARACTERISTICS (Note 1)
Quiet Time t
Q
(Note 2) 4 ns
CS Pulse Width t
1
(Note 2) 10 ns
CS Fall to SCLK Setup t
2
(Note 2) 5 ns
CS Falling Until DOUT High-
Impedance Disabled
t
3
(Note 2) 1 ns
Data Access Time After SCLK
Falling Edge
t
4
Figure 2, V
DD
= +2.2V to +3.6V 15 ns
SCLK Pulse Width Low t
5
Percentage of clock period (Note 2) 40 60 %
SCLK Pulse Width High t
6
Percentage of clock period (Note 2) 40 60 %
Data Hold Time From SCLK
Falling Edge
t
7
Figure 3 5 ns
SCLK Falling Until DOUT High-
Impedance
t
8
Figure 4 (Note 2) 2.5 14 ns
Power-Up Time Conversion cycle (Note 2) 1 Cycle