Manual

High-Speed Microcontroller User’s Guide
Rev: 062210 112 of 176
10. PARALLEL I/O
The high-speed microcontroller method of implementing I/O ports follows the standard 8051 convention.
This provides backward compatibility with existing designs. All drive capabilities exceed or equal the
original 80C32
, and voltage levels are compatible. The transitions between strong and weak drives are
similar but not identical. Differences are to accommodate higher speed timing and the associated
demands on slew rates. As with any new technology, the high-speed microcontroller should be evaluated
in a system to see how subtle differences affect operation.
From a software perspective, each port appears as SFR with a unique address. Each port register is
addressable as a byte or 8 individual bit locations. The CPU distinguishes between a bit access and a byte
access by the instruction type. Except for the special cases mentioned below, the register and port pins
have identical states. Reading or writing a port is the same as reading or writing the SFR for that port.
The microcontroller will distinguish between port and bus operations automatically. If a memory fetch is
decoded and requires external memory, Port 0 and 2 will be driven as a bus with the associated timing
and drive strengths. If either port SFR is accessed, the port pins will revert to the characteristics described
above. This includes a strong pulldown, a strong pullup for transitions, and a weak pullup for static
conditions.
ROMless versions of the high-speed microcontroller dedicate Port 0 and 2 as the memory interface bus.
The Port 0 latch does not exist on ROMless devices. The functions of these ports are described in more
detail in the specific sections.
10.1 Port 0
10.1.1 General-Purpose I/O
Devices that have internal program memory have the ability to use Port 0 as a general-purpose I/O. Data
written
to the port latch serves to set both level and direction of the data on the pin. ROMless devices do
not contain a Port 0 latch, because at no time can it be manipulated as a port. When used as an I/O port, it
functions as an open-drain output. More detail on the functions of these pins is provided under the
description of output and input functions in this section.
Even if internal memory is present, the use of Port 0 as general-purpose I/O pins is not recommended if
the device will be used to access external memory. This is because the state of the pins will be disturbed
during the memory access. In addition, the pullups needed to maintain a high state during the use as
general-purpose I/O will interfere with the complementary drivers employed when the device operates as
an expanded memory bus.
10.1.2 Multiplexed Address/Data Bus AD0–AD7
When used to address expanded memory, Port 0 functions as a multiplexed address/data bus. Port 0 must
function as the address/data bus on ROMless devices. Port 0 pins have extremely strong drivers that allow
the bus to move 100pF loads with the timing shown in the electrical specifications. Special circuit
protection allows these pins to achieve the maximum slew rate without ringing, eliminating excessive
noise or interface problems. Users that compare the high-speed microcontroller family to 80C32 devices
will find improved drive capability. This power is available for dynamic switching only, and should not
be used to drive heavy DC loads such as LEDs.