Datasheet

DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers

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Note that there are a few exceptions for this mode of operation when PAGES1 and PAGES2 are set to 00b:

 PSEN is asserted for both a page hit and a page miss for a full clock cycle.

 The execution of external MOVX instruction causes a page miss.

 A page miss occurs when fetching the next external instruction following the execution of an external MOVX

instruction.

Figure 10

shows the external memory cycle for this bus structure. The first case illustrates a back-to-back

execution sequence for the one-cycle page mode (PAGES1 = PAGES0 = 0b). PSEN remains active during page hit

cycles, and page misses are forced during and after MOVX executions, independent of the most significant byte of

the subsequent addresses. The second case illustrates a MOVX execution sequence for two-cycle page mode

(PAGES1 = 0 and PAGES0 = 1). PSEN is active for a full clock cycle in code fetches. Note that changing the most

significant byte of the data address causes the page misses in this sequence. The third case illustrates a MOVX

execution sequence for four-cycle page mode (PAGES1 = 1 and PAGES0 = 0). There is no page miss in this

execution cycle as the most significant byte of the data address is assumed to match the last program address.

The second page mode (page mode 2) external bus structure multiplexes the most significant address byte with

data on P2 and uses P0 for the least significant address byte. This bus structure is used to speed up external code

fetches only. External data memory access cycles are identical to the nonpage mode except for the different

signals on P0 and P2. Figure 11

illustrates the memory cycle for external code fetches.

Figure 11. Page Mode 2, External Code Fetch Cycle (CD1:CD0 = 10)

Internal Memory Cycles

C2 C3 C4 C1 C2 C1 C2

XTAL1

ALE

Port 0

Port 2

SEN

Ext Code Fetches

Page Miss Page Hit

Page Hit

Data

LSB Add

LSB Add LSB Add

DataMSB Add

Stretch External Data Memory Cycle in Page Mode

The DS89C430 allows software to adjust the speed of external data memory access by stretching the memory bus

cycle in page mode operation just like nonpage mode operation. The following tables summarize the stretch values

and their effect on the external MOVX memory bus cycle and the control signals’ pulse width in terms of the

number of oscillator clocks. A stretch machine cycle always contains four system clocks, independent of the logic

value of the page mode select bits.