Owner manual

DS4830 User’s Guide
141
18.3 – Register Output Selection
The Hardware Multiplier implements the MC Register Write Select (MCW) control bit so that writing of the result to the
MC2:MC0 registers can be blocked to preserve the MC registers (accumulator). When the MCW bit is configured to logic
1, the result for the given operation is not written to the MC registers. When the MCW bit is configured to logic 0, the MC
registers are updated with the result of the operation. The MC1R, MC0R read-only register pair are updated independent
of the MCW bit setting. This register pair always reflects the output that would normally be placed in MC1:MC0, given that
MCW = 1 or MMAC = 0. When MCW = 0 and MMAC = 1, the MC1R:MC0R content may not match the MC1:MC0 register
content, but it will be predictable and may be useful in certain situations. See Table 18-1 for details.
18.3.1 – Signed-Unsigned Operand Selection
The operands can be either signed or unsigned numbers, but the data type must be defined by the user software via the
Signed-Unsigned (SUS) bit prior to triggering the operation. For an unsigned operation, the Signed-Unsigned bit (SUS) in
the MCNT register must be set to 1; for a signed operation, the SUS bit must be cleared to 0. The multiplier treats
unsigned numbers as absolute magnitude. For a 16-bit positional binary number, this represents a value in the range 0 to
2
16
- 1 (FFFFh). The signed number representation is a two's-complement value, where the most significant bit is defined
as a sign bit. The range of a 16-bit two's-complement number is -2
(16-1)
(8000h) to +2
(16-1)
- 1 (7FFFh). The product of any
signed operation will be sign extended before being stored or accumulated/subtracted into the MC registers. The SUS bit
should always be configured to logic 0 (i.e., signed operands) for the multiply-negate operation. Attempting an unsigned
multiply-negate operation results in incorrect results and setting of the OF bit. Modifying the operand data type selection
via the SUS bit does not alter the contents of the MC registers. The MC registers are read/write accessible and can be
modified by user code when necessary.
18.3.2 – Operand Count Selection
The OPCS bit allows selection of single operand or two operands operation for the multiply and multiply-
accumulate/subtract operations. When the OPCS bit is cleared to 0, the multiply or multiply-accumulate/subtract operation
established by the SUS, MSUB, and MMAC bits is triggered once two operands are loaded, one to each of the MA and
MB registers. When OPCS is set to 1, the operation commences once data is loaded to either MA or MB. The OPCS bit is
ignored when the square operation is enabled (SQU), since loading of data to the MA or MB register actually writes to
both registers.
18.4 – Hardware Multiplier Operations
The control bits, which specify data type (SUS), operand count (OPCS or SQU), and destination control (MCW), have
already been described. However, there are two additional MCNT register bits that serve to define the Hardware Multiplier
operation. The multiply-accumulate/subtract and multiply-negate operations are enabled by the Multiply-Accumulate
Enable (MMAC) and Multiply Negate (MSUB) bits in the MCNT register. When the MMAC bit is set to 1, the multiplier
performs a multiply-accumulate (if MSUB = 0) or a multiply-subtract (if MSUB = 1). If MMAC is configured to 0, the
multiplier result is not accumulated or subtracted, but can be stored directly (if MSUB = 0) or negated (if MSUB = 1) before
storage. The multiply-negate operation (MMAC = 0, MSUB = 1) is only allowable for signed data operands (SUS = 0). For
unsigned multiply-accumulate/subtract operations, the OF bit is set when a carry-out/borrow-in from the most significant
bit of the MC register occurs. For a signed two’s-complement multiply-accumulate/subtract operations, the OF bit is set
when the carry-out/borrow-in from the most significant magnitude position of the MC register is different from the carryout/
borrow-in of the sign position of the MC register. Since there is no overflow condition for multiply and multiply-negate
operations, the OF bit is always cleared for these operations with one exception. The OF bit will be set to logic 1 if an
unsigned multiply-negate (invalid operation) is requested. Table 18-1 shows the operations supported by the multiplier
and associated MCNT control bit settings.
18.4.1 – Accessing the Multiplier
There are no restrictions on how quickly data is entered into the operand registers or the order of data entry. The only
requirement to do a calculation is to perform the loading of MA and/or MB registers having specified data type and
operation in the MCNT register. The multiplier keeps track of the writes to the MA and MB registers, and starts calculation
immediately after the prescribed number of operands is loaded. If two operands are specified for the operation, the
multiplier waits for the second operand to be loaded into the other operand register before starting the actual calculation. If
for any reason software needs to reload the first operand, it should either reload that same operand register or use the
CLD bit in the MCNT register to reinitialize the multiplier; otherwise, loading data to another operand register triggers the
calculation. The CLD bit is a self-clearing bit that can be used for multiplier initialization. When it is set, it clears all data
registers and the OF bit to zero and resets the multiplier operand write counter.