Datasheet

DS28EC20: 20Kb 1-Wire EEPROM
3 of 27
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
EEPROM
Programming Current
I
PROG
(Note 19)
0.9
mA
Programming Time
t
PROG
(Note 20)
10
ms
Write/Erase Cycles
(Endurance) (Notes 21,
22)
N
CY
At +25°C
200k

At +85°C (worst case) 50k
Data Retention
(Notes 23, 24, 25)
t
DR
At +85°C (worst case) 40 years
Note 1:
Limits are 100% production tested at T
A
= +25°C and/or T
A
= +85°C. Limits over the operating temperature range and relevant
supply voltage range are guaranteed by design and characterization. Typical values are not guaranteed.
Note 2:
System requirement.
Note 3:
Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system, 1-Wire recovery times, and
current requirements during EEPROM programming. The specified value here applies to systems with only one device and with
the minimum 1-Wire recovery times. For more heavily loaded systems, an active pullup such as that found in the DS2482-x00,
DS2480B, or DS2490 may be required.
Note 4:
Typical value represents the internal parasite capacitance when V
PUP
is first applied. Once the parasite capacitance is charged, it
does not affect normal communication.
Note 5:
Guaranteed by design, characterization and/or simulation only. Not production tested.
Note 6:
V
TL
, V
TH
, and V
HY
are a function of the internal supply voltage which is itself a function of V
PUP
, R
PUP
, 1-Wire timing, and
capacitive loading on I/O. Lower V
PUP
, higher R
PUP
, shorter t
REC
, and heavier capacitive loading all lead to lower values of V
TL
, V
TH
,
and V
HY
.
Note 7:
Voltage below which, during a falling edge on I/O, a logic 0 is detected.
Note 8:
The voltage on I/O needs to be less or equal to V
ILMAX
at all times the master is driving I/O to a logic 0 level.
Note 9:
Voltage above which, during a rising edge on I/O, a logic 1 is detected.
Note 10:
After V
TH
is crossed during a rising edge on I/O, the voltage on I/O has to drop by at least V
HY
to be detected as logic 0.
Note 11:
The I-V characteristic is approximately linear for voltages less than 1V.
Note 12:
Applies to a single device attached to a 1-Wire line.
Note 13:
The earliest recognition of a negative edge is possible at t
REH
after V
TH
has been reached on the preceding rising edge.
Note 14:
Defines maximum possible bit rate. Equal to 1/(t
W0LMIN
+ t
RECMIN
).
Note 15:
Interval after t
RSTL
during which a bus master can read a logic 0 on I/O if there is a DS28EC20 present. The power-up presence
detect pulse could be outside this interval but will be complete within 2ms after power-up.
Note 16:
Highlighted numbers are NOT in compliance with legacy 1-Wire product standards. See comparison table below.
Note 17:
ε in Figure 11 represents the time required for the pullup circuitry to pull the voltage on I/O up from V
IL
to V
TH
. The actual
maximum duration for the master to pull the line low is t
W1LMAX
+ t
F
- ε and t
W0LMAX
+ t
F
- ε, respectively.
Note 18:
δ in Figure 11 represents the time required for the pullup circuitry to pull the voltage on I/O up from V
IL
to the input high threshold
of the bus master. The actual maximum duration for the master to pull the line low is t
RLMAX
+ t
F
.
Note 19:
Current drawn from I/O during the EEPROM programming interval. During a programming cycle the voltage at I/O drops by I
PROG
× R
PUP
below V
PUP
. If V
PUP
and R
PUP
are within their EC table limits, the residual I/O voltage meets the guaranteed-by-design
minimum voltage requirements for programming.
Note 20:
The t
PROG
interval begins t
REHMAX
after the trailing rising edge on I/O for the last time slot of the E/S byte for a valid copy scratchpad
sequence. Interval ends once the device's self-timed EEPROM programming cycle is complete and the current drawn by the
device has returned from I
PROG
to I
L
.
Note 21:
Write-cycle endurance is degraded as T
A
increases.
Note 22:
Not 100% production-tested; guaranteed by reliability monitor sampling.
Note 23:
Data retention is degraded as T
A
increases.
Note 24:
Guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production test to data sheet
limit at operating temperature range is established by reliability testing.
Note 25:
EEPROM writes may become nonfunctional after the data retention time is exceeded. Long-time storage at elevated
temperatures is not recommended; the device may lose its write capability after 10 years at +125°C or 40 years at +85°C.
LEGACY VALUES
DS28EC20 VALUES
PARAMETER
STANDARD SPEED
OVERDRIVE SPEED#
STANDARD SPEED
OVERDRIVE SPEED#
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
t
SLOT
(incl. t
REC
)
61µs
(undefined)
7µs
(undefined)
65µs*
(undefined)
11µs
(undefined)
t
RSTL
480µs
(undefined)
48µs
80µs
480µs
640µs
48µs
80µs
t
PDH
15µs
60µs
2µs
6µs
15µs
60µs
2µs
6µs
t
PDL
60µs
240µs
8µs
24µs
60µs
240µs
8µs
24µs
t
W0L
60µs
120µs
6µs
16µs
60µs
120µs
6µs
15.5µs
*Intentional change, longer recovery time requirement due to modified 1-Wire front-end.
#For operation at overdrive speed, the DS28EC20 requires V
PUP
to be 5V ±5%.