Datasheet

DS28EC20: 20Kb 1-Wire EEPROM
24 of 27
CRC GENERATION
The DS28EC20 uses two different types of CRCs. One CRC is an 8-bit type and is stored in the most significant
byte of the 64-bit ROM. The bus master can compute a CRC value from the first 56 bits of the 64-bit ROM and
compare it to the value stored within the DS28EC20 to determine if the ROM data has been received error-free.
The equivalent polynomial function of this CRC is X
8
+ X
5
+ X
4
+ 1. This 8-bit CRC is received in the true
(noninverted) form. It is computed at the factory and programmed into the ROM.
The other CRC is a 16-bit type, generated according to the standardized CRC16 polynomial function
X
16
+ X
15
+ X
2
+ 1. This CRC is used for fast verification of a data transfer when writing to or reading from the
scratchpad and with the Extended Read Memory command. In contrast to the 8-bit CRC, the 16-bit CRC is always
communicated in the inverted form. A CRC generator inside the DS28EC20 (Figure 13) calculates a new 16-bit
CRC, as shown in the command flowchart (Figure 7). The bus master compares the CRC value read from the
device to the one it calculates from the data, and decides whether to continue with an operation or to reread the
portion of the data with the CRC error.
With the Write Scratchpad command, the CRC is generated by first clearing the CRC generator and then shifting in
the command code, the target addresses TA1 and TA2, and all the data bytes as they were sent by the bus
master. The DS28EC20 transmits this CRC only if the data bytes written to the scratchpad include scratchpad
ending offset 11111b. The data can start at any location within the scratchpad.
With the Read Scratchpad command, the CRC is generated by first clearing the CRC generator and then shifting in
the command code, the target addresses TA1 and TA2, the E/S byte, and the scratchpad data as they were sent
by the DS28EC20 starting at the target address. The DS28EC20 transmits this CRC only if the reading continues
through the end of the scratchpad, regardless of the actual ending offset.
With the initial pass through the extended read memory flow, the 16-bit CRC value is the result of shifting the
command byte into the cleared CRC generator, followed by the two address bytes and the data bytes. Subsequent
passes through the extended read memory flow generate a 16-bit CRC that is the result of clearing the CRC
generator and then shifting in the data bytes. For more information on generating CRC values refer to Application
Note 27: Understanding and Using Cyclic Redundancy Checks with Maxim iButton Products
(
www.maximintegrated.com/AN27).
Figure 13. CRC16 Hardware Description and Polynomial
Polynomial = X
16
+ X
15
+ X
2
+ 1
X
0
X
1
X
2
X
3
X
4
X
5
X
6
X
7
X
8
X
9
X
10
X
11
X
12
X
13
X
14
X
15
X
16
1
st
STAGE
2
nd
STAGE
3
rd
STAGE
4
th
STAGE
6
th
STAGE
5
th
STAGE
7
th
STAGE
8
th
STAGE
9
th
STAGE
10
th
STAGE
11
th
STAGE
12
th
STAGE
13
th
STAGE
14
th
STAGE
15
th
STAGE
16
th
STAGE
INPUT DATA
CRC
OUTPUT