Datasheet

DS2782
4 of 28
Note 1: All voltages are referenced to V
SS
.
Note 2: To properly enter sleep mode the application should hold the bus low for longer than the maximum t
SLEEP
.
Note 3: Factory calibrated accuracy. Higher accuracy can be achieved by in-system calibration by the user.
Note 4: Accumulation bias register set to 00h.
Note 5: Parameters guaranteed by design.
Note 6: Timing must be fast enough to prevent the DS2782 from entering sleep mode due to bus low for period >
t
SLEEP
.
Note 7: f
SCL
must meet the minimum clock low time plus the rise/fall times.
Note 8: The maximum t
HD:DAT
has only to be met if the device does not stretch the LOW period (t
LOW
) of the SCL
signal.
Note 9: This device internally provides a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of
the SCL signal) to bridge the undefined region of the falling edge of SCL.
Note 10: Filters on SDA and SCL suppress noise spikes at the input buffers and delay the sampling instant.
Note 11: C
B
– total capacitance of one bus line in pF.
Figure 1. I
2
C Bus Timing Diagram