Datasheet

DS26518 8-Port T1/E1/J1 Transceiver

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9.10.3.1 HDLC-256 FIFO Control

Control of the transmit and receive FIFOs is accomplished via the Receive HDLC-256 Control Register 2

(

RH256CR2) and Transmit HDLC-256 Control Register 2 (TH256CR2). The FIFO control registers set the

watermarks for the FIFO.

When the receive FIFO fills above the data available level, the RHDA bit (

RH256SR.0) is set. RHDA and THDA are

real-time bits and remain set as long as the FIFO’s write pointer is above the data available level. When the

transmit FIFO empties below the data storage available level , the THDA bit in the

TH256SR1 register is set. THDA

is a real-time bit and remains set as long as the transmit FIFO’s write pointer is below the level setting. If enabled,

this condition can also cause an interrupt via the INTB pin.

If a packet start is received while the receive FIFO is full, the data is discarded and an FIFO overflow condition is

declared (

RH256SRL.7). If any other packet data is received while full, the current packet being transferred is

marked with an abort indication, and a FIFO overflow condition is declared. Once an FIFO overflow condition is

declared, the receive FIFO discards incoming data until a packet start is received while the receive FIFO has 16 or

more bytes available for storage. If the receive FIFO is read while the FIFO is empty, the read is ignored and an

invalid data indication given.

The transmit FIFO accepts data from the host until full. If the transmit FIFO is written to while the FIFO is full, the

write is ignored, and an FIFO overflow condition is declared. If the transmit HDLC-256 controller attempts to read

the transmit FIFO while it is empty, an FIFO underflow condition is declared.

The transmit FIFO fill level is available real-time in the Transmit HDLC-256 Status Register 2 (

TH256SR2),

indicating the number of bytes that can be written into the transmit FIFO.

9.10.3.2 HDLC-256 Status and Information

RH256SRL, RH256SR, TH256SR1, TH256SR2, and TH256SRL provide status information for the HDLC-256

controller. When a particular event has occurred (or is occurring), the appropriate bit in one of these registers is set

to a 1. Some of the bits in these registers are latched and some are real-time bits that are not latched. This section

contains register descriptions that list which bits are latched and which are real-time. With the latched bits, when an

event occurs and a bit is set to a one, it remains set until the user reads and clears that bit. The bit is cleared when

a 1 is written to the bit and it is not set again until the event has occurred again. The real-time bits report the current

instantaneous conditions that are occurring and the history of these bits is not latched.

Like the other latched status registers, the user follows a read of the status bit with a write. The byte written to the

writing to the status register). The user writes a byte to one of these registers, with a 1 in the bit positions he or she

wishes to clear and a 0 in the bit positions he or she does not wish to clear.

The HDLC-256 status registers

RH256SRL and TH256SRL can initiate a hardware interrupt via the INTB output

signal. Each of the events in this register can be either masked or unmasked from the interrupt pin via the

HDLC-256 interrupt enable registers,

TH256SRIE and RH256SRIE. Interrupts force the INTB signal low when the

event occurs. The INTB pin is allowed to return high (if no other interrupts are present) when the user reads the

event bit that caused the interrupt to occur.