Datasheet

DS2155
202 of 238
Figure 34-2. TAP Controller State Diagram
34.2 Instruction Register
The instruction register contains a shift register as well as a latched parallel output and is 3 bits in length.
When the TAP controller enters the Shift-IR state, the instruction shift register is connected between JTDI
and JTDO. While in the Shift-IR state, a rising edge on JTCLK with JTMS LOW shifts the data one stage
toward the serial output at JTDO. A rising edge on JTCLK in the Exit1-IR state or the Exit2-IR state with
JTMS HIGH moves the controller to the Update-IR state. The falling edge of that same JTCLK latches
the data in the instruction shift register to the instruction parallel output. Instructions supported by the
DS2155 and its respective operational binary codes are shown in Table 17-A.
1
0
0
1
11
1
1
1
11
11
11
00
0
0
0
1
0
0
00
1
1
00
0
0
Select
DR-Scan
Capture DR
Shift DR
Exit DR
Pause DR
Exit2 DR
Update DR
Select
IR-Scan
Capture IR
Shift IR
Exit IR
Pause IR
Exit2 IR
Update IR
Test Logic
Reset
Run Test/
Idle
0