Datasheet

DS21455/DS21458 Quad T1/E1/J1 Transceivers
44 of 269
ADDRESS REGISTER NAME
REGISTER
ABBREVIATION
PAGE
94 HDLC #1 Receive Channel Select 3 H1RCS3 146
95 HDLC #1 Receive Channel Select 4 H1RCS4 146
96 HDLC #1 Receive Time Slot Bits/Sa Bits Select H1RTSBS 147
97 HDLC #1 Transmit Channel Select1 H1TCS1 148
98 HDLC #1 Transmit Channel Select 2 H1TCS2 148
99 HDLC #1 Transmit Channel Select 3 H1TCS3 148
9A HDLC #1 Transmit Channel Select 4 H1TCS4 148
9B HDLC #1 Transmit Time Slot Bits/Sa Bits Select H1TTSBS 149
9C HDLC #1 Receive Packet Bytes Available H1RPBA 153
9D HDLC #1 Transmit FIFO H1TF 154
9E HDLC #1 Receive FIFO H1RF 154
9F HDLC #1 Transmit FIFO Buffer Available H1TFBA 153
A0 HDLC #2 Transmit Control H2TC 143
A1 HDLC #2 FIFO Control H2FC 145
A2 HDLC #2 Receive Channel Select 1 H2RCS1 146
A3 HDLC #2 Receive Channel Select 2 H2RCS2 146
A4 HDLC #2 Receive Channel Select 3 H2RCS3 146
A5 HDLC #2 Receive Channel Select 4 H2RCS4 146
A6 HDLC #2 Receive Time Slot Bits/Sa Bits Select H2RTSBS 147
A7 HDLC #2 Transmit Channel Select 1 H2TCS1 148
A8 HDLC #2 Transmit Channel Select 2 H2TCS2 148
A9 HDLC #2 Transmit Channel Select 3 H2TCS3 148
AA HDLC #2 Transmit Channel Select 4 H2TCS4 148
AB HDLC #2 Transmit Time Slot Bits/Sa Bits Select H2TTSBS 149
AC HDLC #2 Receive Packet Bytes Available H2RPBA 153
AD HDLC #2 Transmit FIFO H2TF 154
AE HDLC #2 Receive FIFO H2RF 154
AF HDLC #2 Transmit FIFO Buffer Available H2TFBA 153
B0 Extend System Information Bus Control Register 1 ESIBCR1 205
B1 Extend System Information Bus Control Register 2 ESIBCR2 206
B2 Extend System Information Bus Register 1 ESIB1 207
B3 Extend System Information Bus Register 2 ESIB2 207
B4 Extend System Information Bus Register 3 ESIB3 207
B5 Extend System Information Bus Register 4 ESIB4 207
B6 In-Band Code Control Register IBCC 180
B7 Transmit Code Definition Register 1 TCD1 181
B8 Transmit Code Definition Register 2 TCD2 181
B9 Receive Up Code Definition Register 1 RUPCD1 182
BA Receive Up Code Definition Register 2 RUPCD2 182
BB Receive Down Code Definition Register 1 RDNCD1 183
BC Receive Down Code Definition Register 2 RDNCD2 184
BD In-Band Receive Spare Control Register RSCC 184
BE Receive Spare Code Definition Register 1 RSCD1 185
BF Receive Spare Code Definition Register 2 RSCD2 185
C0 Receive FDL Register RFDL 156
C1 Transmit FDL Register TFDL 157
C2 Receive FDL Match Register 1 RFDLM1 156
C3 Receive FDL Match Register 2 RFDLM2 156
C4 Unused. Must be set = 00h for proper operation — —
C5 Interleave Bus Operation Control Register IBOC 200
C6 Receive Align Frame Register RAF 128
C7 Receive Nonalign Frame Register RNAF 128
C8 Receive Si Align Frame RSiAF 130