Datasheet

DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
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3.1. Pin Function Description
3.1.1. Transmit-Side Pins
Signal Name:
TCLK
Signal Description:
Transmit Clock
Signal Type:
Input
A 2.048MHz primary clock. Used to clock data through the transmit side formatter.
Signal Name:
TSER
Signal Description:
Transmit Serial Data
Signal Type:
Input
Transmit NRZ serial data. Sampled on the falling edge of TCLK when the transmit side elastic store is
disabled. Sampled on the falling edge of TSYSCLK when the transmit side elastic store is enabled.
Signal Name:
TCHCLK
Signal Description:
Transmit Channel Clock
Signal Type:
Output
A 256kHz clock that pulses high during the LSB of each channel. Synchronous with TCLK when the
transmit side elastic store is disabled. Synchronous with TSYSCLK when the transmit side elastic store is
enabled. Useful for parallel to serial conversion of channel data.
Signal Name:
TCHBLK
Signal Description:
Transmit Channel Block
Signal Type:
Output
A user-programmable output that can be forced high or low during any of the 32 E1 channels.
Synchronous with TCLK when the transmit side elastic store is disabled. Synchronous with TSYSCLK
when the transmit-side elastic store is enabled. Useful for blocking clocks to a serial UART or LAPD
controller in applications where not all E1 channels are used such as Fractional E1, 384kbps (H0),
768kbps, or ISDN–PRI. Also useful for locating individual channels in drop-and-insert applications, for
external per-channel loopback, and for per-channel conditioning. See Section 12 for details.
Signal Name:
TSYSCLK
Signal Description:
Transmit System Clock
Signal Type:
Input
1.544MHz, 2.048MHz, 4.096MHz, or 8.192MHz clock. Only used when the transmit-side elastic store
function is enabled. Should be tied low in applications that do not use the transmit-side elastic store. See
Section 17
for details on 4.096MHz and 8.192MHz operation using the Interleave Bus Option.
Signal Name:
TLCLK
Signal Description:
Transmit Link Clock
Signal Type:
Output
4kHz to 20kHz demand clock (Sa bits) for the TLINK input. See Section 17 for details.