Datasheet

DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
122 of 124
Figure 20-11. Transmit-Side AC Timing
t
F
t
R
1
TCLK
TSER / TSIG /
TDATA
TCHCLK
t
t
CL
t
CH
CP
TSYNC
TSYNC
TLINK
TLCLK
TCHBLK
t
D2
t
D2
t
D2
t
t
t
t
t
t
HD
SU
D2
SU
HD
D1
t
HD
2
Notes:
1. TSYNC is in the output mode (TCR1.0 = 1).
2. TSYNC is in the input mode (TCR1.0 = 0).
3. TSER is sampled on the falling edge of TCLK when the transmit side elastic store is disabled.
4. TCHCLK and TCHBLK are synchronous with TCLK when the transmit side elastic store is disabled.
5. TLINK is only sampled during Sa bit locations as defined in TCR2; no relationship between
TLCLK/TLINK and TSYNC is implied.
5
TESO
t
SU