Datasheet

DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
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Figure 18-9. Transmit-Side 1.544MHz Boundary Timing (with Elastic Store Enabled)
Figure 18-10. Transmit-Side 2.048MHz Boundary Timing (with Elastic Store Enabled)
LSB F MSBLSB MSB
CHANNEL 1CHANNEL 24
TSYSCLK
TSER
TSSYNC
TCHCLK
TCHBLK
CHANNEL 23
1
2
NOTE 1: THE F-BIT POSITION IN THE TSER DATA IS IGNORED.
NOTE 2: TCHBLK IS PROGRAMMED TO BLOCK CHANNEL 24.
NOTE 1: TCHBLK IS PROGRAMMED TO BLOCK CHANNEL 31.
TSER
LSB MSB
LSB
CHANNEL 1
TCHCLK
TCHBLK
TSYSCLK
TSSYNC
CHANNEL 31 CHANNEL 32
TSIG
D D
CHANNEL 1 CHANNEL 31 CHANNEL 32
C
B
A
C B
A
1
MSB
A