Datasheet

DS21348/DS21Q348
22 of 76
Table 2-13. MCLK Selection
MCLK
(MHz)
JAMUX
(CCR1.3)
ETS
(CCR1.7)
2.048 0 0
2.048 1 1
1.544 0 1
Figure 2-1. Parallel Port Mode Pinout (BIS1 = 0, BIS0 = 1 or 0) (TQFP
Package)
1
C
S
2 RD (DS)
3
W
R (R/
W
)
4 ALE (AS)
5 NA
6 NA
7 A4
8 A3
9 A2
10 A1
11 A0
BIS1 33
BIS0 32
BPCLK 31
MCLK 30
H
RST 29
RRING 28
RTIP 27
TEST 26
RCL/LOTC 25
PBEO 24
I
NT 23
34 TTIP 35 VSS
36 VDD
37 TRING 38 RPOS 39 RNEG 40 RCLK 41 TPOS 42 TNEG 43 TCLK
44 PBTS
VSS 22
VDD 21
VSM 20
A
D0/D0 19
A
D1/D1 18
A
D2/D2 17
A
D3/D3 16
A
D4/D4 15
A
D5/D5 14
A
D6/D6 13
A
D7/D7 12
DS21348
Parallel Port
Operation
(NOTE: TIE ALL NA PINS LOW)
tie low
TIE LOW (MUX) OR HIGH (NONMUX)
TIE LOW