Datasheet

DS21348/DS21Q348
16 of 76
NAME PIN I/O FUNCTION
TTIP/
TRING
34/37 O
Transmit Tip and Ring [TTIP AND TRING]. Analog line driver
outputs. These pins connect via a step-up transformer to the line. See
Section 5
for details.
VDD 21/36 — Positive Supply. 3.3V ±5%
VSM 20 I Voltage Supply Mode. Should be low for 3.3V operation.
VSS 22/35 —
Signal Ground
WR (R/W)
3 I
Write Input (Read/Write), Active Low. See the bus timing
diagrams in Section 11.
Table 2-6. Pin Descriptions in Serial Port Mode (Sorted By Pin Name,
DS21348T Pin Numbering)
NAME PIN I/O FUNCTION
BIS0/BIS1 32/33 I
Bus Interface Select Bits 0 and 1. Used to select bus interface
option. See Table 2-1 for details.
BPCLK 31 O
Backplane Clock. A 16.384MHz, 8.192MHz, 4.096MHz, or
2.048MHz clock output that is referenced to RCLK selectable via
CCR5.7 and CCR5.6. In hardware mode, defaults to 16.384MHz
output.
CS
1 I
Chip Select, Active Low. Active-low signal must be low to read or
write to the device.
HRST
29 I
Hardware Reset, Active Low. Bringing HRST low will reset the
DS21348 setting all control bits to their default state of all zeros.
ICES 8 I
Input Clock Edge Select. Selects whether the serial port data input
(SDI) is sampled on rising (ICES =0) or falling edge (ICES = 1) of
SCLK.
INT
23 O
Interrupt, Active Low. Flags host controller during conditions and
change of conditions defined in the Status Register. Active-low,
open-drain output.
MCLK 30 I
Master Clock. A 2.048MHz (±50ppm) clock source with TTL
levels is applied at this pin. This clock is used internally for both
clock/data recovery and for jitter attenuation. Use of a T1 1.544MHz
clock source is optional.
NA — I Not Assigned. Should be tied low.
OCES 9 I
Output Clock Edge Select. Selects whether the serial port data
output (SDO) is valid on the rising (OCES = 1) or falling edge
(OCES = 0) of SCLK.
PBEO 24 O
PRBS Bit Error Output. The receiver will constantly search for a
2
15
-1 or a 2
20
-1 PRBS depending on the ETS bit setting (CCR1.7).
Remains high if out of synchronization with the PRBS pattern. Goes
low when synchronized to the PRBS pattern. Any errors in the
received pattern after synchronization will cause a positive going
pulse (with same period as E1 or T1 clock) synchronous with
RCLK. PRBS bit errors can also be reported to the ECR1 and ECR2
registers by setting CCR6.2 to a logic 1.