Datasheet
Dual, Temperature-Controlled Resistors with Inter-
nally Calibrated Monitors and Password Protection
16 Maxim Integrated
DS1856
TABLE 03 (CONFIGURATION)
Word 0 Word 1 Word 2 Word 3
Row
(hex)
Row
Name
Byte 0/8 Byte 1/9 Byte 2/A
Byte 3/B
Byte 4/C Byte 5/D Byte 6/E Byte 7/F
80
<0>
Config
0
<8>
Mode
<4>
Tindex
<4>
Res0
<4>
Res1
<8>
Reserved
<8>
Reserved
<8>
Reserved
<8>
Reserved
88
<8>
Config
1
Int Enable
Config
Reserved Reserved chip addr Reserved
Rshift
1
Rshift
0
90
<8>
Scale
0
Reserved Vcc Scale Mon1 Scale Mon2 Scale
98
<8>
Scale
1
Mon3 Scale Reserved Reserved Reserved
A0
<8>
Offset
0
Reserved Vcc Offset MON1 Offset MON2 Offset
A8
<8>
Offset
1
MON3 Offset Reserved Reserved Internal Temp Offset*
B0
<9>
Pwd Value
PW1 msb PW1 lsb PW2 msb PW2 lsb
EXPANDED BYTES
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Byte
(hex)
Byte
Name
bit
15
bit
14
bit
13
bit
12
bit
11
bit
10
bit
9
bit
8
bit
7
bit
6
bit
5
bit
4
bit
3
bit
2
bit
1
bit
0
80 Mode
Reserved Reserved Reserved Reserved Reserved Reserved
TEN AEN
81 Tindex 2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
82 Res0 2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
83 Res1 2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
88 Int Enable Temp Vcc Mon1 Mon2 Mon3
Reserved Reserved
Reserved
89 Config
Reserved Reserved
ADEN ADFIX
Reserved Reserved
Inv 1 Inv 2
8C Chip Addr 2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
8E Rshift
1
Reserved
Mon1
2
Mon1
1
Mon1
0
Reserved
Mon2
2
Mon2
1
Mon2
0
8F Rshift
0
Reserved
Mon3
2
Mon3
1
Mon3
0
Reserved Reserved Reserved
Reserved
92 V
CC
Scale
2
15
2
14
2
13
2
12
2
11
2
10
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
94
Mon1 Scale 2
15
2
14
2
13
2
12
2
11
2
10
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
96
Mon2 Scale 2
15
2
14
2
13
2
12
2
11
2
10
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
98
Mon3 Scale 2
15
2
14
2
13
2
12
2
11
2
10
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
A2
V
CC
Offset
SS
2
15
2
14
2
13
2
12
2
11
2
10
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
A4
Mon1 Offset
SS
2
15
2
14
2
13
2
12
2
11
2
10
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
A6
Mon2 Offset
SS
2
15
2
14
2
13
2
12
2
11
2
10
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
A8
Mon3 Offset
SS
2
15
2
14
2
13
2
12
2
11
2
10
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
AE
Temp Offset*
S
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
2
-1
2
-2
2
-3
2
-4
2
-5
2
-6
B0 PW1 msb
2
31
2
30
2
29
2
28
2
27
2
26
2
25
2
24
2
23
2
22
2
21
2
20
2
19
2
18
2
17
2
16
B2 PW1 lsb
2
15
2
14
2
13
2
12
2
11
2
10
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
B4 PW2 msb
2
31
2
30
2
29
2
28
2
27
2
26
2
25
2
24
2
23
2
22
2
21
2
20
2
19
2
18
2
17
2
16
B6 PW2 lsb
2
15
2
14
2
13
2
12
2
11
2
10
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
*
The final result must be XOR’ed with BB40h.
Memory Map (continued)