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PMICs
PMIC - system monitor Reserve capacity circuit SOIC 8
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9
DS1836A/B/C/D
4
of
9
NON-MASKABLE INTERR
UPT CIRCUIT EXAMPLE
Figure 3
V
SENSE
=
R2
R2
R1
+
x 1.25
Example:
V
SENSE
= 4.50V at the trip po
int
100k
Ω
= R2
Therefore:
4.5
=
100
k
100k
R1
+
x 1.25
R1 = 260k
Ω
TIMING DIAGRAM: NON-MASKABLE INTERRUPT
Figure 4
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9
