Datasheet

DS1747/DS1747P Y2K-Compliant, Nonvolatile Timekeeping RAMs
5 of 16
Table 1. Truth Table
V
CC
CE
OE
WE
MODE DQ POWER
V
CC
>V
PF
V
IH
X
X
Deselect
High-Z
Standby
V
IL
X
V
IL
Write
Data In
Active
V
IL
V
IL
V
IH
Read
Data Out
Active
V
IL
V
IH
V
IH
Read
High-Z
Active
V
SO
<V
CC
<V
PF
X
X
X
Deselect
High-Z
CMOS Standby
V
CC
<V
SO
<V
PF
X X X Deselect High-Z
Data-Retention
Mode
SETTING THE CLOCK
As shown in Table 2, bit 7 of the Control register is the W (write) bit. Setting the W bit to 1 halts updates
to the device registers. The user can subsequently load correct date and time values into all eight registers,
followed by a write cycle of 00h to the Control register to clear the W bit and transfer those new settings
into the clock, allowing timekeeping operations to resume from the new set point.
Again referring to Table 2, bit 6 of the Control register is the R (read) bit. Setting the R bit to 1 halts
updates to the device registers. The user can subsequently read the date and time values from the eight
registers without those contents possibly changing during those I/O operations. A subsequent write cycle
of 00h to the Control register to clear the R bit allows timekeeping operations to resume from the
previous set point.
The pre-existing contents of the Control register bits 0:5 (Century value) are ignored/unmodified by a
write cycle to Control if either the W or R bits are being set to 1 in that write operation.
The pre-existing contents of the Control register bits 0:5 (Century value) will be modified by a write
cycle to Control if the W bit is being cleared to 0 in that write operation.
The pre-existing contents of the Control register bits 0:5 (Century value) will not be modified by a write
cycle to Control if the R bit is being cleared to 0 in that write operation.
STOPPING AND STARTING THE CLOCK OSCILLATOR
The clock oscillator may be stopped at any time. To increase the shelf life, the oscillator can be turned
off to minimize current drain from the battery. The OSC bit is the MSB (bit 7) of the seconds registers,
see Table 2. Setting it to a one stops the oscillator.
FREQUENCY TEST BIT
As shown in Table 2, bit 6 of the day byte is the frequency test bit. When the frequency test bit is set to
logic “1” and the oscillator is running, the LSB of the seconds register will toggle at 512Hz. When the
seconds register is being read, the DQ0 line will toggle at the 512Hz frequency as long as conditions for
access remain valid (i.e., CE low, OE low, WE high, and address for seconds register remain valid and
stable).
CLOCK ACCURACY (DIP MODULE)
The DS1747 is guaranteed to keep time accuracy to within ±1 minute per month at +25°C. The RTC is
calibrated at the factory by Maxim using nonvolatile tuning elements, and does not require additional
calibration. For this reason, methods of field clock calibration are not available and not necessary. The