Datasheet

DS1232/DS1232S
2 of 7
The second function the DS1232 performs is pushbutton reset control. The DS1232 debounces the
pushbutton input and guarantees an active reset pulse width of 250 ms minimum. The third function is a
watchdog timer. The DS1232 has an internal timer that forces the reset signals to the active state if the
strobe input is not driven low prior to timeout. The watchdog timer function can be set to operate on
timeout settings of approximately 150 ms, 600 ms, and 1.2 seconds.
OPERATION - POWER MONITOR
The DS1232 detects out-of-tolerance power supply conditions and warns a processor-based system of
impending power failure. When V
CC
falls below a preset level as defined by TOL (Pin 3), the V
CC
comparator outputs the signals RST (Pin 5) and
RST (Pin 6). When TOL is connected to ground, the RST
and RST signals become active as V
CC
falls below 4.75 volts. When TOL is connected to V
CC
, the RST
and RST signals become active as V
CC
falls below 4.5 volts. The RST and RST are excellent control
signals for a microprocessor, as processing is stopped at the last possible moments of valid V
CC
. On
power-up, RST and RST are kept active for a minimum of 250 ms to allow the power supply and
processor to stabilize.
OPERATION - PUSHBUTTON RESET
The DS1232 provides an input pin for direct connection to a pushbutton (Figure 2). The pushbutton reset
input requires an active low signal. Internally, this input is debounced and timed such that RST and RST
signals of at least 250 ms minimum are generated. The 250 ms delay starts as the pushbutton reset input is
released from low level.
OPERATION - WATCHDOG TIMER
A watchdog timer function forces RST and RST signals to the active state when the ST input is not
stimulated for a predetermined time period. The time period is set by the TD input to be typically 150 ms
with TD connected to ground, 600 ms with TD left unconnected, and 1.2 seconds with TD connected to
V
CC
. The watchdog timer starts timing out from the set time period as soon as RST and RST are inactive.
If a high-to-low transition occurs on the ST input pin prior to timeout, the watchdog timer is reset and
begins to timeout again. If the watchdog timer is allowed to timeout, then the RST and
RST signals are
driven to the active state for 250 ms minimum. The ST input can be derived from microprocessor
address signals, data signals, and/or control signals. When the microprocessor is functioning normally,
these signals would, as a matter of routine, cause the watchdog to be reset prior to timeout. To guarantee
that the watchdog timer does not timeout, a high-to-low transition must occur at or less than the minimum
shown in Table 1. A typical circuit example is shown in Figure 3.