Datasheet

Monolithic CMOS Analog Multiplexers
DG506A/DG507A
6
Switching Time Test Circuits (continued)
Figure 2a. Enable Switching Time
Figure 2b. Enable Switching Time
Figure 3. Break-Before-Make
Figure 4. Timing Diagrams for Figures 1, 2, and 3
-5V
S
1
A
1
A
2
A
0
EN
A
3
+15V
V
+
V
-
-15V
DG506A
GND
SWITCH
OUTPUT
V
O
1kΩ
D
50Ω
LOGIC
INPUT
S
2
THRU S
16
35pF
-5V
S
1b
A
1
A
2
A
0
EN
+15V
V
+
V
-
-15V
DG507A
GND
SWITCH
OUTPUT
V
O
1kΩ
35pF
D
b
50Ω
LOGIC
INPUT
S
1a
THRU S
4a,
D
a,
S
2b,
S
3b,
S
4b
+2.4V
V
S
= +5V
ALL S AND D
a
A
0
A
1
A
2
A
3
EN
+15V
V
+
V
-
-15V
DG506A
DG507A
GND
SWITCH
OUTPUT
V
O
1kΩ
D
b,
D
50Ω
LOGIC
INPUT
35pF
LOGIC INPUT
t
r
< 20ns
t
i
< 20ns
SWITCH OUTPUT
V
O
(SEE FIGURE 1)
TRANSITION
TIME
SWITCH OUTPUT
V
O
(SEE FIGURE 2)
ENABLE t
(ON)
/t
(OFF)
TIME
SWITCH OUTPUT
V
O
(SEE FIGURE 3)
3V
50%
0
t
ON
(En)
0.1 V
O
0
0.9 V
O
V
O
V
S
V
S
50%
0V
S8 ON
t
off
(En)
V
S1
0.8 V
S1
0.8 V
S8
V
S8
t
transition
S1 ON
t
transition
0
OPEN TIME
BREAK-BEFORE-MAKE
INTERVAL
t
OPEN