Datasheet

DG441/DG442
Improved, Quad, SPST Analog Switches
_______________________________________________________________________________________ 7
t
OFF
0.8 x V
OUT
V
OUT
0.8 x V
OUT
t
f
< 20ns
t
r
< 20ns
50%
0V
0V
+3V
SWITCH
OUTPUT
LOGIC INPUT WAVEFORM IS INVERTED FOR SWITCHES
THAT HAVE THE OPPOSITE LOGIC SENSE.
t
ON
SWITCH
INPUT
LOGIC
INPUT
+3V
IN
D
+15V
V+
V-
-15V
R
L
35pF
V
OUT
S
C
L
(INCLUDES FIXTURE AND STRAY CAPACITANCE)
GND
REPEAT TEST FOR CHANNELS 2, 3, AND 4.
V
OUT
= V
D
R
L
R
L
+ r
DS(ON)
LOGIC
INPUT
V
D
DG441
DG442
( )
ΔV
OUT
OFFONOFF
V
OUT
IN
IN
OFF OFFON
Q = ΔV
OUT
× C
L
-15V
V-
V+
INGND
S
+15V
R
GEN
V
GEN
V
IN
= +3V
C
L
1nF
V
OUT
D
DG441
DG442
DG441
DG442
Figure 2. Switching Time
Figure 3. Charge Injection
NETWORK
ANALYZER
SIGNAL
GENERATOR
R
GEN
= 50Ω
S
D
GND
R
L
10dBm
10nF
V+
+15V
IN
0.8V or 2.4V
V-
-15V
10nF
DG441
DG442
NETWORK
ANALYZER
SIGNAL
GENERATOR
R
GEN
= 50Ω
0.8V or 2.4V
S
IN1
D
GND
R
L
10dBm
10nF
V+
+15V
D
IN2
S
0.8V or 2.4V
50Ω
V-
-15V
10nF
DG441
DG442
Figure 4. Off-Isolation Rejection Ratio Figure 5. Crosstalk (repeat for channels 3 and 4)
______________________________________________Timing Diagrams/Test Circuits