Datasheet

DG401/DG403/DG405
Improved, Dual, High-Speed Analog Switches
6 _______________________________________________________________________________________
______________________________________________Timing Diagrams/Test Circuits
50%
t
OFF
tr < 20ns
t
f
< 20ns
V
OUT
V
OUT
t
ON
0.9 x V
OUT
0.9 x V
OUT
+3V
0V
0V
LOGIC
INPUT
SWITCH
OUTPUT
LOGIC INPUT WAVEFORM IS INVERTED FOR
SWITCHES THAT HAVE THE OPPOSITE LOGIC
SENSE CONTROL.
+5V +15V
V
OUT
R
L
= 1000Ω
C
L
= 35pF
-15V
REPEAT TEST FOR IN2 AND S2
0V
GND
LOGIC
INPUT
V
D
= +10V (for t
ON
)
V
D
= -10V (for t
OFF
)
FOR LOAD CONDITIONS, SEE Electrical Characteristics.
C
L
INCLUDES FIXTURE AND STRAY CAPACITANCE.
V
OUT
= V
D
R
L
R
L
+ r
DS(ON)
V+V
L
V-
D
IN
S
( )
DG401
DG403
DG405
V
GEN
GND
C
L
10nF
V
OUT
0V -15V
V-
V
L
V+
R
GEN
V
OUT
IN
ON OFF ON
∆V
OUT
Q = (∆V
OUT
) (C
L
)
+5V +15V
SD
DG401
DG403
DG405
50%
V
OUT1
V
OUT2
0.9 x V
OUT
+3V
0V
0V
LOGIC
INPUT
SWITCH
OUTPUT 1
SWITCH
OUTPUT 2
+5V
V
L
+15V
V+
V-
-15V
C
L
INCLUDES FIXTURE AND STRAY CAPACITANCE.
0V
GND
LOGIC
INPUT
0V
0.9 x V
OUT
t
D
t
D
IN
R
L2
C
L2
V
OUT2
R
L1
V
OUT1
C
L1
R
L
= 1000Ω
C
L
= 35pF
D
D
S
S
+10V
+10V
DG401
DG403
DG405
Figure 2. Switching Time
Figure 4. Charge Injection
Figure 3. Break-Before-Make Interval