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78P2351

Single Channel

OC-3/ STM1-E/ E4 LIU

DATA SHEET

Page: 1 of 42 2006 Teridian Semiconductor Corporation Rev. 2.4

SEPTEMBER 2006

DESCRIPTION

The 78P2351 is Teridian’s second generation Line

Interface Unit (LIU) for 155 Mbps (OC-3, STS-3, or

STM-1) and 140 Mbps PDH (E4) telecom interfaces.

The device is a single chip solution that includes an

integrated CDR in the transmit path for flexible NRZ

to CMI conversion.

The device can interface to 75

Ω coaxial cable using

CMI coding or directly to a fiber optics transceiver

module using NRZ coding. The 78P2351 is

compliant with all respective ANSI, ITU-T, and

Telcordia standards for jitter tolerance, generation,

and transfer.

APPLICATIONS

• Central Office Interconnects

• DSLAMs

• Add Drop Multiplexers (ADMs)

• PDH/SDH test equipment

• Multi Service Switches

• Digital Microwave Radios

FEATURES

• ITU-T G.703 compliant cable driver for 139.264

Mbps or 155.52 Mbps CMI-coded coax

transmission

• Integrated adaptive CMI equalizer and CDR in

receive path handles over 12.7dB of cable loss

• Serial, LVPECL-compatible system interface

with integrated CRU in transmit path for flexible

NRZ to CMI conversion.

• 4-bit parallel CMOS system interface with

master and slave Tx clock modes.

• Selectable LVPECL compatible NRZ media

interface for 155.52 Mbps optical transmission.

• Configurable via HW control pins or 4-wire serial

interface

• Compliant with ANSI T1.105.03-1994; ITU-T

G.751, G.813, G.823, G.825, G.958; and

Telcordia GR-253-CORE for jitter performance.

• Receiver Loss of Signal (LOS) detection

compatible with ITU-T G.783

• Operates from a single 3.3V supply

• 100-pin JEDEC LQFP

BLOCK DIAGRAM

RXP/N

SODP/N

SOCKP/N

PO[3:0]D

POCK

PTOCK

PI[3:0]D

PICK

SICKP/N

SIDP/N

ECLP/N

TXCKP/N

CMIP/N

CMI2P/N

Rx CDR

CMI

Decoder

FIFO

Tx CDR

Lock Detect

CMI

Encoder

Lock Detect

Adaptive

Eq.

LOS Detect

PMOD, SMOD[1:0], PAR

LLBK

RLBK,

RDSL

CMI

Summary of content (42 pages)

PAGE 1
78P2351 Single Channel OC-3/ STM1-E/ E4 LIU DATA SHEET SEPTEMBER 2006 DESCRIPTION FEATURES The 78P2351 is Teridian’s second generation Line Interface Unit (LIU) for 155 Mbps (OC-3, STS-3, or STM-1) and 140 Mbps PDH (E4) telecom interfaces. The device is a single chip solution that includes an integrated CDR in the transmit path for flexible NRZ to CMI conversion. • The device can interface to 75Ω coaxial cable using CMI coding or directly to a fiber optics transceiver module using NRZ coding.
PAGE 2
78P2351 Single Channel OC-3/ STM1-E/ E4 LIU TABLE OF CONTENTS ................................................................................................. 2 FUNCTIONAL DESCRIPTION........................................................................................ 4 MODE SELECTION................................................................................................................................4 REFERENCE CLOCK .............................................................................
PAGE 3
78P2351 Single Channel OC-3/ STM1-E/ E4 LIU TABLE OF CONTENTS (continued) PIN DESCRIPTION ....................................................................................................... 17 LEGEND ...............................................................................................................................................17 TRANSMITTER PINS ...........................................................................................................................17 RECEIVER PINS .....
PAGE 4
78P2351 Single Channel OC-3/ STM1-E/ E4 LIU FUNCTIONAL DESCRIPTION The 78P2351 contains all the necessary transmit and receive circuitry for connection between 139.264Mbps and 155.52Mbps line interfaces and the digital universe. The chip is controllable through pins or serial port register settings. In hardware mode (pin control) the SPSL pin must be low. In software mode (SPSL pin high), control pins are disabled and the 78P2351 must be configured via the 4-wire serial port.
PAGE 5
78P2351 Single Channel OC-3/ STM1-E/ E4 LIU Receive Loss of Signal The 78P2351 includes a Loss of Signal (LOS) detector. When the peak value of the received signal is less than approximately 19dB below nominal for approximately 110 UI, Receive Loss of Signal is asserted. The Rx LOS signal is cleared when the received signal is greater than approximately 18dB below nominal for 110 UI. In ECL mode, the LOS signal will be asserted when there are no transitions for longer than 2.3µs.
PAGE 6
78P2351 Single Channel OC-3/ STM1-E/ E4 LIU Plesiochronous Tx Serial Mode Figure 3 represents a common condition where a serial transmit clock is not available and/or the data is not source synchronous to the reference clock provided to the 78P2351. In this mode, the 78P2351 will recover a transmit clock from the serial plesiochronous data and bypass the internal FIFO and re-timing block.
PAGE 7
8P2351 Single Channel OC-3/ STM1-E/ E4 LIU Transmit Driver In CMI (electrical) mode, the CMIP/N pins are biased and terminated off-chip. They interface to 75Ω coaxial cable through a 1:1 wideband transformer and coaxial RF connectors. Reference application notes for schematic and layout guidelines. The transmitter encodes the data using CMI line coding and shapes an analog signal to meet the appropriate ITU-T G.703 template.
PAGE 8
78P2351 Single Channel OC-3/ STM1-E/ E4 LIU LOOPBACK MODES In SW mode, LLBK and RLBK bits in the Signal Control register are provided to activate the local and remote analog loopback modes respectively. In HW mode, the LPBK pin can be used to activate local and remote analog loopback paths as shown in the table below. LPBK pin Low Loopback Mode High EACH CHANNEL: Tx Lock Detect Normal operation Remote (analog) Loopback: Recovered receive clock and data looped back directly to the transmit driver.
PAGE 9
78P2351 Single Channel OC-3/ STM1-E/ E4 LIU SERIAL CONTROL INTERFACE PROGRAMMABLE INTERRUPTS The serial port controlled register allows a generic controller to interface with the 78P2351. It is used for mode settings, diagnostics and test, retrieval of status and performance information, and for on-chip fuse trimming during production test. The SPSL pin must be high in order to use the serial port.
PAGE 10
78P2351 Single Channel OC-3/ STM1-E/ E4 LIU REGISTER DESCRIPTION REGISTER ADDRESSING Address Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Port Address Assignment PA[3] PA[2] Bit 2 Bit 1 Bit 0 SA[0] Read/ Write R/W* Sub-Address PA[1] PA[0] SA[2] SA[1] REGISTER TABLE a) PA[3:0] = 0 : Global Registers Sub Addr 0 1 2 Reg.
PAGE 11
78P2351 Single Channel OC-3/ STM1-E/ E4 LIU REGISTER DESCRIPTION (continued) LEGEND TYPE DESCRIPTION R/O Read only R/C Read and Clear TYPE R/W DESCRIPTION Read or Write GLOBAL REGISTERS ADDRESS 0-0: MASTER CONTROL REGISTER BIT NAME TYPE DFLT VALUE DESCRIPTION 7 E4 R/W 0 Line Rate Selection: Selects the line rate as well as the input clock frequency at the CKREFP/N pins. 0: OC-3, STS-3, STM-1 (155.52MHz) 1: E4 (139.
PAGE 12
78P2351 Single Channel OC-3/ STM1-E/ E4 LIU REGISTER DESCRIPTION (continued) ADDRESS 0-1: INTERRUPT CONTROL REGISTER This register selects the events that would cause the interrupt pins to be activated. User may set as many bits as required.
PAGE 13
78P2351 Single Channel OC-3/ STM1-E/ E4 LIU REGISTER DESCRIPTION (continued) PORT-SPECIFIC REGISTERS For PA[3:0] = 1 only. Accessing a register with port address greater than 1 constitutes an invalid command. ADDRESS 1-0: MODE CONTROL REGISTER BIT NAME TYPE DFLT VALUE 7 PDTX R/W 0 Transmitter Power-Down: 0 : Normal Operation 1 : Power-Down. CMI Transmit output is tri-stated.
PAGE 14
78P2351 Single Channel OC-3/ STM1-E/ E4 LIU REGISTER DESCRIPTION (continued) ADDRESS 1-1: SIGNAL CONTROL REGISTER BIT 7 6 5 NAME TCMIINV RCMIINV LOLOR TYPE R/W R/W R/W DFLT VALUE 0 Transmit CMI Inversion: This bit will flip the polarity of the transmit CMI data outputs at CMIP/N. For debug use only. 0: Normal 1: Invert 0 Receive CMI Inversion: This bit will flip the polarity of the receive CMI data inputs at RXP/N. For debug use only.
PAGE 15
78P2351 Single Channel OC-3/ STM1-E/ E4 LIU REGISTER DESCRIPTION (continued) ADDRESS 1-2: ADVANCED TRANSMIT CONTROL REGISTER 1 BIT NAME TYPE DFLT VALUE DESCRIPTION 7:1 -- R/W 0000000 Reserved. 0 TXEQ R/W 0 Transmit Fixed Equalizer Enable: When enabled, compensates for between 0.75m and 1.
PAGE 16
78P2351 Single Channel OC-3/ STM1-E/ E4 LIU REGISTER DESCRIPTION (continued) ADDRESS 1-5: STATUS MONITOR REGISTER BIT NAME TYPE DFLT VALUE 7:5 -- R/C XXX 4 RXLOS R/C X Receive Loss of Signal Indication: 0: Normal operation 1: Loss of signal condition detected DESCRIPTION Reserved.
PAGE 17
78P2351 Single Channel OC-3/ STM1-E/ E4 LIU PIN DESCRIPTION LEGEND TYPE A CIS CI DESCRIPTION Analog Pin TYPE PO (Tie unused pins to ground) CMOS Schmitt Trigger Input CO (Tie unused pins to ground) CMOS Digital Input COZ (Tie unused pins to ground) (Tie unused pins to supply or leave floating) CMOS Digital Output (Leave unused pins floating) CMOS Tristate Digital Output (Leave unused pins floating) Open-drain Digital Output CIU CMOS Digital Input w/ Pull-up CID CMOS Digital Input w/ Pull-do
PAGE 18
78P2351 Single Channel OC-3/ STM1-E/ E4 LIU PIN DESCRIPTION (continued) RECEIVER PINS NAME PIN PO0D PO1D PO2D PO3D 41 40 37 36 POCK 33 SODP SODN 20 21 TYPE DESCRIPTION CO Receive Data (Parallel Mode) Output: Recovered receive data de-serialized into four-bit CMOS parallel (nibble) outputs. The MSB (PO3D) is received first. Active, but undefined during reset. Note: During Loss of Signal conditions, data outputs are held low. CO Receive (Parallel Mode) Clock Output: A 34.816 MHz (E4) or 38.
PAGE 19
78P2351 Single Channel OC-3/ STM1-E/ E4 LIU PIN DESCRIPTION (continued) REFERENCE AND STATUS PINS NAME PIN TYPE DESCRIPTION Reference Clock Input: A required reference clock input used for clock/data recovery and frequency synthesizer. Options include CKREFP CKREFN 83 82 PI/ CI • 139.264 MHz (E4) or 155.52 MHz (STM1) differential LVPECL clock input at CKREFP/N • 17.408 MHz (E4), 19.44 MHz (STM1), or 77.78 MHz (STM1) singleended CMOS clock input at CKREFP. Tie CKREFN to ground when unused.
PAGE 20
78P2351 Single Channel OC-3/ STM1-E/ E4 LIU PIN DESCRIPTION (continued) CONTROL PINS NAME FRST RCSL PIN 59 14 TYPE CIT CID DESCRIPTION FIFO Phase-Initialization Control: When asserted, the transmit FIFO pointers are reset to the respective “centered” states. Also resets the FIERR interrupt bit. De-assertion edge of FRST will resume FIFO operation. • Low: FRST assertion.
PAGE 21
78P2351 Single Channel OC-3/ STM1-E/ E4 LIU PIN DESCRIPTION (continued) CONTROL PINS (continued) NAME TXOUT1 TXOUT0 PIN 1 2 TYPE DESCRIPTION CIT Advanced Tx Control 1: Low: Enables fixed LVPECL equalizer at the transmit inputs SIDP/N for FR4 trace lengths up to 1.5m.
PAGE 22
78P2351 Single Channel OC-3/ STM1-E/ E4 LIU PIN DESCRIPTION (continued) SERIAL-PORT PINS NAME SEN_CMI SCK_MON SDI_PAR SDO_E4 PIN 72 73 71 70 TYPE DESCRIPTION CIU [SPSL=1] Serial-Port Enable: High during read and write operations. Low disables the serial port. While SEN is low, SDO remains in high impedance state, and SDI and SCK activities are ignored. [SPSL=0] Medium Select: Low: Fiber (NRZ pass-through) mode High: CMI mode CIS [SPSL=1] Serial Clock: Controls the timing of SDI and SDO.
PAGE 23
78P2351 Single Channel OC-3/ STM1-E/ E4 LIU ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS Operation beyond these limits may permanently damage the device. PARAMETER RATING Supply Voltage (Vdd) -0.5 to 4.0 VDC Storage Temperature -65 to 150 °C Junction Temperature -40 to 150 °C Pin Voltage (CMIxP,CMIxN) Vdd + 1.5 VDC Pin Voltage (all other pins) -0.3 to (Vdd+0.
PAGE 24
78P2351 Single Channel OC-3/ STM1-E/ E4 LIU ELECTRICAL SPECIFICATIONS (continued) ANALOG PINS CHARACTERISTICS: The following table is provided for informative purpose only. Not tested in production. PARAMETER SYMBOL CONDITIONS MIN NOM MAX UNIT Ground Reference 1.9 2.1 2.
PAGE 25
78P2351 Single Channel OC-3/ STM1-E/ E4 LIU ELECTRICAL SPECIFICATIONS (continued) Pins of type CO and COZ: PARAMETER SYMBOL CONDITIONS Output Voltage Low Vol Iol = 8mA Output Voltage High Voh Ioh = -8mA Tt CL = 20pF Output Transition Time Effective Source Impedance Tri-state Output Leakage Current MIN MAX UNIT 0.4 V 2.
PAGE 26
78P2351 Single Channel OC-3/ STM1-E/ E4 LIU ELECTRICAL SPECIFICATIONS (continued) SERIAL-PORT TIMING CHARACTERISTICS: PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT SDI to SCK setup time tsu 4 ns SDI to SCK hold time th 4 ns SCK to SDO propagation delay tprop 10 ns SCK frequency SCK 20 MHz CS tsu th SCK tsu th SDI X 1 SA0 tprop SA1 SA2 SDO PA0 PA1 PA2 PA3 X or Z Z D0 D1 D2 D3 D4 D5 D6 D7 Z Figure 10: Read Operation CS tsu th SCK tsu th SDI X 0 SDO SA0 S
PAGE 27
78P2351 Single Channel OC-3/ STM1-E/ E4 LIU ELECTRICAL SPECIFICATIONS (continued) TRANSMITTER TIMING CHARACTERISTICS: PARAMETER SYMBOL CONDITIONS MIN Clock Duty Cycle TTCF/TTC PTOCK 40 NOM MAX UNIT 60 % Setup Time TPS Parallel mode 4 ns Hold Time TPH Parallel mode 4 ns Setup Time TSS Serial mode 2 ns Hold Time TSH Serial mode 2 ns TIMING DIAGRAM: Transmitter Waveforms SICKN SICKP SIDP SIDN TSS TSH PICK PIxD<0:3> TPS TRC = 25.72ns TPH TTCT TRCF = 12.
PAGE 28
78P2351 Single Channel OC-3/ STM1-E/ E4 LIU ELECTRICAL SPECIFICATIONS (continued) REFERENCE CLOCK CHARACTERISTICS: PARAMETER SYMBOL CONDITIONS CKREF Duty Cycle MIN MAX UNIT 40 60 % Synchronous mode; E4 -15 +15 Synchronous mode; STM1 -20 +20 Plesiochronous or Loop-timing mode. (see Note 1) -75 +75 -- CKREF Frequency Stability -- NOM ppm Note 1: In Plesiochronous mode, the transmit clock/data source (i.e.
PAGE 29
78P2351 Single Channel OC-3/ STM1-E/ E4 LIU ELECTRICAL SPECIFICATIONS (continued) TRANSMITTER SPECIFICATIONS FOR CMI INTERFACE Bit Rate: 139.264 Mbps ± 15ppm or 155.52 Mbps ± 20ppm Code: Coded Mark Inversion (CMI) Relevant Specifications: ITU-T G.703, Telcordia GR-253, ANSI T1.102 With the coaxial output port driving a 75Ω load, the output pulses conform to the templates in Figures 12, 13, 14 and 15. These specifications are tested during production test.
PAGE 30
78P2351 Single Channel OC-3/ STM1-E/ E4 LIU ELECTRICAL SPECIFICATIONS (continued) V 0.60 0.55 T = 7.18ns (Note 1) (Note 1) 0.50 0.45 0.40 1.795 ns 1ns 0.1ns 1ns 0.1ns -0.05 1.795 ns 1ns 0.1ns 0.35ns 0.05 Nominal Pulse 0.1ns 0.35ns Nominal Zero Level (Note 2) -0.40 1ns -0.45 1ns 1.795 ns -0.50 -0.55 1.795 ns (Note 1) -0.60 1ns (Note 1) Note 1 – The maximum “steady state” amplitude should not exceed the 0.55V limit.
PAGE 31
78P2351 Single Channel OC-3/ STM1-E/ E4 LIU ELECTRICAL SPECIFICATIONS (continued) V 0.60 0.55 T = 7.18ns (Note 1) (Note 1) 0.50 0.45 0.40 1ns 0.1ns 1ns 0.5ns 0.1ns 0.5ns Nominal Pulse 0.05 -0.05 Nominal Zero Level (Note 2) 3.59ns 3.59ns 1.35ns -0.40 1.35ns 1ns -0.45 1ns 1.795 ns -0.50 -0.55 1.795 ns (Note 1) -0.60 Note 1 – The maximum “steady state” amplitude should not exceed the 0.55V limit.
PAGE 32
78P2351 Single Channel OC-3/ STM1-E/ E4 LIU ELECTRICAL SPECIFICATIONS (continued) V 0.60 T = 6.43ns (Note 1) 0.55 (Note 1) 0.50 1.608ns 1ns 0.45 0.1ns 0.40 1ns 0.1ns 1.608ns 1ns 0.1ns 0.35ns 0.05 Nominal Pulse 0.1ns 0.35ns Nominal Zero Level (Note 2) -0.05 -0.40 1ns -0.45 1ns 1.608ns -0.50 -0.55 (Note 1) -0.60 1ns 1.608ns (Note 1) Note 1 – The maximum “steady state” amplitude should not exceed the 0.55V limit.
PAGE 33
78P2351 Single Channel OC-3/ STM1-E/ E4 LIU ELECTRICAL SPECIFICATIONS (continued) V 0.60 0.55 6.43ns (Note 1) (Note 1) 0.50 0.45 0.40 1ns 0.1ns 1ns 0.5ns 0.1ns 0.5ns Nominal Pulse 0.05 -0.05 Nominal Zero Level (Note 2) 3.215ns 3.215ns 1.2ns -0.40 -0.45 -0.50 -0.55 -0.60 1.2ns 1ns 1ns 1.608ns 1.608ns (Note 1) Note 1 – The maximum “steady state” amplitude should not exceed the 0.55V limit.
PAGE 34
78P2351 Single Channel OC-3/ STM1-E/ E4 LIU ELECTRICAL SPECIFICATIONS (continued) TRANSMITTER OUTPUT JITTER The transmit jitter specification ensures compliance with ITU-T G.813, G.823, G.825 and G.958; ANSI T1.1021993 and T1.105.03-1994; and GR-253-CORE for all supported rates. Transmit output jitter is not tested during production test.
PAGE 35
78P2351 Single Channel OC-3/ STM1-E/ E4 LIU ELECTRICAL SPECIFICATIONS (continued) RECEIVER SPECIFICATIONS FOR CMI INTERFACE (Transformer-coupled) Consult application note for reference schematic, layout guidelines, and recommended transformers. PARAMETER CONDITION Peak Differential Input Amplitude, RXP and RXN CMI mode; MON=0; 12.7dB of cable loss CMI mode; MON=1; 20dB flat loss w/ 6dB of cable loss CMI mode; MON=0; All valid cable lengths. STM-1 mode; CMI mode; 12.
PAGE 36
78P2351 Single Channel OC-3/ STM1-E/ E4 LIU ELECTRICAL SPECIFICATIONS (continued) RECEIVER JITTER TOLERANCE The 78P2351 exceeds all relevant jitter tolerance specifications shown in Figures 17, 18. STS-3/OC-3 jitter tolerance specifications are in ANSI T1.105.03-1994 and Telcordia GR-253-CORE. STM-1 (optical) jitter tolerance specifications are in ITU-T G.813, G.825, and G.958. STM-1e (electrical) jitter tolerance specifications are in ITU-T G.825. E4 specifications are found in ITU-T G.823.
PAGE 37
78P2351 Single Channel OC-3/ STM1-E/ E4 LIU ELECTRICAL SPECIFICATIONS (continued) 100 Optical (NRZ) Interfaces G.813, G.958, T1.105.03, GR-253 STM-1 / STS-3 / OC-3 Tolerance G.825 - STM-1 Tolerance Jitter Tolerance ( UIpp ) 10 1 0.1 0.01 1.E+00 10Hz 100Hz 1kHz 10kHz 100kHz 1MHz 10MHz Jitter Frequency Figure 18: Jitter Tolerance - optical (NRZ) interfaces PARAMETER CONDITION MIN 10Hz to 19.3Hz 38.9 19.3Hz to 68.7Hz OC-3/STS-3/STM-1 (optical) Jitter Tolerance 68.7Hz to 6.
PAGE 38
78P2351 Single Channel OC-3/ STM1-E/ E4 LIU ELECTRICAL SPECIFICATIONS (continued) RECEIVER JITTER TRANSFER FUNCTION The receiver clock recovery loop filter characteristics such that the receiver has the following transfer function. The corner frequency of the Rx DLL is approximately 120 kHz. Receiver jitter transfer function is not tested during production test. 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 1.00E+03 1.00E+04 1.00E+05 1.00E+06 1.
PAGE 39
78P2351 Single Channel OC-3/ STM1-E/ E4 LIU ELECTRICAL SPECIFICATIONS (continued) CMI MODE LOSS OF SIGNAL CONDITION PARAMETER CONDITION LOS threshold LOS timing MIN TYP MAX UNIT -35 10 -19 110 -15 255 dB UI Nominal value Maximum cable loss 3 dB 15dB Loss of Signal must be cleared Tolerance range LOS can be detected or cleared 35dB Loss of Signal must be declared APPLICATION INFORMATION EXTERNAL COMPONENTS: COMPONENT Receiver Termination Resistor, CMI Mode Transmitter Termination Resistor, C
PAGE 40
78P2351 Single Channel OC-3/ STM1-E/ E4 LIU MECHANICAL SPECIFICATIONS 15.70 (0.618) 16.30 (0.641) 1 15.70 (0.618) 16.30 (0.641) Top View 13.80 (0.543) 14.20 (0.559) 0.05(0.002) 0.15(0.006) 1.40(0.055) 1.60(0.063) 0.60(0.024) TYP. 0.18(0.007) 0.27(0.011) 0.50(0.020)TYP. Side View 100-pin JEDEC LQFP (Top View) Page: 40 of 42 2006 Teridian Semiconductor Corporation Rev. 2.
PAGE 41
78P2351 Single Channel OC-3/ STM1-E/ E4 LIU PACKAGE INFORMATION 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 78P2351 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 N/C N/C SCK_MON SEN_CMI SDI_PAR SDO_E4 VCC GND INTTXB VCC GND PORB TGND CKSL LOS LOL FRST SPSL N/C VCC GND N/C N/C INTRXB N/C PI2D PI3D PTOCK N/C VSS VDD N/C POCK VSS VDD PO3D PO2D VSS VDD PO1D PO0D VSS VDD N/C N/C N/C N/C N/C N/C N/C 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 4
PAGE 42
78P2351 Single Channel OC-3/ STM1-E/ E4 LIU Revision History -v2-0 v2-2 v2-3 v2-4 Contact Teridian for revision history of earlier releases March 14, 2005: Final Datasheet Release Updated Ordering Numbers to reflect production silicon revision A06 o Obsoleted 70Pxxxx option (CMOS Output type status & interrupt pins) Improved/modified Functional Descriptions for: o Reference Clock, Rx LOS & LOL detectors, Synchronous (Re-Timing) Transmit Modes, Tx FIFO, Tx Driver, Tx LOL detector, and Power-on Reset desc