User's Manual

Updated
2008-09-08
File
LEO2 Platform Hardware Manual
Rev.
V1.0
LGE Proprietary
３
MCTR Lab.
2.3 Top level block diagram 1
2
RX_FRAME_SYNC_N
OPT_CTLCH_SYMB[8]
OPT _CCH_STB, START, END
OPT_CCH_IDX[10]
RSVD[10]
32 Signals
5
4
S
i
g
n
a
l
s
C
T
L
C
H
_
S
Y
M
B
[
8
]
C
T
L
C
H
_
S
T
B
,
S
T
A
R
T
,
E
N
D
C
T
L
C
H
_
I
D
X
[
1
0
]
O
P
T
_
R
X
_
F
R
A
M
E
_
S
Y
N
C
_
N
R
S
V
D
[
3
2
]
TX_FI LTER_OUT[48]
TX_FILTER_IQ_SEL
RSVD[10]
59 Signals
RF_GPIO[16]
4ch SPI
32 Signals
RX_FRAME_SYNC_N
RX_SUB_FRAME_SYNC_N
ENG_EN[5]
ORX_WR, ADDR[10], DATA[32]
MIMO_WR_ADDR[10], DATA[32]
SC_RD_DATA0[32]
SC_RD_DATA1[32]
SC_RD_STB, IDX[2]
SC_RD_EN, ADDR[11]
SC_RD_SYMB_IDX[2]
ORX_OPT[100]
RSVD[64]
310 Signals
3
2
S
i
g
n
a
l
s
32 Signals
51 Signals
5
1
S
i
g
n
a
l
s
149 Signals
149 Signals
100 Signals
Application Interface
EPI, NAND, USB
SDIO, SPI, DIP SW
9
6
S
i
g
n
a
l
s
O
P
T
_
D
C
H
0
_
S
Y
M
B
0
[
8
]
O
P
T
_
D
C
H
0
_
S
Y
M
B
1
[
8
]
O
P
T
_
D
C
H
0
_
S
T
B
,
S
T
A
R
T
,
E
N
D
R
S
V
D
[
1
3
]
OPT_DCH1_SYMB0[8]
OPT_DCH1_SYMB1[8]
OPT_DCH1_STB, START, END
RSVD[13]
DATACH0_SYMB0[8]
DATACH0_SYMB1[8]
DATACH0_STB, START, END
RSVD[ 32]
D
A
T
A
C
H
1
_
S
Y
M
B
0
[
8
]
D
A
T
A
C
H
1
_
S
Y
M
B
1
[
8
]
D
A
T
A
C
H
1
_
S
T
B
,
S
T
A
R
T
,
E
N
D
R
S
V
D
[
3
2
]
TD0_START
TD0_IMEM_WE, SEL[3]
TD0_IMEM_WADDR[12]
TD0_IMEM_WDATA[64]
TD0_DB_DONE, DEC_DONE
HARQ0_START
HARQ0_PARAM_START
RSVD[64]
RSVD[100]
TX_I[12]
TX_Q[12]
RSVD[2]
26 Signals
RX0_I[ 12], RX0_Q[12]
RX1_I[ 12], RX1_Q[12]
48 Signals
PLL
30.72/61.44/122.88MHz
TurboDecoder_CLK
64bits
mDDR
ARM926EJ-S
64bits
mDDR
TD1_START
TD1_IMEM_WE, SEL[3]
TD1_IMEM_WADDR[12]
TD1_IMEM_WDATA[64]
TD1_DB_DONE, DEC_DONE
HARQ1_START
HARQ1_PARAM_START
RSVD[64]
SDRAM
USB
UART
ETM
NAND
Ethernet
Serial
Flash
JTAG
RF Daughter connector
3
Figure 2. Top level block diagram 4
5
6
2.4 Placement map 7
HARQ TP0 HARQ TP1
TD1 TP0 TD1 TP1
MIMO TP0 MIMO TP1
SRCH TP0
SRCH TP1
TX TP0
TX TP1
TD0 TP0
TD0 TP1
HARQ0 TP0
HARQ0 TP1
RF RX
RF TX
RESET
ETHERNET
J1 J4 J7
J10
J11
J6
J3
8
Figure 3. Placement map of the LEO2-A 9