User's Manual

Updated
2008-09-08
File
LEO2 Platform Hardware Manual
Rev.
V1.0
LGE Proprietary iii MCTR Lab.
CONTENTS 1
1. Introduction............................................................................................................................... １ 2
1.1 Scope ..................................................................................................................................... １ 3
1.2 Terminology............................................................................................................................ １ 4
1.3 Trademark List........................................................................................................................ １ 5
1.4 Special Mark........................................................................................................................... １ 6
2. Features and top level diagram ................................................................................................. ２ 7
2.1 Features ................................................................................................................................. ２ 8
2.2 Photograph of the LEO2-A platform board............................................................................... ２ 9
2.3 Top level block diagram .......................................................................................................... ３ 10
2.4 Placement map....................................................................................................................... ３ 11
3. Block description....................................................................................................................... ４ 12
3.1 FPGA subsystem .................................................................................................................... ４ 13
3.2 ARM subsystem...................................................................................................................... ４ 14
3.3 Debugger Interface ................................................................................................................. ５ 15
3.4 RF Interface............................................................................................................................ ６ 16
3.5 Reference Clock ..................................................................................................................... ７ 17
3.6 Reset ...................................................................................................................................... ８ 18
3.7 Application interface................................................................................................................ ８ 19
3.8 Power Supplies....................................................................................................................... ９ 20
4. DIP switch, LED and logic probing connector ............................................................................ ９ 21
4.1 ARM Processor debugging configuration switch setting........................................................... ９ 22
4.2 General purpose LED indication........................................................................................... １０ 23
4.3 Logic probing connector....................................................................................................... １１ 24
5. Description of Smart antenna and beam forming modes if applicable ..................................... １２ 25
6. Reference............................................................................................................................ １２3 26
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