Dual-Core Intel Xeon Processor 2.80 GHz Specification Update

18 Dual-Core Intel
®
Xeon
®
Processor 2.80 GHz Specification Update
Errata
D12. Processor issues inconsistent transaction size attributes for locked
operation
Problem: When the processor is in the page address extension (PAE) mode and detects the need to set the
Access and/or Dirty bits in the page directory or page table entries, the processor sends an 8 byte
load lock onto the System Bus. A subsequent 8 byte store unlock is expected, but instead a 4 byte
store unlock occurs. Correct data are provided since only the lower bytes change, however external
logic monitoring the data transfer may be expecting an 8-byte store unlock.
Implication: No known commercially available chipsets are affected by this erratum.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.
D13. When the processor is in the system management mode (SMM), debug
registers may be fully writeable
Problem: When in system management mode (SMM), the processor executes code and stores data in the
SMRAM space. When the processor is in this mode and writes are made to DR6 and DR7, the
processor should block writes to the reserved bit locations. Due to this erratum, the processor may
not block these writes. This may result in invalid data in the reserved bit locations.
Implication: Reserved bit locations within DR6 and DR7 may become invalid.
Workaround: Software may perform a read/modify/write when writing to DR6 and DR7 to ensure that the values
in the reserved bits are maintained.
Status: For the steppings affected, see the Summary Table of Changes.
D14. Shutdown and IERR# may result due to a machine check exception on a
Hyper-Threading Technology enabled processor
Problem: When a machine check exception (MCE) occurs due to an internal error, both logical processors on
a Hyper-Threading Technology enabled processor normally vector to the MCE handler. However,
if one of the logical processors is in the “Wait for SIPI” state, that logical processor will not have a
MCE handler and will shut down and assert IERR#.
Implication: A processor with a logical processor in the “Wait for SIPI” state will shut down when an MCE
occurs on the other thread.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.
D15. Processor may hang under certain frequencies and 12.5% STPCLK# duty
cycle
Problem: If a system de-asserts STPCLK# at a 12.5% duty cycle, and the processor is running below 2 GHz,
and the processor thermal control circuit (TCC) on-demand clock modulation is active, the
processor may hang. This erratum does not occur under the automatic mode of the TCC.
Implication: When this erratum occurs, the processor will hang.
Workaround: If use of the on-demand mode of the processor's TCC is desired in conjunction with STPCLK#
modulation, then assure that STPCLK# is not asserted at a 12.5% duty cycle.
Status: For the steppings affected, see the Summary Table of Changes.
D16. System may hang if a fatal cache error causes bus write line (BWL)
transaction to occur to the same cache line address as an outstanding bus
read line (BRL) or bus read-invalidate line (BRIL)
Problem: A processor internal cache fatal data ECC error may cause the processor to issue a BWL
transaction to the same cache line address as an outstanding BRL or BRIL. As it is not typical