Datasheet

ManualsBrandsHynix Manualscomputer componentsHMT351R7CFR4C-H9

Rev. 1.0 /Jul. 2012 1

240pin DDR3 SDRAM Registered DIMM

*SK hynix reserves the right to change products or specifications without notice.

DDR3 SDRAM Registered DIMM

Based on 2Gb C-die

HMT325R7CFR8C

HMT351R7CFR8C

HMT351R7CFR4C

HMT31GR7CFR8C

HMT31GR7CFR4C

HMT42GR7CMR4C

Summary of content (76 pages)

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240pin DDR3 SDRAM Registered DIMM DDR3 SDRAM Registered DIMM Based on 2Gb C-die HMT325R7CFR8C HMT351R7CFR8C HMT351R7CFR4C HMT31GR7CFR8C HMT31GR7CFR4C HMT42GR7CMR4C *SK hynix reserves the right to change products or specifications without notice. Rev. 1.0 /Jul.
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Revision History Revision No. History Draft Date 0.1 Initial Release Aug.2011 0.2 Typo Collected : 1866 Speed bin table update Sep.2011 1.0 Latest JEDEC Spec and Product Line-up Updated Jul.2012 Rev. 1.0 / Jul.
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Description Registered DDR3 SDRAM DIMMs (Registered Double Data Rate Synchronous DRAM Dual In-Line Memory Modules) are low power, high-speed operation memory modules that use DDR3 SDRAM devices. These Registered SDRAM DIMMs are intended for use as main memory when installed in systems such as servers and workstations. Features • • • • • • • • • • • • • Power Supply: VDD=1.5V (1.425V to 1.575V) VDDQ = 1.5V (1.425V to 1.575V) VDDSPD=3.0V to 3.
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Key Parameters MT/s Grade tCK (ns) CAS Latency (tCK) tRCD (ns) tRP (ns) tRAS (ns) tRC (ns) CL-tRCD-tRP DDR3-1066 -G7 1.875 7 13.125 13.125 37.5 50.625 7-7-7 DDR3-1333 -H9 1.5 9 13.5 13.5 (13.125)* (13.125)* 36 49.5 (49.125)* 9-9-9 DDR3-1600 -PB 1.25 11 13.75 13.75 (13.125)* (13.125)* 35 48.75 (48.125)* 11-11-11 DDR3-1866 -RD 1.07 13 13.91 13.91 (13.125)* (13.125)* 34 47.91 (48.125)* 13-13-13 *SK hynix DRAM devices support optional downbinning to CL11, CL9 and CL7.
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Pin Descriptions Pin Name Description Num ber Pin Name Description Num ber CK0 Clock Input, positive line 1 ODT[1:0] On Die Termination Inputs 2 CK0 Clock Input, negative line 1 DQ[63:0] Data Input/Output 64 CK1 Clock Input, positive line 1 CB[7:0] CK1 Clock Input, negative line 1 DQS[8:0] Clock Enables 2 DQS[8:0] RAS Row Address Strobe 1 DM[8:0]/ DQS[17:9], TDQS[17:9] CAS Column Address Strobe 1 DQS[17:9], TDQS[17:9] WE Write Enable 1 EVENT S[3:0] Chip Selects 4
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Input/Output Functional Descriptions Symbol Type Polarity CK0 IN Positive Line Positive line of the differential pair of system clock inputs that drives input to the onDIMM Clock Driver. CK0 IN Negative Line Negative line of the differential pair of system clock inputs that drives the input to the on-DIMM Clock Driver. CK1 IN Positive Line Terminated but not used on RDIMMs. CK1 IN Negative Line Terminated but not used on RDIMMs.
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Symbol Type Polarity Function DQS[17:0] I/O Positive Edge Positive line of the differential data strobe for input and output data. DQS[17:0] I/O Negative Edge Negative line of the differential data strobe for input and output data. TDQS/TDQS is applicable for X8 DRAMs only. When enabled via Mode Register A11=1 in MR1,DRAM will enable the same termination resistance function on TDQS/TDQS that is applied to DQS/DQS.
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Pin Assignments Pin # Front Side (left 1–60) Pin # Back Side (right 121–180) Pin # Front Side (left 61–120) Pin # Back Side (right 181–240) 1 VREFDQ 121 VSS 61 A2 181 A1 2 VSS 122 DQ4 62 VDD 182 VDD 3 DQ0 123 DQ5 63 NC, CK1 183 VDD 4 DQ1 124 VSS 64 NC, CK1 184 CK0 5 VSS 125 DM0,DQS9, TDQS9 65 VDD 185 CK0 6 DQS0 126 NC,DQS9, TDQS9 66 VDD 186 VDD 7 DQS0 127 VSS 67 VREFCA 187 EVENT, NC 8 VSS 128 DQ6 68 Par_In, NC 188 A0 9 DQ2 129 DQ7 6
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Pin # Front Side (left 1–60) Pin # Back Side (right 121–180) Pin # Front Side (left 61–120) Pin # Back Side (right 181–240) 32 VSS 152 DM3,DQS12, TDQS12 92 VSS 212 DM5,DQS14, TDQS14 33 DQS3 153 NC,DQS12, TDQS12 93 DQS5 213 NC,DQS14, TDQS14 34 DQS3 154 VSS 94 DQS5 214 VSS 35 VSS 155 DQ30 95 VSS 215 DQ46 36 DQ26 156 DQ31 96 DQ42 216 DQ47 37 DQ27 157 VSS 97 DQ43 217 VSS 38 VSS 158 CB4, NC 98 VSS 218 DQ52 39 CB0, NC 159 CB5, NC 99 DQ48 219 D
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Registering Clock Driver Specifications Capacitance Values Symbol CI CIR Parameter Conditions Min Typ Max Unit Input capacitance, Data inputs 1.5 - 2.5 pF Input capacitance, CK, CK, FBIN, FBIN (up to DDR3-1600) 1.5 - 2.5 pF - - 3 pF Input capacitance, RESET, MIRROR, QCSEN VI = VDD or GND; VDD = 1.
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On DIMM Thermal Sensor The DDR3 SDRAM DIMM temperature is monitored by integrated thermal sensor. The integrated thermal sensor comply with JEDEC “TSE2002av, Serial Presence Detect with Temperature Sensor”. Connection of Thermal Sensor EVENT SCL SDA SA0 SPD with SA1 Integrated SA2 TS EVENT SCL SA0 SDA SA1 SA2 Temperature-to-Digital Conversion Performance Parameter Temperature Sensor Accuracy (Grade B) Resolution Rev. 1.0 / Jul.
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RODT0B PCK0B RCKE0B RWEB PCK0B A[O:N]/BA[O:N] ODT CK CKE CK CAS WE ODT CK CKE CK WE CAS D5 ODT CK CKE CK WE CAS D6 A[O:N]/BA[N:O] ZQ ODT CK CKE CK D7 A[N:O]/BA[N:O] ZQ WE RAS CS A[N:O]/BA[N:O] ODT CK CKE CK ZQ A[O:N]/BA[N:O] DQS DQS TDQS TDQS DQ [7:0] ZQ D0 RCASB DQS7 DQS7 DM7/DQS16 DQS16 DQ[63:56] RAS DQS DQS TDQS TDQS DQ [7:0] CS DQS6 DQS6 DM6/DQS15 DQS15 DQ[55:48] D4 CAS ODT A[O:N]/BA[N:O] A[N:O]/BA[N:O] ODT DQS DQS TDQS TDQS DQ [7:0] RAS ODT ODT CK C
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RODT1B A[N:O]/BA[N:O] ODT A[N:O]/BA[N:O] A[O:N]/BA[N:O] ODT ODT ODT CK CKE CK CKE A[N:O]/BA[N:O] PCK1B CK WE CK CKE CK CKE CK WE WE D16 CAS ZQ RAS DQS DQS TDQS TDQS DQ [7:0] CK WE D15 CAS CS ZQ RAS DQS DQS TDQS TDQS DQ [7:0] CK RAS CS CAS D14 CAS CS RAS A[N:O]/BA[N:O] ZQ PCK1B RCKE1B RS1B A[N:O]B /BA[N:O]B A[N:O]/BA[N:O] D13 DQS DQS TDQS TDQS DQ [7:0] CS ODT CK CKE ZQ A[N:O]/BA[N:O] ODT CK CKE CK CKE ODT ODT CK CKE CK DQS DQS TDQS TDQS DQ [7:0] A[N:O]/BA[N:O]
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4GB, 512Mx72 Module(2Rank of x8) - page2 S0 1:2 S1 S[3:2] NC BA[N:0] R E G I S T E R / P L L A[N:0] RAS CAS WE CKE0 CKE1 ODT0 ODT1 CK0 120 Ω ±5% CK0 CK1 CK1 120 Ω ±5% PAR_IN RS0A → CS0: SDRAMs D[3:0], D8 RS0B → CS0: SDRAMs D[7:4] RS1A → CS1: SDRAMs D[12:9], D17 RS1B → CS1: SDRAMs D[16:13] RBA[N:0]A → BA[N:0]: SDRAMs D[3:0], D[12:8], D17 RBA[N:0]B → BA[N:0]: SDRAMs D[7:4], D[16:13] RA[N:0]A → A[N:0]: SDRAMs D[3:0], D[12:8], D17 RA[N:0]B → A[N:0]: SDRAMs D[7:4], D[16:13] RRASA → RAS: SDRAMs D[3:0], D[
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ODT CK CKE CK VSS A[O:N]/BA[O:N] ODT CK CKE CK WE CAS VSS A[O:N]/BA[O:N] ODT CK CKE CK VSS A[O:N]/BA[O:N] ODT CK CK CKE D15 ODT CK CKE VSS D16 A[O:N]/BA[O:N] ZQ CK RAS CS CAS ZQ CAS RAS CS D14 CAS ODT A[O:N]/BA[O:N] A[O:N]/BA[O:N] ODT CK CKE D7 RAS DQS DQS DM DQ [3:0] ZQ WE DQS16 DQS16 VSS DQ[63:60] ZQ RAS A[O:N]/BA[O:N] ODT CK CKE CK CKE D6 D13 WE DQS DQS DM DQ [3:0] ZQ ZQ WE DQS15 DQS15 VSS DQ[55;52] CS VSS VSS A[O:N]/BA[O:N] DQS DQS DM DQ [3:
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4GB, 512Mx72 Module(1Rank of x4) - page2 S0 S1 1:2 BA[N:0] R E A[N:0] G RAS I S T E R / P L L CAS WE CKE0 ODT0 RS0A → CS0: SDRAMs D[3:0], D[12:8], D17 RS0B → CS0: SDRAMs D[7:4], D[16:13] RS1A → CS1: SDRAMs D[12:9], D17 RS1B → CS1: SDRAMs D[16:13] RBA[N:0]A → BA[N:0]: SDRAMs D[3:0], D[12:8], D17 RBA[N:0]B → BA[N:0]: SDRAMs D[7:4], D[16:13] RA[N:0]A → A[N:0]: SDRAMs D[3:0], D[12:8], D17 RA[N:0]B → A[N:0]: SDRAMs D[7:4], D[16:13] RRASA → RAS: SDRAMs D[3:0], D[12:8], D17 RRASB → RAS: SDRAMs D[7:4], D[1
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CS CS CS CS DQS DQS TDQS TDQS DQ [7:0] ZQ DQS8 DQS8 DM8/TDQS17 TDQS17 CB[7:0] DQS DQS TDQS TDQS DQ [7:0] ZQ Rev. 1.0 / Jul.
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BA[N:O] VDD ODT A[N:O] WCKE1 PCK2 CK CK WE CKE PCK2 BA[N:O] ODT A[N:O] CKE CK CK ODT A[N:O] BA[N:O] ODT BA[N:O] CKE CK A[N:O] DQS DQS TDQS TDQS DQ [7:0] ZQ CKE CK U36 WE CAS DQS DQS TDQS TDQS DQ [7:0] ZQ CK CAS WE WE CAS U35 CK CAS CS3 CS RAS RAS CS CS RAS BA[N:O] A[N:O] A[N:O] BA[N:O] CKE ODT U34 DQS DQS TDQS TDQS DQ [7:0] ZQ CS A[N:O] BA[N:O] ODT CKE CKE ODT CK U28 DQS DQS TDQS TDQS DQ [7:0] ZQ RAS A[N:O] BA[N:O] WCKE0 WODT1 CKE ODT PCK2 PCK
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8GB, 1Gx72 Module(4Rank of x8) - page3 S0 S1 S2 S3 BA[N:0] 1:2 R E G I S T E R / P L L A[N:0] RAS CAS WE CKE0 CKE1 ODT0 ODT1 CK0 CK0 CK1 CK1 120 Ω ±5% PAR_IN CS0 → CS0: SDRAMs U[10:2] CS1 → CS1: SDRAMs U[19:11] CS2 → CS2: SDRAMs U[28:20] CS3 → CS3: SDRAMs U[37:29] WBA[N:0] → BA[N:0]: SDRAMs U[6:2], U[15:11], U[24:20], U[33:29] EBA[N:0] → BA[N:0]: SDRAMs U[10:7], U[19:16], U[28:25], U[37:34] WA[N:0] → A[N:0]: SDRAMs U[6:2], U[15:11], U[24:20], U[33:29] EA[N:0] → A[N:0]: SDRAMs U[10:7], U[19:16], U[28:
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DQS0 DQS0 VSS DQ[3:0] DQS DQS DM DQ [3:0] Vtt Rev. 1.0 / Jul.
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R0DT1B A[N:O]/BA[N:O] ODT A[N:O]/BA[N:O] A[N:O]/BA[N:O] ODT ODT ODT CK CKE CK CKE CK CKE A[N:O]/BA[N:O] RCKE1B PCK1B PCK1B CK CKE CK WE D24 WE CAS DQS DQS DM DQ [3:0] CK D33 WE CAS RAS CS DQS DQS DM DQ [3:0] CK WE D23 CK CAS RAS CS DQS DQS DM DQ [3:0] RAS A[N:O]B /BA[N:O]B RS1B D31 CAS RAS CS DQS DQS DM DQ [3:0] CS ODT A[N:O]/BA[N:O] A[N:O]/BA[N:O] A[N:O]/BA[N:O] ODT CK CKE CK CKE ODT ODT CK CKE D6 A[N:O]/BA[N:O] PCK0B RCKE0B RWEB RODT0B CK CKE CK CK CAS CAS
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8GB, 1Gx72 Module(2Rank of x4) - page3 S0 1:2 S1 R E G I S T E R / P L L BA[N:0] A[N:0] RAS CAS WE CKE0 CKE1 ODT0 ODT1 CK0 CK0 CK1 CK1 120 Ω ±5% PAR_IN RS0A → CS0: SDRAMs D[3:0], D[12:8], D17 RS0B → CS0: SDRAMs D[7:4], D[16:13] RS1A → CS1: SDRAMs D[21:18], D[30:26], D35 RS1B → CS1: SDRAMs D[25:22], D[34:31] RBA[N:0]A → BA[N:0]: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35 RBA[N:0]B → BA[N:0]: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31] RA[N:0]A → A[N:0]: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26
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VSS DQS0 DQS0 VSS DQ[3:0] ZQ DQS DQS DM DQ [3:0] Rev. 1.0 / Jul.
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VSS DQS9 DQS9 VSS DQ[7:4] ZQ DQS DQS DM DQ [3:0] Rev. 1.0 / Jul.
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VSS DQS7 DQS7 VSS DQ[59:56] ZQ DQS DQS DM DQ [3:0] Rev. 1.0 / Jul.
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BRCKE1B VDD A[N:O]/BA[N:O] CK CKE CK ODT A[N:O]/BA[N:O] A[N:O]/BA[N:O] ODT ODT ODT CK CKE CK CKE CK CKE CAS WE WE CK CK WE WE D54 CK CS RAS RAS CS CAS CAS RAS CS D56 ZQ DQS DQS DM DQ [3:0] CS A[N:O]/BA[N:O] D58 ZQ DQS DQS DM DQ [3:0] CAS A[N:O]/BA[N:O] A[N:O]/BA[N:O] ODT ODT CK CKE WE D55 D60 ZQ DQS DQS DM DQ [3:0] RAS A[N:O]/BA[N:O] CK CKE CK ODT ODT CK CKE CK CKE VSS ZQ DQS DQS DM DQ [3:0] ZQ DQS DQS DM DQ [3:0] A[N:O]/BA[N:O] BRS3B BRA[N:O]B /BRBA[N:O]B BPCK0B
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16GB, 2Gx72 Module(4Rank of x4) - page5 S0 1:2 WE R E G I S T E R / P L L CKE0 A S1 BA[N:0] A[N:0] RAS CAS CKE1 ODT0 CK0 120 Ω ±5% CK0 PAR_IN RESET ARS0A → CS1: SDRAMs D1,D3,D5,D7 D9, D19, D21, D23, D25, D27 ARS0B → CS1: SDRAMs D11, D13, D15, D17, D29, D31, D33, D35 S2 1:2 S3 ARS1A → CS0: SDRAMs D0, D2, D4, D6, D8, D18, D20, D22, D24, D26 ARS1B → CS0: SDRAMs D10, D12, D14, D16, D28, D30, D32, D34 ARBA[N:0]A → BA[N:0]: SDRAMs D[9:0],D[27:18] BA[N:0] ARBA[N:0]B → BA[N:0]: SDRAMs D[17:10],D[35
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Absolute Maximum Ratings Absolute Maximum DC Ratings Absolute Maximum DC Ratings Symbol VDD VDDQ Parameter Rating Units Notes Voltage on VDD pin relative to Vss - 0.4 V ~ 1.80 V V 1,3 Voltage on VDDQ pin relative to Vss - 0.4 V ~ 1.80 V V 1,3 - 0.4 V ~ 1.80 V V 1 C 1, 2 VIN, VOUT Voltage on any pin relative to Vss TSTG -55 to +100 Storage Temperature o Notes: 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
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AC & DC Operating Conditions Recommended DC Operating Conditions Recommended DC Operating Conditions Symbol VDD VDDQ Parameter Rating Units Notes 1.575 V 1,2 1.575 V 1,2 Min. Typ. Max. Supply Voltage 1.425 1.500 Supply Voltage for Output 1.425 1.500 Notes: 1. Under all conditions, VDDQ must be less than or equal to VDD. 2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together. Rev. 1.0 / Jul.
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AC & DC Input Measurement Levels AC and DC Logic Input Levels for Single-Ended Signals AC and DC Input Levels for Single-Ended Command and Address Signals Single Ended AC and DC Input Levels for Command and ADDress DDR3-800/1066/1333/1600 Symbol Min VIH.CA(DC100) VIL.CA(DC100) VIH.CA(AC175) VIL.CA(AC175) VIH.CA(AC150) VIL.CA(AC150) VIH.CA(AC135) VIL.CA(AC135) VIH.CA(AC125) VIL.CA(AC125) VRefCA(DC) DDR3-1866 Parameter DC input logic high Vref + 0.100 DC input logic low VSS AC input logic high Vref + 0.
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AC and DC Input Levels for Single-Ended Signals DDR3 SDRAM will support two Vih/Vil AC levels for DDR3-800 and DDR3-1066 as specified in the table below. DDR3 SDRAM will also support corresponding tDS values (Table 41 and Table 47 in “ DDR3 Device Operation”) as well as derating tables in Table 44 of “DDR3 Device Operation” depending on Vih/Vil AC levels. Single Ended AC and DC Input Levels for DQ and DM Symbol VIH.DQ(DC100) VIL.DQ(DC100) VIH.DQ(AC175) VIL.DQ(AC175) VIH.DQ(AC150) VIL.DQ(AC150) VIH.
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Vref Tolerances The dc-tolerance limits and ac-noise limits for the reference voltages VRefCA and VRefDQ are illustrated in figure below. It shows a valid reference voltage VRef (t) as a function of time. (VRef stands for VRefCA and VRefDQ likewise). VRef (DC) is the linear average of VRef (t) over a very long period of time (e.g. 1 sec). This average has to meet the min/max requirements in the table "Differential Input Slew Rate Definition" on page 38.
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AC and DC Logic Input Levels for Differential Signals Differential signal definition tDVAC Differential Input Voltage(i.e.DQS - DQS#, CK - CK#) VIL.DIFF.AC.MIN VIL.DIFF.MIN 0 half cycle VIL.DIFF.MAX VIL.DIFF.AC.MAX tDVAC time Definition of differential ac-swing and “time above ac-level” tDVAC Rev. 1.0 / Jul.
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Differential swing requirements for clock (CK - CK) and strobe (DQS-DQS) Differential AC and DC Input Levels DDR3-800, 1066, 1333, 1600 Symbol Parameter VIHdiff VILdiff VIHdiff (ac) VILdiff (ac) Unit Notes Differential input high Differential input logic low Differential input high ac Differential input low ac Min Max + 0.180 Note 3 2 x (VIH (ac) - Vref) Note 3 Note 3 - 0.180 Note 3 2 x (VIL (ac) - Vref) V V V V 1 1 2 2 Notes: 1. Used to define a differential signal slew-rate. 2.
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Single-ended requirements for differential signals Each individual component of a differential signal (CK, DQS, DQSL, DQSU, CK, DQS, DQSL, of DQSU) has also to comply with certain requirements for single-ended signals. CK and CK have to approximately reach VSEHmin / VSELmax (approximately equal to the ac-levels (VIH (ac) / VIL (ac)) for ADD/CMD signals) in every half-cycle.
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Single-ended levels for CK, DQS, DQSL, DQSU, CK, DQS, DQSL or DQSU DDR3-800, 1066, 1333, 1600 Symbol VSEH VSEL Parameter Single-ended high level for strobes Single-ended high level for Ck, CK Single-ended low level for strobes Single-ended low level for CK, CK Unit Notes Min Max (VDD / 2) + 0.175 (VDD /2) + 0.175 Note 3 Note 3 Note 3 Note 3 (VDD / 2) = 0.175 (VDD / 2) = 0.175 V V V V 1,2 1,2 1,2 1,2 Notes: 1.
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Differential Input Cross Point Voltage To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross point voltage of differential input signals (CK, CK and DQS, DQS) must meet the requirements in table below.
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Slew Rate Definitions for Single-Ended Input Signals See 7.5 “Address / Command Setup, Hold and Derating” on page 134 in “DDR3 Device Operation” for single-ended slew rate definitions for address and command signals.  See 7.6 “Data Setup, Hold and Slew Rate Derating” on page 142 in “DDR3 Device Operation” for singleended slew rate definition for data signals.
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AC & DC Output Measurement Levels Single Ended AC and DC Output Levels Table below shows the output levels used for measurements of single ended signals. Single-ended AC and DC Output Levels Symbol Parameter VOH(DC) DC output high measurement level (for IV curve linearity) VOM(DC) DC output mid measurement level (for IV curve linearity) VOL(DC) VOH(AC) DDR3-800, 1066, 1333 and 1600 0.8 x VDDQ Unit Notes V V DC output low measurement level (for IV curve linearity) 0.5 x VDDQ 0.
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Single Ended Output Slew Rate When the Reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOL(AC) and VOH(AC) for single ended signals are shown in table and figure below.
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Differential Output Slew Rate With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOLdiff (AC) and VOHdiff (AC) for differential signals as shown in table and figure below.
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Reference Load for AC Timing and Output Slew Rate Figure below represents the effective reference load of 25 ohms used in defining the relevant AC timing parameters of the device as well as output slew rate measurements. It is not intended as a precise representation of any particular system environment or a depiction of the actual load presented by a production tester. System designers should use IBIS or other simulation tools to correlate the timing reference load to a system environment.
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Overshoot and Undershoot Specifications Address and Control Overshoot and Undershoot Specifications AC Overshoot/Undershoot Specification for Address and Control Pins DDR3- DDR3- DDR3- DDR3- DDR3- Parameter 800 Maximum peak amplitude allowed for overshoot area. (See Figure below) Maximum peak amplitude allowed for undershoot area. (See Figure below) Maximum overshoot area above VDD (See Figure below) Maximum undershoot area below VSS (See Figure below) 1066 1333 0.4 0.4 0.67 0.67 0.4 0.4 0.5 0.5 0.
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Clock, Data, Strobe and Mask Overshoot and Undershoot Specifications AC Overshoot/Undershoot Specification for Clock, Data, Strobe and Mask DDR3- DDR3- DDR3- DDR3- DDR3- Parameter Maximum peak amplitude allowed for overshoot area. (See Figure below) Maximum peak amplitude allowed for undershoot area. (See Figure below) Maximum overshoot area above VDD (See Figure below) Maximum undershoot area below VSS (See Figure below) 800 1066 1333 1600 1866 0.4 0.4 0.25 0.25 0.4 0.4 0.19 0.19 0.4 0.4 0.15 0.
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Refresh parameters by device density Refresh parameters by device density Parameter REF command ACT or REF command time Average periodic refresh interval Rev. 1.0 / Jul. 2012 RTT_Nom Setting 512Mb 1Gb 2Gb 4Gb 8Gb tRFC 90 110 160 260 350 ns 7.8 7.8 7.8 7.8 7.8 us 3.9 3.9 3.9 3.9 3.
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Standard Speed Bins DDR3 SDRAM Standard Speed Bins include tCK, tRCD, tRP, tRAS and tRC for each corresponding bin. DDR3-800 Speed Bins For specific Notes See "Speed Bin Table Notes" on page 51. Speed Bin DDR3-800E CL - nRCD - nRP 6-6-6 Unit Parameter Symbol min max Internal read command to first data tAA 15 20 ns ACT to internal read or write delay time tRCD 15 — ns PRE command period tRP 15 — ns ACT to ACT or REF command period tRC 52.
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DDR3-1066 Speed Bins For specific Notes See "Speed Bin Table Notes" on page 51. Speed Bin DDR3-1066F CL - nRCD - nRP Parameter Symbol Unit 7-7-7 min max Note Internal read command to first data tAA 13.125 20 ns ACT to internal read or write delay time tRCD 13.125 — ns PRE command period tRP 13.125 — ns ACT to ACT or REF command period tRC 50.625 — ns ACT to PRE command period tRAS 37.5 9 * tREFI ns CWL = 5 tCK(AVG) 2.5 3.
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DDR3-1333 Speed Bins For specific Notes See "Speed Bin Table Notes" on page 51. Speed Bin DDR3-1333H CL - nRCD - nRP Parameter Symbol Unit 9-9-9 min max Note Internal read command to first data tAA 13.5 (13.125)5,10 20 ns ACT to internal read or write delay time tRCD 13.5 (13.125)5,10 — ns PRE command period tRP 13.5 (13.125)5,10 — ns ACT to ACT or REF command period tRC 49.5 (49.125)5,10 — ns ACT to PRE command period tRAS 36 9 * tREFI ns CWL = 5 tCK(AVG) 2.5 3.
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DDR3-1600 Speed Bins For specific Notes See "Speed Bin Table Notes" on page 51. Speed Bin DDR3-1600K CL - nRCD - nRP Parameter Symbol Unit 11-11-11 min max Note Internal read command to first data tAA 13.75 (13.125)5,10 20 ns ACT to internal read or write delay time tRCD 13.75 (13.125)5,10 — ns PRE command period tRP 13.75 (13.125)5,10 — ns ACT to ACT or REF command period tRC 48.75 (48.
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DDR3-1866 Speed Bins For specific Notes See "Speed Bin Table Notes" on page 51.
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Speed Bin Table Notes Absolute Specification (TOPER; VDDQ = VDD = 1.5V +/- 0.075 V); 1. The CL setting and CWL setting result in tCK(AVG).MIN and tCK(AVG).MAX requirements. When making a selection of tCK(AVG), both need to be fulfilled: Requirements from CL setting as well as requirements from CWL setting. 2. tCK(AVG).MIN limits: Since CAS Latency is not purely analog - data and strobe output are synchronized by the DLL - all possible intermediate frequencies may not be guaranteed.
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Environmental Parameters Symbol Parameter Rating TOPR Operating temperature See Note HOPR Operating humidity (relative) 10 to 90 TSTG Storage temperature HSTG Storage humidity (without condensation) PBAR Barometric Pressure (operating & storage) Units Notes 3 % 1 o C 1 5 to 95 % 1 105 to 69 K Pascal 1, 2 -50 to +100 Note: 1. Stress greater than those listed may cause permanent damage to the device.
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IDD and IDDQ Specification Parameters and Test Conditions IDD and IDDQ Measurement Conditions In this chapter, IDD and IDDQ measurement conditions such as test load and patterns are defined. Figure 1. shows the setup and test load for IDD and IDDQ measurements. • IDD currents (such as IDD0, IDD1, IDD2N, IDD2NT, IDD2P0, IDD2P1, IDD2Q, IDD3N, IDD3P, IDD4R, IDD4W, IDD5B, IDD6, IDD6ET and IDD7) are measured as time-averaged currents with all VDD balls of the DDR3 SDRAM under test tied together.
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IDDQ (optional) IDD VDD VDDQ RESET CK/CK DDR3 SDRAM CKE CS RAS, CAS, WE DQS, DQS DQ, DM, TDQS, TDQS A, BA ODT ZQ VSS RTT = 25 Ohm VDDQ/2 VSSQ Figure 1 - Measurement Setup and Test Load for IDD and IDDQ (optional) Measurements [Note: DIMM level Output test load condition may be different from above Application specific memory channel environment IDDQ Test Load Channel IO Power Simulation IDDQ Simulation IDDQ Simulation Correction Channel IO Power Number Figure 2 - Correlation from simulated
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Table 1 -Timings used for IDD and IDDQ Measurement-Loop Patterns Symbol tCK DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866 7-7-7 9-9-9 11-11-11 13-13-13 1.875 1.5 1.25 1.
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Symbol Description Precharge Standby Current CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank IDD2N Address Inputs: partially toggling according to Table 5; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 5.
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Symbol Description Operating Burst Read Current CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: High between RD; Command, Address, IDD4R Bank Address Inputs: partially toggling according to Table 7; Data IO: seamless read data burst with different data between one burst and the next one according to Table 7; DM: stable at 0; Bank Activity: all banks open, RD commands cycling through banks: 0,0,1,1,2,2,...
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Symbol Description Operating Bank Interleave Read Current CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, NRRD, nFAW, CL: see Table 1; BL: 8a),f); AL: CL-1; CS: High between ACT and RDA; Command, Address, Bank Address Inputs: partially toggling according to Table IDD7 10; Data IO: read data burst with different data between one burst and the next one according to Table 10; DM: stable at 0; Bank Activity: two times interleaved cycling through banks (0, 1,...
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Command CS RAS CAS WE ODT BA[2:0] A[15:11] A[10] A[9:7] A[6:3] A[2:0] 0 ACT 0 0 1 1 0 0 00 0 0 0 0 - 1,2 D, D 1 0 0 0 0 0 00 0 0 0 0 - D, D 1 1 1 1 0 0 00 0 0 0 0 - 0 0 0 - Cycle Number Datab) Sub-Loop CKE CK, CK Table 3 - IDD0 Measurement-Loop Patterna) 0 3,4 ... nRAS Static High toggling ... repeat pattern 1...4 until nRAS - 1, truncate if necessary PRE 0 0 1 0 0 0 00 0 repeat pattern 1...
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Command CS RAS CAS WE ODT BA[2:0] A[15:11] A[10] A[9:7] A[6:3] A[2:0] 0 ACT 0 0 1 1 0 0 00 0 0 0 0 - 1,2 D, D 1 0 0 0 0 0 00 0 0 0 0 - D, D 1 1 1 1 0 0 00 0 0 0 0 - 0 0 00000000 0 0 - Cycle Number Datab) Sub-Loop CKE CK, CK Table 4 - IDD1 Measurement-Loop Patterna) 0 3,4 ... nRCD ... nRAS Static High toggling ... repeat pattern 1...4 until nRCD - 1, truncate if necessary RD 0 1 0 1 0 0 00 0 0 repeat pattern 1...
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Static High CS RAS CAS WE ODT BA[2:0] A[15:11] A[10] A[9:7] A[6:3] A[2:0] 0 D 1 0 0 0 0 0 0 0 0 0 0 - 1 D 1 0 0 0 0 0 0 0 0 0 0 - 2 D 1 1 1 1 0 0 0 0 0 F 0 - 3 D 1 1 1 1 0 0 0 0 0 F 0 - Cycle Number Command 0 toggling Datab) Sub-Loop CKE CK, CK Table 5 - IDD2N and IDD3N Measurement-Loop Patterna) 1 4-7 repeat Sub-Loop 0, use BA[2:0] = 1 instead 2 8-11 repeat Sub-Loop 0, use BA[2:0] = 2 instead 3 12-15 repeat Sub-Loop 0, use
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CS RAS CAS WE ODT BA[2:0] A[15:11] A[10] A[9:7] A[6:3] A[2:0] 0 RD 0 1 0 1 0 0 00 0 0 0 0 00000000 1 D 1 0 0 0 0 0 00 0 0 0 0 - 2,3 D,D 1 1 1 1 0 0 00 0 0 0 0 - 4 RD 0 1 0 1 0 0 00 0 0 F 0 00110011 5 D 1 0 0 0 0 0 00 0 0 F 0 - D,D 1 1 1 1 0 0 00 0 0 F 0 - Cycle Number Command Static High 0 toggling Datab) Sub-Loop CKE CK, CK Table 7 - IDD4R and IDDQ4R Measurement-Loop Patterna) 6,7 1 8-15 repeat Sub-Loo
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Command CS RAS CAS WE ODT BA[2:0] A[15:11] A[10] A[9:7] A[6:3] A[2:0] 0 0 REF 0 0 0 1 0 0 0 0 0 0 0 - 1 1.2 D, D 1 0 0 0 0 0 00 0 0 0 0 - D, D 1 1 1 1 0 0 00 0 0 F 0 - Cycle Number Datab) Sub-Loop CKE CK, CK Table 9 - IDD5B Measurement-Loop Patterna) Static High toggling 3,4 2 5...8 repeat cycles 1...4, but BA[2:0] = 1 9...12 repeat cycles 1...4, but BA[2:0] = 2 13...16 repeat cycles 1...4, but BA[2:0] = 3 17...20 repeat cycles 1...
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Table 10 - IDD7 Measurement-Loop Patterna) 2 3 4 Static High 5 6 7 8 9 10 4*nRRD nFAW nFAW+nRRD nFAW+2*nRRD nFAW+3*nRRD nFAW+4*nRRD 2*nFAW+0 2*nFAW+1 2&nFAW+2 11 2*nFAW+nRRD 2*nFAW+nRRD+1 2&nFAW+nRRD+2 12 13 2*nFAW+2*nRRD 2*nFAW+3*nRRD 14 2*nFAW+4*nRRD 15 16 17 18 3*nFAW 3*nFAW+nRRD 3*nFAW+2*nRRD 3*nFAW+3*nRRD 19 3*nFAW+4*nRRD 00110011 - 0 - 0 - 0 0 0 00110011 - 0 0 0 00000000 - 0 - 0 - A[10] 0 0 0 ODT 00000000 - WE 0 0 0 CAS ACT 0 0 1 1 0 0 00 0 0 0 RDA 0 1 0 1 0 0 00 1
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IDD Specifications (Tcase: 0 to 95oC) * Module IDD values in the datasheet are only a calculation based on the component IDD spec and register power. The actual measurements may vary according to DQ loading cap.
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4GB, 512M x 72 R-DIMM: HMT351R7CFR4C Symbol IDD0 IDD1 IDD2N IDD2NT IDD2P0 IDD2P1 DDR3 1333 1484 1664 1124 1214 444 498 DDR3 1600 1574 1754 1214 1304 444 498 DDR3 1866 1574 1844 1214 1304 444 534 Unit mA mA mA mA mA mA IDD2Q IDD3N IDD3P IDD4R IDD4W IDD5B IDD6 IDD6ET IDD7 1178 1250 498 2384 2294 2834 444 480 4004 1178 1304 534 2654 2474 2924 444 480 4094 1214 1304 552 3014 2924 2924 444 480 4364 mA mA mA mA mA mA mA mA mA DDR3 1600 1979 2069 1664 1844 660 768 1592 1844 840 2519 2429 2654 660 732 323
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8GB, 1G x 72 R-DIMM: HMT31GR7CFR4C Symbol IDD0 IDD1 IDD2N IDD2NT IDD2P0 IDD2P1 DDR3 1333 1844 2024 1484 1664 660 768 DDR3 1600 2114 2294 1664 1844 660 768 DDR3 1866 2114 2384 1664 1844 660 840 Unit mA mA mA mA mA mA IDD2Q IDD3N IDD3P IDD4R IDD4W IDD5B IDD6 IDD6ET IDD7 1592 1736 768 2744 2654 3194 660 732 4364 1592 1844 840 3194 3014 3464 660 732 4634 1664 1844 879 3554 3464 3464 660 732 4904 mA mA mA mA mA mA mA mA mA DDR3 1600 3194 3374 2564 2924 1092 1308 2420 2924 1452 4274 4094 4544 1092 1236
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Module Dimensions 256Mx72 - HMT325R7CFR8C Front 133.35 128.95 Detail A Detail B 1 Detail C 120 1 2X3.00±0.10 5.175 47.00 30.00 Registering Clock Driver 4X3.00±0.10 9.50 17.30 SPD/TS 2.10±0.15 71.00 5.0 Back 121 240 1 2x R0.75 Max Side 3.43mm max 0.80± 0.05 3.80 0.35 2.50±0.20 2.50 2.50±0.20 1.20± 0.15 3± 0.1 Detail of Contacts C Detail of Contacts B 0.3 ±0.15 Detail of Contacts A 0.3~0.1 1.00 1.50 ±0.10 5.00 1.27±010mm max Note: 1.  0.
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512Mx72 - HMT351R7CFR8C Front 133.35 128.95 SPD/TS 2.10±0.15 Detail C Detail B 1 120 1 2X3.00±0.10 5.175 47.00 30.00 4X3.00±0.10 9.50 17.30 23.30 Registering Clock Driver Detail A 71.00 5.0 Back 121 240 1 2x R0.75 Max Side 3.43mm max 0.80± 0.05 2.50±0.20 3.80 2.50 2.50±0.20 0.35 3± 0.1 Detail of Contacts C Detail of Contacts B 1.20± 0.15 0.3 ±0.15 Detail of Contacts A 0.3+0.1 1.00 1.50 ±0.10 5.00 1.27±010mm max Note: 1.  0.
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512Mx72 - HMT351R7CFR4C Front 133.35 128.95 SPD/TS 2.10±0.15 Detail C Detail B 1 120 1 2X3.00±0.10 5.175 47.00 30.00 4X3.00±0.10 9.50 17.30 23.30 Registering Clock Driver Detail A 71.00 5.0 Back 121 240 1 2x R0.75 Max Side 3.43mm max 0.80± 0.05 2.50±0.20 3.80 2.50 2.50±0.20 0.35 3± 0.1 Detail of Contacts C Detail of Contacts B 1.20± 0.15 0.3 ±0.15 Detail of Contacts A 0.3+0.1 1.00 1.50 ±0.10 5.00 1.27±010mm max Note: 1.  0.
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1Gx72 - HMT31GR7CFR8C Front 133.35 Detail B 128.95 SPD/TS 2.10±0.15 1 120 1 2X3.00±0.10 47.00 Detail C 5.175 9.50 17.30 23.30 Registering Clock Driver 4X3.00±0.10 30.00 Detail A 71.00 5.0 Detail D Back 121 240 1 2x R0.75 Max Side Detail of Contacts A Detail of Contacts D Detail of Contacts C Detail of Contacts B 1.20± 0.15 3.46mm max 0.80± 0.05 2.50 14.90 2.50±0.20 0.3 ±0.15 0.35 2.50±0.20 13.60 3± 0.1 3.80 0.4 0.3~0.1 1.00 1.50 ±0.10 5.00 1.27±010mm max Note: 1.
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1Gx72 - HMT31GR7CFR8C - Heat Spreader Front 133.75 133.35 127 42.7 2.786 8 36.7 22.00 30.20 6.3 2.15 7.74 14.214 Registering Clock Driver 3.69 5.39 10 20.9 6.35 120 1 7.36 33.4 33.4 46.46 80.54 119.64 57.2 Back 15.36 Registering Clock Driver 121 22.00 2.7 240 2x R0.75 Max Side 7.19mm max 1.27±010mm max Note: 1.  0.13 tolerance on all dimensions unless otherwise stated. 2.In order to uninstall FDHS, please contact sales administrator. Rev. 1.0 / Jul.
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1Gx72 - HMT31GR7CFR4C Front 133.35 Detail B 128.95 SPD/TS 2.10±0.15 1 120 1 2X3.00±0.10 47.00 Detail C 5.175 9.50 17.30 23.30 Registering Clock Driver 4X3.00±0.10 30.00 Detail A 71.00 5.0 Detail D Back 121 240 1 2x R0.75 Max Side Detail of Contacts A Detail of Contacts D Detail of Contacts C Detail of Contacts B 1.20± 0.15 3.46mm max 0.80± 0.05 2.50 14.90 2.50±0.20 0.3 ±0.15 0.35 2.50±0.20 13.60 3± 0.1 3.80 0.4 0.3~0.1 1.00 1.50 ±0.10 5.00 1.27±010mm max Note: 1.
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1Gx72 - HMT31GR7CFR4C - Heat Spreader Front 133.75 133.35 127 42.7 2.786 8 36.7 22.00 30.20 6.3 2.15 7.74 14.214 Registering Clock Driver 3.69 5.39 10 20.9 6.35 120 1 7.36 33.4 33.4 46.46 80.54 119.64 57.2 Back 15.36 Registering Clock Driver 121 22.00 2.7 240 2x R0.75 Max Side 7.19mm max 1.27±010mm max Note: 1.  0.13 tolerance on all dimensions unless otherwise stated. 2.In order to uninstall FDHS, please contact sales administrator. Rev. 1.0 / Jul.
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2Gx72 - HMT42GR7CMR4C Front 133.35 Detail B 128.95 SPD/TS DDP DDP DDP DDP DDP DDP DDP DDP DDP Detail A DDP 1 120 1 2X3.00±0.10 47.00 Detail C 5.175 9.50 17.30 23.30 DDP DDP DDP DDP DDP DDP DDP DDP Registering Clock Driver 4X3.00±0.10 30.00 2.10±0.15 71.00 5.0 Detail D Back DDP DDP DDP DDP DDP DDP DDP DDP DDP DDP DDP DDP DDP DDP DDP DDP DDP DDP 121 240 1 2x R0.
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2Gx72 - HMT42GR7CMR4C - Heat Spreader Front 133.75 133.35 127 42.7 2.786 8 36.7 22.00 30.20 6.3 2.15 7.74 14.214 Registering Clock Driver 3.69 5.39 10 20.9 6.35 120 1 7.36 33.4 33.4 46.46 80.54 119.64 57.2 Back 15.36 Registering Clock Driver 121 22.00 2.7 240 2x R0.75 Max Side 7.19mm max 1.27±010mm max Note: 1.  0.13 tolerance on all dimensions unless otherwise stated. 2.In order to uninstall FDHS, please contact sales administrator. Rev. 1.0 / Jul.