Brocade Fabric OS Troubleshooting and Diagnostics Guide v6.2.0 (53-1001187-01, April 2009)

Fabric OS Troubleshooting and Diagnostics Guide 35
53-1001187-01
Segmented fabrics
3
[-nframes count]—Specify the number of frames to send.
[-lb_mode mode]—Select the loopback point for the test.
[-spd_mode mode]—Select the speed mode for the test.
[-ports itemlist]—Specify a list of user ports to test.
Testing components to and from the HBA
1. Connect to the switch and log in as admin.
2. Enter the portTest command (see the Fabric OS Command Reference for information on the
command options).
See Table 7 on page 35 for a list of additional tests that can be used to determine the switch
components that are not functioning properly. See the Fabric OS Command Reference for
additional command information.
Segmented fabrics
Fabric segmentation is generally caused by one of the following conditions:
Incompatible fabric parameters (see “Reconciling fabric parameters individually,” next).
Incorrect PID setting (see Fabric OS Administrator’s Guide).
Incompatible zoning configuration (see Chapter 9, “Zone Issues”).
Domain ID conflict (see “Reconciling fabric parameters individually” on page 36).
Fabric ID conflict (see Chapter 7, “Virtual Fabrics”).
Incompatible security policies.
Incorrect fabric mode.
Incorrect policy distribution.
There are a number of settings that control the overall behavior and operation of the fabric. Some
of these values, such as the domain ID, are assigned automatically by the fabric and can differ
from one switch to another in the fabric. Other parameters, such as the BB credit, can be changed
for specific applications or operating environments, but must be the same among all switches to
allow the formation of a fabric.
The following fabric parameters must be identical on each switch for a fabric to merge:
TABLE 7 Switch component tests
Test Function
portLoopbackTest Performs a functional test of port N to N path. Verifies the functional components of the
switch.
turboRamTest Verifies that the on chip SRAM located in the 2 Gbps ASIC is using the Turbo-Ram BIST
circuitry. This allows the BIST controller to perform the SRAM write and read operations at a
much faster rate.
Related Switch Test Option:
itemList Restricts the items to be tested to a smaller set of parameter values that you pass to the
switch.