Fault Codes DTC & Troubleshooting
Table Of Contents
- Cover
- Copyright
- SAFETY PRECAUTIONS
- Revision record
- PREFACE
- CONTENTS
- FIGURES
- TABLES
- 1 PRELIMINARY CHECKING
- 2 TROUBLESHOOTING
- 2.1 Troubleshooting Procedure
- 2.2 Troubleshooting Maps
- LPU
- ● None of the LED indicators comes on.
- ● The ERR indicator (LED) is lit.
- ● The remote I/O process produces outputs but does not accept inputs.
- ● The PCs OK output is OFF.
- ● The sequence program does not run.
- ● A DI/O or AI/O module mounted on the same mount base as is the LPU module does not runnormally.
- CMU
- PS Power supply
- FL.NET
- OD.RING, SD.LINK
- ET.NET (LQE520)
- SV.LINK
- J.NET, J.NET-INT
- IR.LINK
- CPU LINK Inter-CPU link
- RS-232C, RS-422
- D.NET
- EQ.LINK
- ET.NET (LQE720)
- RI/O
- J.Station
- IR.Station
- D.Station
- A.INPUT Analog input
- A.INPUT Scan-type analog input
- A.OUTPUT Analog output
- D.INPUT Digital input
- D.OUTPUT Digital output
- D.IN/OUT Digital input/output
- COUNTER Pulse counter
- Tool (personal computer) connection
- LPU
- 3 TECHNICAL SUPPORT INFORMATION
- 3.1 Remote I/O Troubleshooting
- 3.2 LPU Error Information Detail Table
- 3.3 Clearing the Entire Memory
- 3.4 Backing Up and Restoring
- 3.5 Performance
- 3.6 Address Space Maps
- 3.7 Registers
- 3.8 Memory Maps for Optional Modules
- 3.9 FL.NET (Model LQE500/LQE502) Error Information
- 3.10 OD.RING (Model LQE510/515) and SD.LINK (Model LQE530) Communication Traces
- 3.11 ET.NET (Model LQE520) Error Information
- 3.12 SV.LINK (Model LQE521) Error Information
- 3.13 J.NET (Model LQE541), J.NET-INT (Model LQE547), and IR.LINK (Model LQE548) Trace Information
- 3.14 RS-232C (Model LQE560) and RS-422 (Model LQE565) Trace Information
- 3.15 D.NET (Model LQE570/575) Statistical and Error Information
- 3.16 ET.NET (Model LQE720) Error Information
- 3.17 Error Freeze Information
- 3.18 Memory Dump Procedure
- 3.19 Network Information
- 3.20 Network Maintenance Commands
- 4 ERROR LOG INFORMATION
- 4.1 Displaying Error Log Information
- 4.2 Error Log Information and Required Actions
- 4.2.1 LPU (model LQP510) error log info and required actions
- 4.2.2 CMU (model LQP520) error log info and required actions
- 4.2.3 FL.NET (model LQE500/502) error log info and required actions
- 4.2.4 OD.RING (model LQE510/515) error log info and required actions
- 4.2.5 ET.NET (model LQE520) error log info and required actions
- 4.2.6 SV.LINK (model LQE521) error log info and required actions
- 4.2.7 SD.LINK (model LQE530) error log info and required actions
- 4.2.8 J.NET (model LQE541) / J.NET-INT (model LQE547) error log info and required actions
- 4.2.9 IR.LINK (model LQE548) error log info and required actions
- 4.2.10 CPU LINK (model LQE550) error log info and required actions
- 4.2.11 RS-232C (model LQE560) / RS-422 (model LQE565) error log info and required actions
- 4.2.12 D.NET (model LQE570/575) error log info and required actions
- 4.2.13 EQ.LINK (model LQE701) error log info and required actions
- 4.2.14 ET.NET (model LQE720) error log info and required actions
- 4.2.15 NCP-F (model LQE780-Z) error log info and required actions
- 4.2.16 LANCP (model LQE790-Z/795-Z) error log info and required actions
- 4.3 CMU Error Message Formats
- 4.4 RPDP Error Log Display Guide
- 4.4.1 Reading the error log
- 4.4.2 Types of error logs
- 4.4.3 Error log details and analysis
- (1) Program error
- (2) Macro parameter check error
- (3) I/O error
- (4) Watchdog timer timeout error
- (5) Module error
- (6) Kernel warning
- (7) Kernel information
- (8) System down -- system error
- (9) System down -- kernel trap
- (10) System down -- built-in subroutine error
- (11) System down -- built-in subroutine stoppage
- (12) ADT error
- (13) Memory error
- (14) System bus error
- (15) Other error
- 4.4.4 Reading the DHP trace information
- 4.5 Maintenance Commands
- 5 APPENDIX
- 5.1 Tool Error Messages
- 5.1.1 Error messages from the LADDER CHART SYSTEM
- 5.1.2 Error messages from the HI-FLOW SYSTEM
- 5.1.3 Error messages from the BASE SYSTEM
- 5.1.4 Error messages from the FL.NET SYSTEM
- 5.1.5 Error messages from the OD.RING/SD.LINK SYSTEM
- 5.1.6 Error messages from the ET.NET SYSTEM
- 5.1.7 Error messages from the J.NET SYSTEM
- 5.1.8 Error messages from the IR.LINK SYSTEM
- 5.1.9 Error messages from the CPU LINK SYSTEM
- 5.1.10 Error messages from the EXTERNAL SERIAL LINK SYSTEM
- 5.1.11 Error messages from the D.NET SYSTEM
- 5.1.12 Error messages from the EQ.LINK SYSTEM
- 5.1.13 Error messages from the BACKUP RESTORE SYSTEM
- 5.1.14 Error messages from the NX/Tools-S10V SYSTEM
- 5.1.15 Error messages from the tools
- 5.2 Trouble Report
- 5.1 Tool Error Messages
4 ERROR LOG INFORMATION
- 306 -
Item Description
TN The task number of the task in which the error occurred.
PC The content of the program counter.
SR The content of the status register.
PR The content of the procedure register, which is used in calling a subroutine and stores the return address to
the calling routine.
SP The content of the stack pointer -- the register R15 is used as the stack pointer.
GBR The content of the global base register, which stores base addresses to be used in GBR-indirect addressing
with displacement and in indexed GBR-indirect addressing.
MACH The content of the MAC register high, which saves the accumulated value of a MAC (Multiply and
Accumulate) instruction or the result of a MAC or a MUL instruction. When the result of a MAC
operation is a 64-bit value, this register contains the upper 32-bit value.
MACL The content of the MAC register low, which serves the same purpose as MACH. When the result of a
MAC operation is a 64-bit value, this register contains the lower 32-bit value. When the result of a MAC
operation is a 32-bit value, it contains the entire 32-bit value.
Rxx The content of the general register numbered xx.
FPSCR The content of the floating-point status/control register.
FPUL The content of the floating-point communication register, a register via which data transfer is done
between general and floating-point registers.
FRxx The content of the 32-bit floating-point register numbered xx. When FPSCR.PR (19th bit of the bits 31
thru 0) = 0, these registers contain values of FPRxx_BANK0. When FPSCR.PR = 1, they contain values
of FPRxx_BANK1.
XFxx The content of the 32-bit floating-point extension register numbered xx. When FPSCR.PR (19th bit of
the bits 31 thru 0) = 0, these registers contain values of FPRxx_BANK1. When FPSCR.PR = 1, they
contain values of FPRxx_BANK0.
DRxx The content of the 64-bit floating-point register numbered xx. When FPSCR.PR (19th bit of the bits 31
thru 0) = 0, these registers contain values of FPRxx_BANK0. When FPSCR.PR = 1, they contain values
of FPRxx_BANK1.
XDxx The content of the 64-bit floating-point register numbered xx. When FPSCR.PR (19th bit of the bits 31
thru 0) = 0, these registers contain values of FPRxx_BANK1. When FPSCR.PR = 1, they contain values
of FPRxx_BANK0.
BARA
0 31
BARA
Bit no. Bit name Read-in value Meaning
0 to 31 BARA Specified value Is the logical address used as a break
condition for channel A.
BAMRA
0 27 28 29 30 31
0 0 BAMA2 BASMA BAMA1 BAMA0
Bit no. Bit name Read-in value Meaning
0 to 27 － Always 0. －
29 BASMA 0: Included.
1: Not included.
Indicates whether or not all bits in BASRA
are included in the break condition.
28, 30,
31
BAMA2,
BAMA1,
BAMA0
Specified value Used in combination, specify the bits to be
included in the break address (break
condition) for channel A:
0, 0, 0: Do not mask in or out all the bits of
BARA.
0, 0, 1: Mask in or out only the low-order 10
bits of BARA.
0, 1, 0: Mask in or out only the low-order 12
bits of BARA.
0, 1, 1: Mask in or out all the bits of BARA.
1, 0, 0: Mask in or out only the low-order 16
bits of BARA.
1, 0, 1: Mask in or out only the low-order 20
bits of BARA.
1, 1, 0: Reserved (may not be used).
1, 1, 1: Reserved (may not be used).
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