User's Manual
Table Of Contents
- Contents
- Figures
- Tables
- Document history
- Introduction
- Product concept
- GSM application interface
- GSM/GPRS operating modes
- Power supply
- Power up / down scenarios
- Automatic GPRS Multislot Class change
- Charging control of the GSM part
- Power saving
- Summary of state transitions (except SLEEP mode)
- RTC backup for GSM part of XT55/56
- Serial interfaces of the XT55/56 GSM part
- Audio interfaces
- SIM interface
- Control signals
- GPS application interface
- GSM and GPS antenna interfaces
- Electrical, reliability and radio characteristics
- Mechanics
- Reference approval
- Example applications
- List of parts and accessories
XT55/56 Hardware Interface Description
Confidential / Released
s
XT55/56_hd_v02.06a Page 60 of 125 17.12.2004
Note: Before starting the data transfer the clock GSM_SCLK should be available for at
least three cycles.
After the transfer of the LSB0 the clock GSM_SCLK should be still available for at
least three cycles.
GSM_SLCK
GSM_RFSDAI
GSM_RXDDAI
(input)
Internal
signal
(input)
(input)
Flag
T = 100ns to 5,000 ns
minimum possible distance = 25 bit periods
= T
= T
= T
MSB
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit
10
Bit
9
Bit
8
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
LSB
0
MSB
15
automatic reset after
reading to DAIRD
interrupt on INTO
after 3 DSP cycles
< 1.5 SCLK
cycles
< 1 DSP cycle
Figure 17: DAI timing on transmit path
GSM_SLCK
GSM_TFSDAI
GSM_TXDDAI
(input)
Internal
signal
(output)
Flag
T = 100ns to 5,000 ns
minimum possible distance = 25 bit periods
= T
= T
= T
MSB
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit
10
Bit
9
Bit
8
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
LSB
0
MSB
15
interrupt on INTO
after 3 DSP cycles
<1 DSP
cycles
(output)
<2 DSP
cycles
<3 SCLK
cycles
automatic reset after
writing to DAITD
Figure 18: DAI timing on receive path