FUJITSU SEMICONDUCTOR CM71-xxxxx-1E CONTROLLER MANUAL FR60 32-BIT MICROCONTROLLER MB91460 Series User’s Manual Version 1.
FUJITSU LIMITED
FR60 32-BIT MICROCONTROLLER MB91460 Series User’s Manual
• • • • • • The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information.
TOC Chapter 1 1. 2. 3. 4. How to Handle the Device ..................................................................................................... Instruction for Users............................................................................................................... Caution: debug-related matters ............................................................................................. How to Use This Document ..........................................................................
. 7. 8. 9. EIT Vector Table................................................................................................................ Multiple EIT Processing ..................................................................................................... Operation ........................................................................................................................... Caution ......................................................................................................
8. Explanations of Registers .................................................................................................. 169 Chapter 12 Instruction Cache............................................................................ 179 1. 2. 3. 4. 5. General description............................................................................................................ Main body structure .........................................................................................................
3. 4. 5. 6. 7. 8. Configuration ..................................................................................................................... Registers............................................................................................................................ Operation ........................................................................................................................... Settings.....................................................................................
4. 5. 6. 7. 8. Register ............................................................................................................................. Operation ........................................................................................................................... Setting................................................................................................................................ Q & A .....................................................................................
4. 5. 6. 7. 8. Register ............................................................................................................................. Operation ........................................................................................................................... Setting................................................................................................................................ Q & A .....................................................................................
Chapter 34 CAN Controller ................................................................................ 691 1. 2. 3. 4. Overview............................................................................................................................ Register Description .......................................................................................................... Functional Description .......................................................................................................
2. 3. 4. 5. 6. 7. 8. Features............................................................................................................................. Configuration ..................................................................................................................... Registers............................................................................................................................ Operation ................................................................................
4. 5. 6. 7. 8. Registers............................................................................................................................ Operation ........................................................................................................................... Setting................................................................................................................................ Q & A ......................................................................................
6. Application Note................................................................................................................. 973 Chapter 51 Low Voltage Reset/Interrupt .......................................................... 975 1. 2. 3. Overview............................................................................................................................ 975 Features....................................................................................................................
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Chapter 1 Introduction 1.How to Handle the Device Chapter 1 Introduction 1. How to Handle the Device ■ Device Handling Instructions This chapter describes latch-up prevention and pin termination. ● To set latch-up prevention Latch up may occur on CMOS ICs when the applied voltage for input terminals or output terminals is higher than VCC or lower than VSS, or a voltage higher than the maximum rating voltage is applied between VCC and VSS.
Chapter 1 Introduction 1.How to Handle the Device ● Caution: during the PLL clock operation Even if oscillator is disconnected or input is stopped while selecting PLL clock, self-excited oscillation circuit in the PLL may continue running at self-running frequency. This self-running operation is not covered by guarantee. ● For more specification about operating voltage, see the latest data sheet.
Chapter 1 Introduction 2.Instruction for Users 2. Instruction for Users ■ Clock Controls By inputting “L” to INIT, ensure clock oscillation stabilization time. ■ Switching of dual-purpose port Use PFR (Port function register) to switch between PORT and dual-purpose port. ■ Low-power-consumption mode • For standby mode, enable synchronous standby (TBCR.SYNCS=“1”) and then use the following sequences.
Chapter 1 Introduction 2.Instruction for Users ■ Caution: PS register Because some commands previously proceed PS register, interrupt processing routine may be broken during the use of debugger or displayed data on PS flag may be updated due to the following excecptional operations ((1) and (2)). In each case, it is designed to correctly re-proceed operations after the return, the operation before and after EIT is carried out in accordance with the specification.
Chapter 1 Introduction 2.Instruction for Users ■ Caution: writing to registers which include a status flag Writing to a register including a status flag (in particular, interrupt request flag) in order to control the function, note that you should not clear status flag unintentionally. That is, take care not to clear the flag for status bit and make control bit to be the expected value during the writing.
Chapter 1 Introduction 3.Caution: debug-related matters 3. Caution: debug-related matters ■ Stepwise execution of RETI command Under the circumstances where interruption is often generated when carrying out stepwise execution, only relevant interrupt processing routine is repeatedly executed after the stepwise execution of RETI. Therefore, main routine or low-level interruption program will not be executed. To avoid this problem, do not proceed stepwise execution of RETI command.
Chapter 1 Introduction 4.How to Use This Document 4. How to Use This Document ■ Main terminology: This table shows main terminology used for FR60. Term I-bus D-bus F-bus R-bus Meaning 32-bit-wide bus for internal instruction. Since FR60 series employ internal Harvard architecture, instruction and data are independent bus. For I-bus, Harverd/Prinston-bus-converter is connected. Internal 32-bit-wide data bus.
Chapter 1 Introduction 4.How to Use This Document ■ Access size and address position Offset Address Register name Write-only Read-only Address offset value/Register name Block Up/down counter 0, 1 Read/write Initial value Byte access, Half-word access, and Word access are allowed. There are three kinds of accesses such as Byte access, Half-word access and Word access. However, note that some registers have restricted access. For more information, see “3.2. I/O Map (Page No.
Chapter 1 Introduction 4.How to Use This Document ■ About access size and bit position Register name Register mark Target peripheral device Address Access size Bit position (1) Counter control register (Higher byte) This is the register (higher byte) which controls up/down counter operation.
Chapter 1 Introduction 4.How to Use This Document ■ Meaning of Bit Attribute Symbols R W RM : Readable : Writable : Reading operation during read/modify/write operation. “/” (Slash) R/W: Readable and writable. (The read value is the value written.) “,” (comma) R,W: Values are different between read and write. (The read value is different from the value written.) R0 : The read value is “0”. R1 : The read value is “1”. W0 : Always write “0”. W1 : Always write “1”.
Chapter 2 MB91460 Rev.A/Rev.B Overview 1.Overview Chapter 2 MB91460 Rev.A/Rev.B Overview 1. Overview MB91460 is a series of standard microcontrollers containing a range of I/O peripherals and bus control functions. MB91460 features a 32-bit RISC CPU (FR60 series) core and is suitable for embedded control applications requiring high-performance and high-speed CPU processing.
Chapter 2 MB91460 Rev.A/Rev.B Overview 2.Features • 4 words (16 bytes) per set • Variable capacity (4/2/1 kB) • Lock function enabling programs to be resident • Available as instruction RAM requiring no wait state when not used as an instruction cache • Direct mapped I-cache • Up to 16 kByte integrated • Variable capacity (16/8/4/2/1 kB) • Lock function enabling programs to be resident 2.
Chapter 2 MB91460 Rev.A/Rev.B Overview 2.Features • • • • • • 3 types of transfer sources (external pins/internal peripherals/and software) Up to 128 selectable internal transfer sources Addressing mode: Specifying up to 32-bit addresses (Increment/decrement/fixed) Transfer mode (Demand transfer/burst transfer/step transfer/block transfer) Fly-by transfer supported (between external I/O and memory) Transferred data size selectable from among 8, 16, and 32 bits 2.9 Infotainment extension (MB91460 Rev.
Chapter 2 MB91460 Rev.A/Rev.B Overview 2.Features 2.
Chapter 2 MB91460 Rev.A/Rev.B Overview 2.
Chapter 2 MB91460 Rev.A/Rev.B Overview 2.
Chapter 2 MB91460 Rev.A/Rev.B Overview 2.Features the range of 1 to 1.
Chapter 2 MB91460 Rev.A/Rev.B Overview 2.Features • Prescaler value for 32 kHz is 001FFFH • Clock monitor (clock output function): 1 channel • Clock supervisor • Monitors external 32kHz and 4MHz for fails (e.g.
Chapter 2 MB91460 Rev.A/Rev.B Overview 3.MB91460 Series Product Lineup 3. MB91460 Series Product Lineup Feature MB91V460 Rev.A MB91V460 Rev.B MB91F467DA Core frequency 80 MHz 100 MHz 100 MHz Resource frequency 40 MHz 50 MHz 50 MHz Technology 0.35um 0.18um 0.18um yes yes yes Watchdog Watchdog (RC osc.
Chapter 2 MB91460 Rev.A/Rev.B Overview 3.MB91460 Series Product Lineup Feature MB91V460 Rev.A MB91V460 Rev.
max. 8MB SRAM/ Flash max.
Chapter 2 MB91460 Rev.A/Rev.B Overview 4.
Chapter 3 MB91460 Series Basic Information 1.Memory Map Chapter 3 MB91460 Series Basic Information This chapter describes MB91460 series basic information including Memory- and I/O map, interrupt vector table, pin function list, circuit type and pin state table for each device mode. 1.
Chapter 3 MB91460 Series Basic Information 2.I/O Map 2. I/O Map This section shows the association between memory space and each register of peripheral resources.
Chapter 3 MB91460 Series Basic Information 2.
Chapter 3 MB91460 Series Basic Information 2.I/O Map Register Address 000048H 26 Block +0 +1 +2 +3 SCR01 [R/W,W] 00000000 SMR01 [R/W,W] 00000000 SSR01 [R/W,R] 00001000 RDR01/TDR01 [R/W] 00000000 00004CH ESCR01 [R/W] 00000X00 ECCR01 [R/W,R,W] 000000XX 000050H SCR02 [R/W,W] 00000000 SMR02 [R/W,W] 00000000 000054H ESCR02 [R/W] 00000X00 ECCR02 [R/W,R,W] 000000XX 000058H SCR03 [R/W,W] 00000000 SMR03 [R/W,W] 00000000 USART (LIN) 1 res.
Chapter 3 MB91460 Series Basic Information 2.
Chapter 3 MB91460 Series Basic Information 2.I/O Map Register Address Block +0 +1 +2 +3 0000D0H IBCR0 [R/W] 00000000 IBSR0 [R] 00000000 ITBAH0 [R/W] - - - - - - 00 ITBAL0 [R/W] 00000000 0000D4H ITMKH0 [R/W] 00 - - - - 11 ITMKL0 [R/W] 11111111 ISMK0 [R/W] 01111111 ISBA0 [R/W] - 0000000 0000D8H res. IDAR0 [R/W] 00000000 ICCR0 [R/W] - 0011111 res.
Chapter 3 MB91460 Series Basic Information 2.
Chapter 3 MB91460 Series Basic Information 2.I/O Map Register Address 000170H Block +0 +1 +2 +3 P0TMCSRH [R/W] - 0 - 000 - 0 P0TMCSRL [R/W] - - - 00000 P1TMCSRH [R/W] - 0 - 000 - 0 P1TMCSRL [R/W] - - - 00000 000174H P0TMRLR [W] XXXXXXXX XXXXXXXX P0TMR [R] XXXXXXXX XXXXXXXX 000178H P1TMRLR [W] XXXXXXXX XXXXXXXX P1TMR [R] XXXXXXXX XXXXXXXX 00017CH ICS01 [R/W] 00000000 ICS23 [R/W] 00000000 res.
Chapter 3 MB91460 Series Basic Information 2.
Chapter 3 MB91460 Series Basic Information 2.I/O Map Register Address Block +0 0001F8H +1 TCDT2 [R/W] XXXXXXXX XXXXXXXX +2 +3 res. TCCS2 [R/W] 00000000 Free Running Timer 2 (OCU 0-1) 0001FCH TCDT3 [R/W] XXXXXXXX XXXXXXXX res.
Chapter 3 MB91460 Series Basic Information 2.
Chapter 3 MB91460 Series Basic Information 2.I/O Map Register Address 0002B0H Block +0 +1 +2 +3 SCR14 [R/W,W] 00000000 SMR14 [R/W,W] 00000000 SSR14 [R/W,R] 00001000 RDR14/TDR14 [R/W] 00000000 0002B4H ESCR14 [R/W] 00000X00 ECCR14 [R/W,R,W] 000000XX 0002B8H SCR15 [R/W,W] 00000000 SMR15 [R/W,W] 00000000 res.
Chapter 3 MB91460 Series Basic Information 2.I/O Map Register Address Block +0 0002F4H +1 TCDT5 [R/W] XXXXXXXX XXXXXXXX +2 +3 res. TCCS5 [R/W] 00000000 Free Running Timer 5 (ICU 6-7) 0002F8H TCDT6 [R/W] XXXXXXXX XXXXXXXX res. TCCS6 [R/W] 00000000 Free Running Timer 6 (OCU 4-5) 0002FCH TCDT7 [R/W] XXXXXXXX XXXXXXXX res.
Chapter 3 MB91460 Series Basic Information 2.I/O Map Register Address Block +0 +1 000340H PTMR14 [R] 11111111 11111111 000344H PDUT14 [W] XXXXXXXX XXXXXXXX 000348H PTMR15 [R] 11111111 11111111 00034CH PDUT15 [W] XXXXXXXX XXXXXXXX +2 +3 PCSR14 [W] XXXXXXXX XXXXXXXX PPG 14 PCNH14 [R/W] 0000000 - PCNL14 [R/W] 000000 - 0 PCSR15 [W] XXXXXXXX XXXXXXXX PPG 15 000350H 00035CH PCNL15 [R/W] 000000 - 0 reserved DACR [R/W] - - - - - 000 000360H res.
Chapter 3 MB91460 Series Basic Information 2.
Chapter 3 MB91460 Series Basic Information 2.
Chapter 3 MB91460 Series Basic Information 2.I/O Map Register Address Block +0 +1 +2 +3 00048CH PLLDIVM [R/W] - - - - 0000 PLLDIVN [R/W] - - 000000 PLLDIVG [R/W] - - - - 0000 PLLMULG [W] 00000000 000490H PLLCTRL [R/W] - - - - 0000 res. res. res. 000494H OSCC1 [R/W] - - - - - 010 OSCS1 [R/W] 00001111 OSCC2 [R/W] - - - - - 010 OSCS2 [R/W] 00001111 Main/Sub Oscillator Control (do not use) 000498H PORTEN [R/W] - - - - - - 00 res. res. res. Port Input Enable Control 0004A0H res.
Chapter 3 MB91460 Series Basic Information 2.I/O Map Register Address +1 +2 +3 0004D0H C340R [R/W] -------0 res. EISSRH [R/W] 00000000 EISSRL [R/W] 00000000 0004D4H SHDE [R/W] 0------- res. EXTE [R/W] 00000000 EXTF [R/W] 00000000 res. res.
Chapter 3 MB91460 Series Basic Information 2.
Chapter 3 MB91460 Series Basic Information 2.I/O Map Register Address 0007FCH Block +0 +1 +2 +3 res. MODR [W] XXXXXXXX res. res. 000800H 000BFCH 000C00H reserved TVCTW [W] XXXXXXXX TVCTR [R] - - XXXXXX 000C04H 000CFCH 42 DSU4 / RTM res.
Chapter 3 MB91460 Series Basic Information 2.
Chapter 3 MB91460 Series Basic Information 2.
Chapter 3 MB91460 Series Basic Information 2.
Chapter 3 MB91460 Series Basic Information 2.
Chapter 3 MB91460 Series Basic Information 2.
Chapter 3 MB91460 Series Basic Information 2.
Chapter 3 MB91460 Series Basic Information 2.
Chapter 3 MB91460 Series Basic Information 2.I/O Map Register Address Block +0 +1 +3 00C040H IF2CREQ0 [R/W] 00000000 00000001 IF2CMSK0 [R/W] 00000000 00000000 00C044H IF2MSK20 [R/W] 11111111 11111111 IF2MSK10 [R/W] 11111111 11111111 00C048H IF2ARB20 [R/W] 00000000 00000000 IF2ARB10 [R/W] 00000000 00000000 00C04CH IF2MCTR0 [R/W] 00000000 00000000 res.
Chapter 3 MB91460 Series Basic Information 2.
Chapter 3 MB91460 Series Basic Information 2.
Chapter 3 MB91460 Series Basic Information 2.I/O Map Register Address Block +0 +1 +2 +3 00C140H IF2CREQ1 [R/W] 00000000 00000001 IF2CMSK1 [R/W] 00000000 00000000 00C144H IF2MSK21 [R/W] 11111111 11111111 IF2MSK11 [R/W] 11111111 11111111 00C148H IF2ARB21 [R/W] 00000000 00000000 IF2ARB11 [R/W] 00000000 00000000 00C14CH IF2MCTR1 [R/W] 00000000 00000000 res.
Chapter 3 MB91460 Series Basic Information 2.
Chapter 3 MB91460 Series Basic Information 2.
Chapter 3 MB91460 Series Basic Information 2.I/O Map Register Address Block +0 +1 +3 00C240H IF2CREQ2 [R/W] 00000000 00000001 IF2CMSK2 [R/W] 00000000 00000000 00C244H IF2MSK22 [R/W] 11111111 11111111 IF2MSK12 [R/W] 11111111 11111111 00C248H IF2ARB22 [R/W] 00000000 00000000 IF2ARB12 [R/W] 00000000 00000000 00C24CH IF2MCTR2 [R/W] 00000000 00000000 res.
Chapter 3 MB91460 Series Basic Information 2.
Chapter 3 MB91460 Series Basic Information 2.
Chapter 3 MB91460 Series Basic Information 2.I/O Map Register Address Block +0 +1 +2 +3 00C340H IF2CREQ3 [R/W] 00000000 00000001 IF2CMSK3 [R/W] 00000000 00000000 00C344H IF2MSK23 [R/W] 11111111 11111111 IF2MSK13 [R/W] 11111111 11111111 00C348H IF2ARB23 [R/W] 00000000 00000000 IF2ARB13 [R/W] 00000000 00000000 00C34CH IF2MCTR3 [R/W] 00000000 00000000 res.
Chapter 3 MB91460 Series Basic Information 2.
Chapter 3 MB91460 Series Basic Information 2.
Chapter 3 MB91460 Series Basic Information 2.I/O Map Register Address Block +0 +1 +3 00C440H IF2CREQ4 [R/W] 00000000 00000001 IF2CMSK4 [R/W] 00000000 00000000 00C444H IF2MSK24 [R/W] 11111111 11111111 IF2MSK14 [R/W] 11111111 11111111 00C448H IF2ARB24 [R/W] 00000000 00000000 IF2ARB14 [R/W] 00000000 00000000 00C44CH IF2MCTR4 [R/W] 00000000 00000000 res.
Chapter 3 MB91460 Series Basic Information 2.
Chapter 3 MB91460 Series Basic Information 2.
Chapter 3 MB91460 Series Basic Information 2.I/O Map Register Address Block +0 +1 +2 +3 00C540H IF2CREQ5 [R/W] 00000000 00000001 IF2CMSK5 [R/W] 00000000 00000000 00C544H IF2MSK25 [R/W] 11111111 11111111 IF2MSK15 [R/W] 11111111 11111111 00C548H IF2ARB25 [R/W] 00000000 00000000 IF2ARB15 [R/W] 00000000 00000000 00C54CH IF2MCTR5 [R/W] 00000000 00000000 res.
Chapter 3 MB91460 Series Basic Information 2.
Chapter 3 MB91460 Series Basic Information 2.
Chapter 3 MB91460 Series Basic Information 2.
Chapter 3 MB91460 Series Basic Information 2.
Chapter 3 MB91460 Series Basic Information 2.
Chapter 3 MB91460 Series Basic Information 2.
Chapter 3 MB91460 Series Basic Information 2.I/O Map Register Address Block +0 +1 +2 200000H 27FFFCH ROMS10 area (512kB) 280000H 2FFFFCH ROMS11 area (512kB) 300000H 37FFFCH ROMS12 area (512kB) 380000H 3FFFFCH ROMS13 area (512kB) 400000H 47FFFCH ROMS14 area (512kB) 480000H 4FFFFCH ROMS15 area (512kB) +3 Write operations to address 0FFFF8H and 0FFFFCH are not possible. When reading these addresses, the values shown above will be read.
Chapter 3 MB91460 Series Basic Information 3.Interrupt Vector Table 3. Interrupt Vector Table This section shows the allocation of interrupt and interrupt vector/interrupt register.
Chapter 3 MB91460 Series Basic Information 3.
Chapter 3 MB91460 Series Basic Information 3.
Chapter 3 MB91460 Series Basic Information 3.
Chapter 3 MB91460 Series Basic Information 3.Interrupt Vector Table Prog. Pulse Gen. 14 126 7E ICR55 Prog. Pulse Gen.
Chapter 3 MB91460 Series Basic Information 4.Package 4.
Chapter 3 MB91460 Series Basic Information 5.Pin Assignment Diagram 5.
Chapter 3 MB91460 Series Basic Information 6.Pin Definitions 80 Pad JEDEC Pin (INNER) 6.
Chapter 3 MB91460 Series Basic Information 6.
Chapter 3 MB91460 Series Basic Information 6.
Chapter 3 MB91460 Series Basic Information 6.
Chapter 3 MB91460 Series Basic Information 6.
Chapter 3 MB91460 Series Basic Information 6.
Chapter 3 MB91460 Series Basic Information 6.
Chapter 3 MB91460 Series Basic Information 6.
Chapter 3 MB91460 Series Basic Information 6.
Chapter 3 MB91460 Series Basic Information 6.
Chapter 3 MB91460 Series Basic Information 6.
Chapter 3 MB91460 Series Basic Information 6.Pin Definitions AK37 316 263 FLASH_FRSTX - - - - TE10_0 - - no Tool 4mA 0.0 637 531 VDD5 - - - - TS02_0 - - - VDD 5V - 0.0 615 513 VDD5 - - - - TS02_0 - - - VDD 5V - 0.0 591 491 VDD5 - - - - TS02_0 - - - VDD 5V - 0.
Chapter 3 MB91460 Series Basic Information 6.Pin Definitions 92 0.
Chapter 3 MB91460 Series Basic Information 6.
Chapter 3 MB91460 Series Basic Information 7.I/O Circuit Type 7. I/O Circuit Type The table below describes the circuit types which are used on the evaluation device MB91V460 Rev.A. Please refer to the datasheets for information about the circuit type of each pin used on the flash devices. 94 Type Pull Up/ Pull Down CMOS/ CMOS Hyst.
Chapter 3 MB91460 Series Basic Information 7.
Chapter 3 MB91460 Series Basic Information 8.Pin State Table 8. Pin State Table Explanation of the meaning of words and phrases used in the pin state table according to the chosen mode. • Input enable: It is possible to input a signal to the device. • Input fixed: To prevent leakage by floating inputs, the input level is fixed to "0" internally. • Hi-Z: The pin is put in a high impedance state. • State hold: The state (input/output) of the pin immediately before changing the state is maintained.
Chapter 3 MB91460 Series Basic Information 8.
Chapter 3 MB91460 Series Basic Information 8.
Chapter 3 MB91460 Series Basic Information 8.
Chapter 3 MB91460 Series Basic Information 8.
Chapter 3 MB91460 Series Basic Information 8.Pin State Table A13 58 47 P22_7 - SCL1 - - STOP: Input enabled if PFR is set (for Ext.INT) D14 57 46 P22_6 - SDA1 - INT15 C14 56 45 P22_5 - SCL0 - - STOP: Input enabled if PFR is set (for Ext.INT) D13 55 44 P22_4 - SDA0 - C13 54 42 P22_3 - TX5 - Hi-Z, Output Hi-Z, INT14 Output Input Input State hold enabled enabled - Output: HiZ, State hold, Output: Input fixed Input fixed STOP: Input enabled if PFR is set (for Ext.
Chapter 3 MB91460 Series Basic Information 8.
Chapter 3 MB91460 Series Basic Information 8.
Chapter 3 MB91460 Series Basic Information 8.
Chapter 4 CPU Architecture 1.Overview Chapter 4 CPU Architecture This chapter describes the architecture of FR60 family CPU. 1. Overview The CPUs of the FR60 family series employ RISC architecture and advanced function instructions for embedded application. CPU of FR60 family employs Harvard architecture whose instruction bus and data bus are independent. “32bit/16-bit bus converter” realizes the interface between CPU and peripheral functions.
Chapter 4 CPU Architecture 2.Features 2. Features ■ Features of internal architecture • • • • • • • • • • • • • 106 RISC architecture Base instruction: 1 instruction/1 cycle 32-bit architecture General-purpose register: 32-bit x 16 4GB of linear memory space Equipped with multiplier.
Chapter 4 CPU Architecture 3.CPU 3. CPU The CPU realizes the compact implementation of a 32-bit RISC FR architecture. It employs a 5-stage instruction pipeline method to execute 1 instruction per 1 cycle. This pipeline consists of the following stages. • • • • • Instruction fetch (IF): outputs instruction address to fetch instruction. Instruction decode (ID): decodes fetched instruction and reads register. Execution (EX): executes operation.
Chapter 4 CPU Architecture 6.Instruction Overview 6. Instruction Overview The FR60 family supports logic operation, bit operation and direct addressing instruction optimized for embedded application as well as general RISC instruction system. Instruction-set list is shown in the appendix. Since each instruction is 16-bit length (some instruction is 32-bit or 48-bit length), it enables you to generate compact program code. Instruction sets are grouped into the following a through f function groups.
Chapter 4 CPU Architecture 7.Data Structure 7. Data Structure FR60 has two data allocations as follows. ■ Bit Ordering FR60 uses little endian as bit ordering. Figure 7-1 Bit Structure of Bit Ordering bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LSB MSB ■ Byte Ordering FR60 uses big endian as byte ordering.
Chapter 4 CPU Architecture 8.Word Alignment 8. Word Alignment Since instructions and data are accessed by byte, allocated addresses vary by instruction length or data width. ■ Program Access FR60 program is required to be allocated in addresses multiplied by 2. PC's bit0 is cleared for instruction execution upon the PC update. (PC bit 0 may be set when odd address is specified for branching address, however, it is invalid.
Chapter 4 CPU Architecture 9.Addressing 9. Addressing Address space is 32-bit linear. ■ Map Figure 9-1 Map 0000 0000H Byte data 0000 0100H Half-word data Direct addressing area 0000 0200H Word data 0000 0400H 000F FC00H Vector table 000F FFFFH FFFF FFFFH FR60’s logical address space is 4GB (232 addresses), CPU accesses the data linearly. ■ Direct Addressing Area The following areas are used for I/O.
Chapter 4 CPU Architecture 9.
Chapter 5 CPU Registers 1.General-purpose Registers Chapter 5 CPU Registers 1. General-purpose Registers Registers R0 through R15 are general-purpose registers. These registers are used for accumulator and memory access pointers on various operations. Figure 1-1 General-purpose Registers 32 bit [Initial value] R0 R1 ... ... ... ... R12 R13 R14 R15 AC FP SP XXXX XXXXH ... ... ... ... XXXX XXXXH 0000 0000H Of 16 registers, the following registers are reserved for special application.
Chapter 5 CPU Registers 2.Dedicated Registers 2.1 PC: Program Counter Program Counter (PC) consists of 32 bits. Figure 2-2 Bit Structure of Program Counter (PC) [Initial value] 0 31 PC XXXXXXXXH Program counter (PC) indicates active instruction address. Upon the execution of the instruction, program counter (PC)’s bit 0 is cleared. 2.2 PS: Program Status Register Program status register (PS) is the register to hold program status which consists of three parts including ILM, SCR and CCR.
Chapter 5 CPU Registers 2.Dedicated Registers This bit becomes “0” by reset. • [Bit 3] N: Negative flag This bit indicates the sign when operation results is deemed as integer represented by two’s-complement numbers. N 0 1 Description It indicates that operation result is positive value. It indicates that operation result is negative value. • [Bit 2] Z: Zero flag It indicates whether operation result is 0 or not. Z 0 1 Description It indicates that operation result is other than 0.
Chapter 5 CPU Registers 2.Dedicated Registers program. ■ ILM: Interrupt Level Mask Register Figure 2-6 Register Structure of Interrupt Level Mask Register (ILM) 20 19 18 17 16 ILM4 ILM3 ILM2 ILM1 ILM0 • • • • [Initial value] 01111 B This is the register to hold interrupt level mask value. This bit uses the value held in ILM as level mask. ILM indicates corresponding interrupt level from interrupt requests entered in CPU.
Chapter 5 CPU Registers 2.Dedicated Registers ■ Caution: PS Register Since some instructions have already processed PS register in advance, the following exception operations may break interrupt processing routine during the use of debugger, or update PS flag data. In either cases, after returning from EIT, it is designed to execute the correct process so that operations before and after EIT will be processed in accordance with specification.
Chapter 5 CPU Registers 2.Dedicated Registers 2.3 TBR: Table-base Register Table-base register (TBR) consists of 32 bits. Figure 2-7 Bit Structure of Table-base Register (TBR) 31 0 TBR [Initial value] 000FFC00H Table-base register holds head address of vector table used for EIT processes. Vector address is made by adding offset value specified in TBR and EIT each. 2.4 RP: Return Pointer Return pointer (RP: Return Pointer) consists of 32 bits.
Chapter 5 CPU Registers 2.Dedicated Registers 2.6 USP: User Stack Pointer User Stack Pointer (USP) consists of 32 bits. Figure 2-10 Bit Structure of User Stack Pointer (USP) 31 0 USP [Initial value] 00000000H When S flag is “1”, this pointer works as R15. You can explicitly specify USP. You can not use it for RETI instruction. This pointer saves and returns PC and PS values at the position where system stack pointer (SSP) indicates.
Chapter 5 CPU Registers 2.Dedicated Registers 2.7 MDH, MDL: Multiply & Divide Register Multiply & Divide register (MDH/MDL) consists of 32 bits. Figure 2-12 Bit Structure of Multiply & Divide Register (MDH/MDL) 31 0 MDH MDL This is the register for multiplication and division and consists of 32 bits. Initial value by reset is indeterminate.
Chapter 6 EIT: Exceptions, Interrupts and Traps 1.Overview Chapter 6 EIT: Exceptions, Interrupts and Traps 1. Overview EIT means that some events interrupt current program to execute other programs. EIT stands for Exception, Interrupt and Trap. • Exception is the event which is generated in association with active context. It is returned to the instruction which triggered the exception. • Interrupt is the event which is generated regardless of active context. Interrupt is triggered by hardware.
Chapter 6 EIT: Exceptions, Interrupts and Traps 5.EIT Interrupt Level 5. EIT Interrupt Level Interrupt level is between 0 and 31, and controlled with 5 bits. Table 5-1 Interrupt Level of EIT Binary 00000 ... ... 00011 Level Decimal 0 ... ... 3 Description Remarks (Reserved for system) ... ... (Reserved for system) 00100 4 INTE instruction Step trace trap If original value of ILM is between 16 and 31, these values are not configurable to ILM by program. 00101 ... ... 01110 01111 10000 10001 ... ...
Chapter 6 EIT: Exceptions, Interrupts and Traps 7.Multiple EIT Processing 7. Multiple EIT Processing If multiple EITs are generated at the same time, CPU repeats the operation which selects one of the EIT to accept, and then executes EIT sequence, and detects EIT again. If there is no EIT to accept upon detecting EIT, CPU executes instruction of the last accepted EIT handler.
Chapter 6 EIT: Exceptions, Interrupts and Traps 7.
Chapter 6 EIT: Exceptions, Interrupts and Traps 8.Operation 8. Operation In the following sections, note that source “PC” means instruction address which detected each EIT trigger. Similarly, “address of next instruction” means the following addresses based on the instruction which detected the EIT. • When LDI is 32: PC+6 • When LDI is 20, and it is COPOP, COPLD, COPST or COPSV: PC+4 • For other instructions: PC+2 8.
Chapter 6 EIT: Exceptions, Interrupts and Traps 8.Operation 8.2 Operation of INT Instruction INT No. u8 instruction is operated as follows. Branches to interrupt handler of vector specified in u8. ■ Operation 1. 2. 3. 4. 5. 6. The contents of the program status (PS) are saved to the system stack. The address of the next instruction is saved to the system stack. The value of the system stack pointer (SSP) is reduced by 8.
Chapter 6 EIT: Exceptions, Interrupts and Traps 8.Operation 8.4 Operation of Step Trace Trap If you set T flag at SCR within PS and enable step trace trap function, step trace trap is generated with each executing instruction. ■ Condition for detecting step trace trap T flag = 1 Instructions are other than delayed branch command. During the execution of instructions other than INTE instructions or step trace trap process routines.
Chapter 6 EIT: Exceptions, Interrupts and Traps 9.Caution 8.6 Coprocessor Absent Trap If you execute coprocessor instruction for unmounted coprocessor, coprocessor absent trap is generated. ■ Operation 1. 2. 3. 4. 5. The contents of the program status (PS) are saved to the system stack. The address of the instruction that caused the undefined instruction exception is saved to the system stack. The value of the system stack pointer (SSP) is reduced by 8.
Chapter 7 Branch Instruction 1.Branch Instruction with Delay Slot Chapter 7 Branch Instruction FR60 can instruct the operation with and without delay slot for branch instruction. 1.
Chapter 7 Branch Instruction 3.Actual Example (with Delay Slot) 3. Actual Example (with Delay Slot) 3.1 JMP:D @Ri / CALL:D @Ri Instruction Ri referred in JMP:D @Ri / CALL:D @Ri instruction remains intact even if instructions within delay slot update Ri. • Example LDI:32 JMP:D LDI:8 ... #Label, @R0 #0, R0 ; Branches to Label. ; Not affect any branched address. R0 3.2 RET:D Instruction RP referred in RET:D instruction remains intact even if instructions within delay slot update RP. • Example RET:D MOV ..
Chapter 7 Branch Instruction 4.Restrictions on Branch Instruction with Delay Slot 4. Restrictions on Branch Instruction with Delay Slot 4.1 Available Instructions for Delay Slot Instructions which meet the following requirements can only be executed in delay slot. • 1-cycle instruction • Non-branch instruction • Instruction which does not affect any operation even if its sequence is changed.
Chapter 7 Branch Instruction 5.Branch Instruction without Delay Slot 5. Branch Instruction without Delay Slot • Branch instruction without delay slot: JMP @Ri CALL label12 CALL @Ri RET BRA label9 BNO label9 BEQ label9 BNE label9 BC label9 BNC label9 BN BP BV label9 BNV label9 BLT label9 BGE label9 BLE label9 BGT label9 BLS label9 BHI label9 label9 label9 6.
Chapter 8 Device State Transition 1.Overview Chapter 8 Device State Transition 1. Overview MB91460 basically has devices state and flow as shown below. For more information, see “3. State Transition Diagram (Page No.134)”. Status transition Power-on Watchdog reset INITX INT-pin input Setting-initialization reset Oscillation-stabilization wait reset Operation-initialization reset Software-reset instruction Run Interrupt request Oscillation-stabilization RUN Stop Interrupt request Sleep 2.
Chapter 8 Device State Transition 3.State Transition Diagram 3. State Transition Diagram This section describes state transition.
Chapter 8 Device State Transition 3.State Transition Diagram 3.1 RUN (Normal Operation) This is the state where program is executed with all clocks and all circuits are enabled. This state has various paths for a state transition. However, if the synchronous reset mode is selected the state transition operations for some requests are different from normal reset mode. For more information, see the chapter of “Chapter 9 Reset (Page No.139)”. 3.
Chapter 8 Device State Transition 3.State Transition Diagram 3.5 Oscillation-stabilization-wait Reset This is the state where the device is stopped. This state is entered upon a setting-initialization reset (INIT). All internal circuits are stopped except for clock generation control parts (timebase counter and device state control parts). All internal clocks are stopped while oscillation circuits and main PLL (if enabled) are operating. • High-impedance control of external pins by STOP is cancelled.
Chapter 8 Device State Transition 3.
Chapter 8 Device State Transition 3.
Chapter 9 Reset 1.Overview Chapter 9 Reset 1. Overview When a reset is triggered, the device halts the program and all hardware operation, and then initializes all states. This state is called a reset. When the reset trigger condition is removed, the device changes from this initialized state to restart the program and hardware operation. The series of steps from removal of the reset condition until operation starts is called the reset cancellation sequence.
Chapter 9 Reset 3.Configuration • A settings initialization reset (INIT) is followed by an operation reset (RST) after the oscillation stabilization time elapses. 3.
Chapter 9 Reset 4.Registers 4. Registers 4.1 RSRR: Reset Cause Register Stores the cause of the previous reset, and sets the period and activation control for the watchdog timer.
Chapter 9 Reset 4.Registers Indicates whether a software reset has been triggered by writing to the software reset bit (STCR.SRST). SRST 0 1 Meaning No RST has been triggered by a software reset. RST has been triggered by a software reset. The software reset occurred flag (SRST) is cleared to “0” after reading. • Bit2: Low voltage reset occurred flag Indicates whether a reset (INIT) was triggered by the low voltage detection. LINIT 0 1 Meaning No INIT has been triggered by the low voltage detection.
Chapter 9 Reset 4.Registers 4.2 STCR: Standby Control Register This register is used for software reset control (changing to standby mode, pin control in stop mode, and clock oscillation halted in stop mode), and specifies the oscillation stabilization wait time. Note: See also “Chapter 10 Standby (Page No.155)”.
Chapter 9 Reset 4.Registers 4.3 MOD: Mode Pins These pins specify the location of the mode vector and reset vector that are read after the MCU is reset. Mode pins MD2 MD1 MD0 0 0 0 0 0 1 Reset vector Access area Mode name Internal ROM mode vector External ROM mode vector Remarks Internal External 4.4 Mode Vector The data written to the mode register (MODR) by the mode vector fetch operation is called the mode data.
Chapter 9 Reset 4.Registers Initial value to load into PC. Address 007FDH MODR 000FFFF8 H Mode Vector 000FFFFC H Reset Vector XXXXXXXX XXXXXXXX XXXXXXXX PC 4.
Chapter 9 Reset 5.INIT Pin Input (INIT: Settings Initialization Reset) 5. INIT Pin Input (INIT: Settings Initialization Reset) 5.1 Trigger The pin is used to trigger a settings initialization reset. A settings initialization reset (INIT) request remains active while the pin remains at the “L” level. Keep the “L” level for the main oscillation stabilisation time. 5.
Chapter 9 Reset 5.INIT Pin Input (INIT: Settings Initialization Reset) 5.6 Reset Cancellation Sequence After the cancellation (removal) of the settings initialization reset (external INITX pin) request the device performs the following operations in the sequence listed. 1. Removal of settings initialization reset (INIT) 2. Set operation reset (RST) state and start internal clock 3. Clear operation reset (RST) state and change to normal operation (RUN) 4. Read mode vector from address 000FFFF8H 5.
Chapter 9 Reset 6.Watchdog Reset (INIT: Settings Initialization Reset) 6. Watchdog Reset (INIT: Settings Initialization Reset) 6.1 Trigger Writing to the watchdog timer control register (RSRR) starts the watchdog timer. Once started, a watchdog reset request is generated unless “A5H” and “5AH” are written to the watchdog reset delay register (WPR) within the time specified by the watchdog period selection bits (RSRR.WT[1:0]). 6.
Chapter 9 Reset 7.Software Reset (RST: Operation Initialization Reset) 7. Software Reset (RST: Operation Initialization Reset) 7.1 Trigger Writing “0” to the software reset bit (STCR.SRST) generates a software reset request. A software reset requests an operation reset (RST). 7.2 Releasing the Reset Request The software reset request is released after the request is received and the operation reset (RST) generated. 7.
Chapter 9 Reset 8.Reset Operation Modes 8. Reset Operation Modes The following two different modes can be used for an operation reset (RST): • Normal (asynchronous) reset mode • Synchronous reset mode Which mode to use is specified by the synchronous reset operation enable bit (TBCR.SYNCR). Pin input resets and watchdog resets always use normal reset mode. For software resets, either normal reset mode or synchronous reset mode can be selected. 8.
Chapter 9 Reset 9.MCU Operation Mode 9. MCU Operation Mode After release of a reset, the MCU starts operation in the mode specified by the mode pins and mode data. Operation mode Bus mode Single chip mode Internal ROM/external bus mode External ROM/external bus mode Access mode 32-bit bus width 16-bit bus width 8-bit bus width 9.1 Bus Modes and Access Modes ■ Bus mode The bus mode controls internal ROM operation and the external access function.
Chapter 9 Reset 10.Caution 10. Caution • INIT pin input Ensure that a settings initialization reset (INIT) is applied to this pin when the power is turned on. Also, after turning on the power, ensure a sufficient oscillation stabilization wait time is provided for the oscillation circuit by holding the input to the pin at the “L” level for the required time. Note: The INIT reset triggered by INIT pin input initializes the oscillation stabilization wait time to its minimum value.
Chapter 9 Reset 10.
Chapter 9 Reset 10.
Chapter 10 Standby 1.Overview Chapter 10 Standby 1. Overview Two standby modes (low power consumption modes) are available. • Sleep mode: Stops the program • Stop mode: Shuts down the device Note: It is possible to keep the Real Time Clock active in STOP mode (see chapter RTC). 2. Features ■ Sleep mode • Device state in sleep mode: • Halts the program. • CPU program execution only stops. Peripheral functions can continue to operate. • The internal memory and internal bus halt.
Chapter 10 Standby 3.Configuration 3. Configuration Figure 3-1 Configuration Diagram State transition control circuit (for standby modes) SYNCS 0 1 OSCD1 0 1 TB CR: bit0 Setting prohibited Synchronous standby SLEEP STCR: bit7 0 1 Do not change to sleep mode. Change to sleep mode. Sleep signal STOP STCR: bit7 Stop signal 0 1 Do not change to stop mode. STCR: bit0 Change to stop mode. Do not halt main clock oscillation during stop mode.
Chapter 10 Standby 4.Registers 4. Registers 4.1 STCR: Standby Control Register Used to control transition to the stop and sleep standby modes, and to specify the pin states and whether to halt the oscillation during stop mode. Note: See “Chapter 9 Reset (Page No.139)” also.
Chapter 10 Standby 4.Registers • Bit0: Main clock oscillation halt OSCD1 0 1 Operation of main clock during stop mode Continue oscillation Halt oscillation 4.2 TBCR: Timebase timer control register This register controls the timebase timer interrupts and the options for resets and standby operation. Note: See also “Chapter 19 Timebase Timer (Page No.263)”.
Chapter 10 Standby 5.Operation 5. Operation 5.1 Sleep Mode ■ Entering sleep mode Writing “1” to the sleep mode bit (STCR.SLEEP) changes to sleep mode. The device remains in this mode until an event occurs to wakeup the device from sleep mode. (See “8. Caution (Page No.165)”.) ■ Device state in sleep mode • CPU program execution stops. (Peripheral functions continue to operate.) • The internal memory and internal bus halt.
Chapter 10 Standby 5.Operation 5.2 Stop mode ■ Entering stop mode Writing “1” to the stop mode bit (STCR.STOP) changes to stop mode. The device remains in this mode until an event occurs to wakeup the device from stop mode. (See “8. Caution (Page No.165)”.) ■ Device state in stop mode • The overall device halts (internal circuits halt and the internal clock signals halt). • Circuits that halt during stop mode All internal circuits except those listed below.
Chapter 10 Standby 6.Settings 6. Settings Table 6-1 Settings Required to Change to Sleep Mode Setting Setting procedure* Setting register Interrupt settings (See the chapter for each peripheral function.) — Synchronous standby settings Timebase timer control register (TBCR) See 7.1 Change to sleep mode Standby control register (STCR) See 7.1 Operational restrictions (See “8. Caution (Page No.165)”.) — *:For the setting procedure, refer to the section indicated by the number.
Chapter 10 Standby 7.Q&A 7.2 How do I change to stop mode? • When operating on the main PLL clock, the operating clock must be set to the main clock divided by two. See “7.3 How do I select the operating clock source? (Page No.202)” for details about changing the operating clock. • Before you can change to stop mode, you must first set the synchronous standby operation enable bit (TBCR.SYNCS). See section 7.1. • Set using the stop mode bit (STCR.STOP).
Chapter 10 Standby 7.Q&A 7.6 How do I recover from stop mode? The following events end stop mode: • The following four interrupts change the device to the oscillation stabilization wait state. • External level-detect interrupt or edge-detect interrupt. • Oscillation stabilization wait timer for the main clock when oscillation not halted. • Sub oscillation stabilisation timer when oscillation not halted. • Real time clock when oscillation not halted.
Chapter 10 Standby 7.
Chapter 10 Standby 8.Caution 8. Caution • Points to note when changing to sleep mode When changing to sleep mode, set the synchronous standby operation enable bit (TBCR.SYNCS= “1”). Also, in order to change to sleep mode with synchronous standby operation enabled, the STCR register must be read after writing to the SLEEP bit. Always use the following sequence.
Chapter 10 Standby 8.
Chapter 11 Memory Controller 1.Overview Chapter 11 Memory Controller 1. Overview This module combines the interfaces to the F-Bus memory resources, FLASH and General Purpose RAM (also referenced as I/D-RAM). These memories can be combined CODE and DATA storage. While code fetch is possible in general via the F-Bus at the FR core, due to performance reasons the code fetch is accellerated by a direct I-Bus connection in MB91460 series MCUs.
Chapter 11 Memory Controller 7.Registers • Reset vector address: 0x000ffffc; return 0x00030000 at RAM execution mode (jump to test program) or return 0x0000bff8 in any other case (jump to Boot ROM) • If FMCS_FIXE is switched off, the FLASH memory can be accessed on addresses 0x000ffff8 and 0x000ffffc. FIXE is set at reset. 7.
Chapter 11 Memory Controller 8.Explanations of Registers 8.
Chapter 11 Memory Controller 8.Explanations of Registers • BIT[29]: BIRE - Burn-In ROM Enable 0 Disable Burn-In ROM and enable FLASH access at Burn-In ROM address 1 Enable access to the Burn-In ROM (default) The BIRE bit is a reserved bit and should not be used. • BIT[28]: RDYEG - RDY status hold and qittation register 0 Auto algorithm not started or started and not compleated (default) 1 The FLASH auto-algorithm has been completed since last register read access.
Chapter 11 Memory Controller 8.Explanations of Registers Important remark: To maintain data consistency it is strongly recommended to disable the instruction cache while writing to the FLASH memory and to flush the instruction cache (FLUSH=1) after completing the write procedure to the FLASH memory. Important remark: It is not allowed to switch between the 16 bit, the 32 bit and the 64 bit mode while reading instructions or data from the FLASH memory.
Chapter 11 Memory Controller 8.Explanations of Registers • BIT[17]: PF2I - Prefetch 32 bit (2 instructions) only 0 Prefetch 64 bit (default) 1 Prefetch 32 bit only When switching on 64 bit read mode (RD64=1) then prefetch will be performed on instruction address IA+8 (when current access is aligned at IA+0) and on instruction address IA+4 (when current access is aligned at IA+4).
Chapter 11 Memory Controller 8.Explanations of Registers • BIT[7]: FLUSH - Flush instruction cache entries 0 Flushing the instruction cache entries has been completed 1 Actually flushing the instruction cache entries This bit is set after reset. If the FLUSH bit is set, the instruction cache entries are flushed sequentially. During this initialization the cache is disabled. The initialization has a duration of 1 clock cycle per cache entry.
Chapter 11 Memory Controller 8.Explanations of Registers • BIT[4]: PFMC - Prefetch Miss Cache enable 0 Standard cache algorithm (default) 1 Prefetch misses are cached only This bit is cleared after reset. The prefetch miss cache is disabled by default. The instruction cache uses the standard algorithm of writing cache entries for each accessed instruction word from FLASH. Setting the PFMC bit switches to a second write algorithm for cache entries.
Chapter 11 Memory Controller 8.Explanations of Registers • BIT[1:0]: SZ[1:0] - Cache size configuration 00 0kByte - Cache disabled 01 4kByte (1024 entries) 10 8kByte (2048 entries) 11 16kByte (4096 entries) (default) The cache size is set to ’11’ after reset. The cache size can be configured on the evaluation device (EVA). Remark: The number of cache entries determines the TAG initialization period at device startup, see the explanaition of the FLUSH bit above.
Chapter 11 Memory Controller 8.Explanations of Registers WTP controls the wait timing of the FLASH access in case of page hit for Page Mode FLASH. The WTP configuration is in units of clock cycles. The value of WTP should be set to the intra page access time (cycle time) of the FLASH memory in number of clock cycles, subtracted by one. The setting is used if the page size PS[2:0] is set different to 0. • BIT[29:28]: WEXH[1:0] - Minimum WEX High timing requirement WEXH is set to 3 after reset.
Chapter 11 Memory Controller 8.Explanations of Registers FLASH access cycle waveform flash_start FMA ATDIN EQIN flash_wait DO tATD tALEH tEQ tWTC tRC Figure 8-1 Timing of a FLASH access cycle Figure 8-1 shows the example of a FLASH access cycle. In the FMWT register the three parts of the FLASH timing tATD, tALEH, tEQ and tWTC can be configured independently. The table below lists the configuration values for this example. Symbol Length Setup tATD 1.5 cycles ATD=2 tALEH 1.
Chapter 11 Memory Controller 8.Explanations of Registers ● FLASH Memory Adddress Check register (FMAC) FMAC Address 7008H +0 -------- [R] +1 -0000000 +2 00000000 +3 00000000 This register captures the address at the begin of a FLASH access cycle for test purposes. The register could be read only. ● Non-cacheable area definition The non-cacheable area definition registers FCHA0 and FCHA1 define the FLASH region not to be cached. Not used bits are read back as zero.
Chapter 12 Instruction Cache 1.General description Chapter 12 Instruction Cache This chapter describes the instruction cache memory included in MB91460 family members and its operation. 1. General description The instruction cache is a fast local memory for temporary storage. Once an instruction is accessed to be fetched from external slower memory, the instruction cache holds the instruction code inside to increase the speed of accessing the same code from then on.
Chapter 12 Instruction Cache 2.
Chapter 12 Instruction Cache 2.Main body structure FLUSHbit is set to "0" when the cache is flushed.) [Bit 1] LRU bit (way 1 only) This bit exists only in the instruction cache tag in way 1. The bit indicates way 1 or 2 as the way containing the last entry accessed in the selected set. When set to "1", the LRU bit indicates that the entry of the set in way 1 is the last entry accessed. When set to "0", it indicates that the one in way 2 is the last entry accessed.
Chapter 12 Instruction Cache 2.Main body structure [Bit 7] RAM: RAM Mode Setting this bit to "1" causes the cache to operate in RAM mode. By placing the cache in RAM mode, the cache RAM is mapped as shown in Figure I-CACHE-3 while the cache is enabled with the ENAB bit set to "1". [Bit 5] GBLK: Global lock bit This bit locks all of the current entries in the cache. Setting the GBLK bit to "1" prevents the valid entries in the cache from being updated when a cache miss occurs.
Chapter 12 Instruction Cache 2.
Chapter 12 Instruction Cache 2.
Chapter 12 Instruction Cache 3.Operating mode conditions 3. Operating mode conditions ● Cache status in various operating modes The table below indicates the prevailing state for disable and flush when the associated bit is changed by bit manipulation instruction, etc. Immediately after a Reset Disable (FNAB=0) Flushed Cache Memory Contents undefined The preceding state is held. Rewriting is impossible while the cache is disabled. The preceding state is held.
Chapter 12 Instruction Cache 4.Cacheable areas in the instruction cache ● Cache Entry Update Cache entries are updated as shown in the following table. Unlock Lock Hit Not updated Not updated. Miss The memory data is loaded, and the cache entry data is updated. Not updated at tag miss. Updated when sub-block invalid. 4. Cacheable areas in the instruction cache • The instruction cache can cache data only in external bus space.
Chapter 12 Instruction Cache 5.Settings for handling the I-Cache To disable the I-Cache, set the ENAB bit to 0. Idi #0x000003e7,r0 // I-Cache control register address Idi #0B00000000,r1 // ENAB bit (bit 0) stb r1,@r0 // Writing to register In the resultant state (same as state prevailing after reset), there appears to be no cache.
Chapter 12 Instruction Cache 5.Settings for handling the I-Cache Only lock information is released; locked instructions are replaced sequentially with new instructions according to the state of the LRU bit.
Chapter 13 Clock Control 1.Overview Chapter 13 Clock Control 1. Overview The clock control circuit consists of the source oscillator, base clock generator, and operating clock generator. The circuit supports a range of clock speeds from the high speed clock (100MHz maximum) to the low speed clock (32.768kHz).
Chapter 13 Clock Control 3.Configuration • External bus clock (CLKT): F/1, /2, /3, /4, /5, /6, /7, /8, ..., /16 The clock used by the external bus expansion interface. The circuits that use this clock are as follows. • External bus expansion interface • External CLK output 3.
Chapter 13 Clock Control 4.Registers 4. Registers 4.1 CLKR: Clock Source Control Register Selects the clock source for the base clock used to run the MCU and controls the PLL. • CLKR: Address 0484h (Access: Byte) 7 - 6 - 5 - 4 - 3 SCKEN 2 PLL1EN 1 CLKS1 0 CLKS0 X X X X 0 0 0 0 X X X X X X X X R/W0 R/W0 R/W0 R/W0 R/W R/W R/W R/W bit Initial value (INIT pin input, watchdog reset) Initial value (Software reset) Attribute (See “Meaning of Bit Attribute Symbols (Page No.
Chapter 13 Clock Control 4.Registers • After setting “11B” (subclock), insert one or more NOP instructions. • Selecting the subclock as the clock source is prohibited while the subclock selection enable bit (SCKEN) is “0”. (See table for details.
Chapter 13 Clock Control 4.Registers 4.2 DIV0R: Clock Division Setting Register 0 Sets the division ratio for the clocks used for internal device operation. DIVR0: Address 0486h (Access: Byte, Half-word) 7 B3 6 B2 5 B1 4 B0 3 P3 2 P2 1 P1 0 P0 0 0 0 0 0 0 1 1 X X X X X X X X R/W R/W R/W R/W R/W R/W R/W R/W bit Initial value (INIT pin input, watchdog reset) Initial value (software reset) Attribute (See “Meaning of Bit Attribute Symbols (Page No.
Chapter 13 Clock Control 4.Registers 1010 1011 1100 1101 1110 1111 Φ/11 Φ/12 Φ/13 Φ/14 Φ/15 Φ/16 • Sets the clock division ratio for the clock used by the peripheral circuits and peripheral bus (CLKP). The 16 options listed in the table are available. • Do not set a division ratio that exceeds the maximum operating frequency of the MCU.
Chapter 13 Clock Control 4.Registers 4.3 DIV1R: Clock Division Setting Register 1 Sets the division ratio for the clocks used for internal device operation. • DIVR1: Address 0487h (Access: Byte, Half-word) 7 T3 0 X R/W 6 T2 0 X R/W 5 T1 0 X R/W 4 T0 0 X R/W 3 – 0 X R/W 2 – 0 X R/W 1 – 0 X R/W 0 – 0 X R/W bit Initial value (INIT pin input, watchdog reset) Initial value (software reset) Attribute (See “Meaning of Bit Attribute Symbols (Page No.10)” for details of the attributes.
Chapter 13 Clock Control 4.Registers 4.4 CSCFG: Clock Source Configuration Register This register controls the main clock oscillation in subclock mode • CSCFG: Address 04AEh (Access: Byte) 7 6 EDSUEN PLLLOCK 5 RCSEL 4 MONCKI 3 CSC3 2 CSC2 1 CSC1 0 CSC0 0 X 0 0 0 0 0 0 X X X X X X X X R/W R R/W R/W R/W R/W R/W R/W bit Initial value (INIT pin input, watchdog reset) Initial value (software reset) Attribute (See “Meaning of Bit Attribute Symbols (Page No.
Chapter 13 Clock Control 4.
Chapter 13 Clock Control 4.Registers 4.5 OSCCR: Oscillation Control Register This register controls the main clock oscillation in subclock mode • OSCCR: Address 04CCh (Access: Byte) 7 – 6 – 5 – 4 – 3 – 2 – 1 OSCDS2 0 OSCDS1 X X X X 0 0 0 0 X X X X X X X X RX/WX RX/WX RX/WX RX/WX RX/WX RX/WX R/W R/W bit Initial value (INIT pin input, watchdog reset) Initial value (software reset) Attribute (See “Meaning of Bit Attribute Symbols (Page No.10)” for details of the attributes.
Chapter 13 Clock Control 5.Operation 5. Operation This section describes how to setup and switch between clocks. 5.1 Clock Setup Sequence (Example) (1) Main clock oscillation stabilization, sub clock oscillation stabilization (2) Operate using initial values (main clock divided by 2). Setup operating clocks. (2) Set divide ratios for operating clocks. (CLKB, CLKP, CLKT) (3) Select PLL multiplier. ( PLLS[2:0] ) (4) Enable main PLL operation (PLL1EN), and enable sub clock operation (PLL2EN).
Chapter 13 Clock Control 5.Operation 5.3 Notes ■ Main PLL control After initialization, the main PLL oscillation is halted. While halted, the output of the main PLL cannot be selected as the clock source. After the program starts, first set the multiplier for the main PLL that you want to use as the clock source and then, after allowing a time for the main PLL to lock, change the clock source. The recommended method for waiting for the main PLL to lock is to use the timebase timer interrupt.
Chapter 13 Clock Control 6.Settings 6. Settings Table 6-1 Settings for Operating at 1/2 of the Main Clock Setting Clock source selection Setting register Clock source control register (CLKR) Setting procedure* See 7.3 *: For the setting procedure, refer to the section indicated by the number. Table 6-2 Settings for Operating Using the Main PLL Setting Main PLL operation enable Clock source selection Setting register Clock source control register (CLKR) Setting procedure* See 7.1 See 7.
Chapter 13 Clock Control 7.Q & A 7. Q & A 7.1 How do I enable or disable clock operation? • There is no operation enable bit for the main clock. Main clock operation is always enabled. (Halting the oscillation in subclock mode or stop mode is handled separately.) • Main PLL operation is enabled by the main PLL operation enable bit (CLKR.PLL1EN). Operation To halt the main PLL To enable operation of the main PLL Main PLL operation enable bit (PLL1EN) Set to “0”. Set to “1”.
Chapter 13 Clock Control 7.Q & A 7.4 How do I set the operation clock division ratios? • CPU clock setting The CPU clock setting is set using the CLKB division ratio selection bits (DIVR0.B[3:0]). Example frequency When FΦ = 32MHz When FΦ = 16MHz PLL multiplier ratio CLKB division ratio selection bits(B[3:0]) To select no division Set to “0000”. FCLKB = 32.0MHz FCLKB = 16.0MHz To select divide by 2 Set to “0001”. FCLKB = 16.0MHz FCLKB = 8.00MHz To select divide by 3 Set to “0010”. FCLKB = 10.
Chapter 13 Clock Control 7.Q & A 7.5 How do I halt the main clock in sub clock mode? Set using the “halt main clock oscillation in subclock mode” bit (OSCCR.OSCDS1). Operation in subclock mode To not halt the main clock To halt the main clock Halt main clock oscillation in subclock mode bit (OSCDS1) Set to “0”. Set to “1”. (See “8. Caution (Page No.205)”.) 7.6 How do I halt the sub clock in sub clock on RC oscillator mode? Set using the “halt main clock oscillation in subclock mode” bit (OSCCR.OSCDS2).
Chapter 13 Clock Control 8.Caution 8. Caution • Operation is not guaranteed if the clock source selection, main PLL multiplier setting, and division ratio setting result in a frequency that exceeds the maximum. • Take care with the sequence in which you set or modify the clock source selection. • When the main clock oscillation is set to halt during subclock mode (OSCDS1 = “1”), selecting the main clock (CLKS[1:0])=“00”, “01”, or “10”) is prohibited.
Chapter 13 Clock Control 8.
Chapter 14 PLL Interface 1.Overview Chapter 14 PLL Interface 1. Overview • This blockdiagram (simplified) shows the integration of the PLL and the PLL Interface with the multiplier control logic (1/M, 1/N for basic frequency multiplication and 1/G for clock auto gear). Clock Unit XIN1 CPU-Core Resources Ext Bus PLL Interface PLLIN PLL X 1/G 1/M CK MAIN Osc. Phase Correction M U X FB 1/N Clocktree CLKB CLKP CLKT M U X FB1 delay 2.
Chapter 14 PLL Interface 4.Registers 4. Registers 4.1 PLL Control Registers Controls the PLL multiplier ratio (divide-by-M and divide-by-N) and the automatic clock gear up/down function.
Chapter 14 PLL Interface 4.Registers (See “Meaning of Bit Attribute Symbols (Page No.10)” for details of the attributes.) • Bit7-6: Reserved bits.The read value is always “0”.
Chapter 14 PLL Interface 4.Registers • PLLMULG: Address 048Fh (Access: Byte, Halfword, Word) 7 MLG7 6 MLG6 5 MLG5 4 MLG4 3 MLG3 2 MLG2 1 MLG1 0 MLG0 0 0 0 0 0 0 0 0 X X X X X X X X R/W R/W R/W R/W R/W R/W R/W R/W bit Initial value (INIT pin input, watchdog reset) Initial value (Software reset) Attribute (See “Meaning of Bit Attribute Symbols (Page No.10)” for details of the attributes.) • Bit7-6: Reserved bitThe read value is always “0”.
Chapter 14 PLL Interface 4.Registers • While switching from clock source PLL to clock source oscillator this flag is set when the divide-by-G counter reaches the programmed end value. • This bit is read as “1” at a Read-Modify-Write instructions. Writing “1” has no effect. • Bit1: Interrupt Enable Gear UP. IEUP 0 1 Function Gear UP interrupt disabled [Initial value] Gear UP interrupt enabled • Bit2: Interrupt Flag Gear UP.
Chapter 14 PLL Interface 5.Recommended Settings 5.
Chapter 14 PLL Interface 6.Clock Auto Gear Up/Down 6. Clock Auto Gear Up/Down To avoid voltage drops and surges when switching the clock source from oscillator to high frequency PLL/ DLL output (or vice versa), a clock smooth gear-up and gear-down circuitry is implemented with the PLL interface.
Chapter 14 PLL Interface 6.Clock Auto Gear Up/Down this equals to (resolved closed arithmetic series of the first sum term): i ⎛i ⋅ (i + 1) ⋅ (i + 2) ⎞ duration = mul ⋅ t ⋅ ⎜ ------------------------------------------ – ∑ k ⋅ ( i – k + 1 )⎟ 6 ⎝ ⎠ k = j+1 with i = G ; j = G - M ; mul = MULG ; t = 1/f(pllout) For the above given setting this equals 1483 PLL output clock cycles with a duration from the start frequency to the target frequency of 9262500 ps (about 9.3 us).
Chapter 14 PLL Interface 7.Caution 7. Caution When using the clock auto-gear function it is strongly recommended to make use of the gear up and gear down flags (PLLCTRL.GRUP, PLLCTRL.GRDN) to evaluate the current state of this function to avoid malfunctions in the clock system due to setting changes prior to completion. Procedure example: • Set the PLL interface registers (PLLDIVN, PLLDIVM, PLLDIVG, PLLMULG) according to the selected frequency and gear duration • Switch on the PLL (CLKR.
Chapter 14 PLL Interface 7.
Chapter 15 CAN Clock Prescaler 1.Overview Chapter 15 CAN Clock Prescaler 1. Overview • This blockdiagram (simplified) shows the integration of the CAN and the CAN Interface with the CAN clock prescaler logic (1/C) and clock source selector. CAN Clock Prescaler MAIN Osc.
Chapter 15 CAN Clock Prescaler 3.Registers 3. Registers 3.1 CAN Clock Control Register Controls the CAN clock source, the clock division ratio and the clock disable. • CANPRE: Address 04C0h (Access: Byte) 7 - 6 - 5 CPCKS1 4 CPCKS0 3 DVC3 2 DVC2 1 DVC1 0 DVC0 0 0 0 0 0 0 0 0 0 0 X X X X X X R0/W0 R0/W0 R/W R/W R/W R/W R/W R/W bit Initial value (INIT pin input, watchdog reset) Initial value (Software reset) Attribute (See “Meaning of Bit Attribute Symbols (Page No.
Chapter 15 CAN Clock Prescaler 3.Registers 0 0 0 0 X X X X R/W0 R/W0 R/W R/W R/W R/W R/W R/W Initial value (Software reset) Attribute (See “Meaning of Bit Attribute Symbols (Page No.10)” for details of the attributes.) • Bit7-6: Reserved bitAlways write “0” to these register bits.
Chapter 15 CAN Clock Prescaler 3.
Chapter 16 Clock Supervisor 1.Overview Clock Supervisor Chapter 16 Clock Supervisor This section gives an overview of the Clock Supervisor. Purpose of the Clock Supervisor is the supervision of the main and sub oscillation clock. In case of main oscillation clock failure the Clock Supervisor control logic will take action, i.e. switching to an internal RC-oscillation clock, depending on the operation mode set in the control register. 1.
Chapter 16 Clock Supervisor 2.Clock Supervisor Register 2. Clock Supervisor Register This section lists the Clock Supervisor Control Register and describes the function of each bit in detail. ■ Clock Supervisor Control Register (CSVCR) The Clock Supervisor Control Register (CSVCR) sets the operation mode of the Clock Supervisor. Figure 2-1 shows the configuration of the Clock Supervisor Control Register.
Chapter 16 Clock Supervisor 2.Clock Supervisor Register Table 2-1 describes the function of each bit of the Clock Supervisor Control Register (CSVCR). Table 2-1 Functional Description of each bit of the Clock Supervisor Control Register Bit Name Function 7 SCKS (Sub-clock select) This bit is to select between 32k external oscillation and internal RC oscillation as subclock.
Chapter 16 Clock Supervisor 3.Block Diagram Clock Supervisor 3. Block Diagram Clock Supervisor This section presents a block diagram of the Clock Supervisor.
Chapter 16 Clock Supervisor 4.Operation Modes 4. Operation Modes This section describes all operation modes of the Clock Supervisor. ■ Operation mode with initial settings In case the clock supervisor control register (CSVCR) is not configured at the beginning of the user program, the RC-oscillator, the main clock supervisor and the sub-clock supervisor is enabled. • The RC-oscillator is enabled at power-on.
Chapter 16 Clock Supervisor 4.
Chapter 16 Clock Supervisor 4.
Chapter 16 Clock Supervisor 4.
Chapter 16 Clock Supervisor 4.
Chapter 16 Clock Supervisor 4.
Chapter 16 Clock Supervisor 4.Operation Modes ■ Disabling the RC-oscillator and the clock supervisors The initial point of this scenario is that the RC-oscillator and main clock or sub-clock supervisor is enabled. • The RC-oscillator can be disabled by setting bit RCE (bit 4 of CSVCR) to ’0’. First disable the main clock and sub-clock supervisor. Do not disable the RC-oscillator while either the main clock or sub-clock supervisor is still enabled.
Chapter 16 Clock Supervisor 4.Operation Modes ■ Re-enabling the RC-oscillator and the clock supervisors The initial point of this scenario is that the RC-oscillator and both main clock and sub-clock supervisor are disabled. • The RC-oscillator can be enabled by setting RCE (bit 4 of CSVCR) to ’1’. • The main clock supervisor is enabled by setting MSVE (bit 3 of CSVCR) to ’1’. Enabling of the main clock supervisor must only take place 100 µ s after the RC-oscillator is enabled.
Chapter 16 Clock Supervisor 4.Operation Modes ■ Sub-clock modes The main clock supervisor is automatically disabled in sub-clock modes. The enable bit MSVE remains unchanged.
Chapter 16 Clock Supervisor 4.
Chapter 16 Clock Supervisor 4.
Chapter 16 Clock Supervisor 4.Operation Modes ■ Stop mode If RC-oscillator, main clock and sub-clock supervisors are enabled, they will be automatically disabled at transition into stop mode. The corresponding enable bits in the clock supervisor control register remain unchanged. So after wake-up from stop mode the RC-oscillator and the clock supervisors will be enabled again.
Chapter 16 Clock Supervisor 4.Operation Modes ■ Operation with single clock device In a single clock device the sub-clock supervisor can provide the RC-oscillation clock as sub-clock. To enable this feature, SCKS bit (bit7 of CSVCR) must be set to ’1’ (refer to Table 2-1for precautions when modifying this bit) and SRST must be ’0’ (initial value). Before the transition to sub-clock mode, it has to be confirmed by software that the sub-clock has been substituted by the RC-oscillation clock.
Chapter 16 Clock Supervisor 4.Operation Modes ■ Check if reset was asserted by the Clock Supervisor To find out whether the Clock Supervisor has asserted reset , the software must check the reset cause by reading the WDTC register at address A8H. If ERST (bit 4 of WDTC) is set, the cause was either external reset at the RSTX pin or the clock supervisor. If neither SM bit nor MM bit (bit 5 and bit 6 of CSVCR) is set, reset cause was the external reset.
Chapter 17 Clock Modulator 1.Overview Chapter 17 Clock Modulator This chapter provides an overview of the Clock Modulator and its features. It describes the register structure and operation of the Clock Modulator. 1. Overview The clock modulator is intended for the reduction of electromagnetic interference - EMI, by spreading the spectrum of the clock signal over a wide range of frequencies. The module is fed with an unmodulated reference clock with frequency F0, provided by the PLL circuit.
Chapter 17 Clock Modulator 2.Clock Modulator Registers 2. Clock Modulator Registers This section lists the clock modulator registers and describes the function of each register in detail.
Chapter 17 Clock Modulator 2.
Chapter 17 Clock Modulator 2.Clock Modulator Registers ● Clock modulator control register contents Table 2-1 Function of each bit of the clock modulator control register (1 / 2) Bit name Function bit7 undefined bit 6 to 5 Reserved Always write 0 to this bit. bit 4 Reserved Always write 1 to this bit.
Chapter 17 Clock Modulator 2.Clock Modulator Registers Table 2-1 Function of each bit of the clock modulator control register (2 / 2) Bit name Function bit 1 FMOD: Frequency modulation enable bit "0": Frequency modulation disabled. "1": Frequency modulation enabled. • To enable the modulator in frequency modulation mode, FMOD must be set to 1. • Before the modulator can be enabled, the PLL must deliver a stable reference clock (PLL lock time must be elapsed).
Chapter 17 Clock Modulator 2.Clock Modulator Registers Table 2-2 States of the modulator FMOD PDX FMODRUN (read only) modulator enabled in frequency modulation mode, modulator is calibrating, modulation not active 1 1 0 modulator is running in frequency modulation mode modulation is active 1 1 1 others not allowed ● Clock Modulation Parameter Register (CMPR) The Modulation Parameter Register (CMPR) determines the modulation degree in frequency modulation mode.
Chapter 17 Clock Modulator 2.Clock Modulator Registers Table 2-3 Function of each bit of the modulation parameter register (CMPR) Bit name bit 13 to 0 MP13 to 0: Modulation Parameter bits Function Depending on the PLL frequency the following modulation parameter settings are possible. The corresponding CMPR register value is stated in the most right column.
Chapter 17 Clock Modulator 2.Clock Modulator Registers F0: Frequency of unmodulated input clock (PLL frequency) T0: Period of unmodulated input clock (PLL clock period) resolution: resolution of frequencies in the modulated clock.
Chapter 17 Clock Modulator 3.Application Note The table below shows the recommended setting for several MCU clocks and modulation parameters: Table 2-4 Modulation Parameter settings F0 (MHz) resolution mod degree Fmin (MHz) Fmax (MHz) +/- phase skew 50 [periods] +/- phase skew min/max [periods] CMPR Please refer to the datasheet of each device about modulation parameter settings. 3. Application Note Startup/stop sequence for frequency modulation mode.
Chapter 17 Clock Modulator 3.Application Note recommended. 1. define the required PLL frequency based on performance needs e.g. 16 MHz 2. determine the maximal allowed clock frequency of the MCU e.g. 32 MHz 3. choose the setting with the highest resolution and the highest modulation degree, whose maximal frequency is below the maximal allowed clock frequency of the MCU. e.g. resolution:7, degree:2, CMPR=0x05F2 (Fmax= 30.34 MHz) 4. perform EMI measurements 5.
Chapter 18 Timebase Counter 1.Overview Chapter 18 Timebase Counter 1. Overview The timebase counter is a 26-bit up-counter that counts the subclock or the main clock divided by two. When recovering from a state in which the selected clock source for the MCU has been, or may have been, halted, the MCU automatically changes to the oscillation stabilization wait state to avoid any unstable output from the oscillator.
Chapter 18 Timebase Counter 3.Configuration ■ Events that invoke an oscillation stabilization wait using other than the timebase counter ● Wait time after power on: Provided by pin input ● Wait time after changing from subclock to main clock: Using the main oscillation stabilization wait timer to generate this time is recommended. ● When recovering from main clock oscillation halted: Enabling the main clock oscillation and waiting for oscillation to stabilize is required.
Chapter 18 Timebase Counter 4.Registers 4. Registers 4.1 STCR: Standby Control Register Controls transition to standby modes, pin states during stop mode, whether to halt the clock during stop mode, the oscillation stabilization wait time, and software reset. Note: See also “Chapter 10 Standby (Page No.155)” and “Chapter 20 Software Watchdog Timer (Page No.273)” chapters.
Chapter 18 Timebase Counter 4.Registers 4.2 CLKR: Clock Source Control Register Selects the clock source for the base clock used to run the MCU and controls the PLL. Note: See also the “Chapter 13 Clock Control (Page No.189)”.
Chapter 18 Timebase Counter 5.Operation 5. Operation This section describes the events that trigger an oscillation stabilization wait and the operation in each case. 5.1 INIT Pin Input An oscillation stabilization wait is required after power on. As the wait time provided by the initialized timebase counter is too short, the INIT pin input must be held at the “L” level.
Chapter 18 Timebase Counter 5.Operation 5.2 Watchdog Reset (The specified oscillation stabilization wait time is generated automatically) If a watchdog reset occurs while the main clock oscillation is halted, the oscillation stabilization wait time is generated automatically. (See figure below.
Chapter 18 Timebase Counter 5.Operation ■ Watchdog reset when main clock operating Although no oscillation stabilization wait is required in this case, the specified wait time is generated automatically. 5.3 Recovering from Stop Mode via an Interrupt ■ When changing from main PLL operation to stop mode with the main clock oscillation halted (STCR.OSCD[2:1]=“11”): The main oscillation circuit generates the selected oscillation stabilization time automatically.
Chapter 18 Timebase Counter 5.Operation ■ When changing to stop mode without halting the clock oscillation circuit (main PLL/main/ sub): Although no oscillation stabilization wait is required in this case, a wait is generated automatically. Accordingly, it is recommended that you set the interval time to its minimum value before changing to stop mode. • When recovering from stop mode, the device goes to the oscillation stabilization wait state immediately after stop mode is released.
Chapter 18 Timebase Counter 5.Operation 5.7 Types of Oscillation Stabilization Wait ■ Timebase counter Automatically provides a count for the oscillation stabilization wait time. When a trigger occurs to change the device to the oscillation stabilization wait state, the timebase counter is cleared and then starts counting the specified oscillation stabilization wait time.
Chapter 18 Timebase Counter 5.Operation 5.8 Whether or not a Stabilization Wait is Required for Each State Transition See figure below.
Chapter 18 Timebase Counter 6.Settings 6. Settings Table 6-1 Settings Required to Specify the Oscillation Stabilization Wait Time Setting Setting register Oscillation stabilization wait time setting Standby control register (STCR) Setting procedure* See 7.1. *: For the setting procedure, refer to the section indicated by the number.
Chapter 18 Timebase Counter 7.Q&A 7. Q&A 7.1 How do I setup the oscillation stabilization wait time that is generated automatically? Use the oscillation stabilization wait time selection bits (STCR.OS[1:0]). (The following lists likely scenarios and the required settings.
Chapter 18 Timebase Counter 7.Q&A 7.2 How do I set the oscillation stabilization wait time without generating it automatically? The settings described below for various cases are required.
Chapter 18 Timebase Counter 8.Caution 8. Caution • Clock source If the clock selected as the clock source is not stable, an oscillation stabilization wait time is required. • Oscillation stabilization wait time The wait time set in the oscillation stabilization time selection bits (STCR.OS[1:0]) is not initialized by any reset except a reset triggered by the external INITX pin input, the RC based watchdog or the Clock Supervisor.
Chapter 19 Timebase Timer 1.Overview Chapter 19 Timebase Timer 1. Overview The timebase timer is a selector that uses the output from a 26-bit timebase counter using the base clock (F). The timebase timer is an interval-interrupt generating timer that is used to acquire main PLL lock wait time and to count a long time. Watchdog control section Timebase counter Base clock (φ) Watchdog timer 26-bit counter Timebase timer Selector Timebase timer interrupt 2.
Chapter 19 Timebase Timer 3.Configuration 3.
Chapter 19 Timebase Timer 4.Register 4. Register 4.1 TBCR: Timebase Timer Control Register This register is used to set timebase timer interrupt control, reset/ standby operation option etc. Note: Refer also to “Chapter 10 Standby (Page No.155)”.
Chapter 19 Timebase Timer 4.Register • Bit1: Enabling the synchronous reset operation SYNCR 0 1 Operation Ordinary reset operation Synchronous reset operation enable • Ordinary operation reset: Immediately resets the operation initialization when the operation initialization reset (RST) request is generated. Synchronous reset: Resets the operation initialization after all accesses to the bus have stopped.
Chapter 19 Timebase Timer 5.Operation 5. Operation Timebase timer operation is described. 5.1 Timebase Timer Interrupt Example (Main PLL Lock Wait) Main PLL lock wait by the timebase timer (8) (5) Example of the Main PLL oscillation 600 µsec.
Chapter 19 Timebase Timer 6.Setting 6. Setting Table 6-1 Setting Required for the Timebase Timer Setting Setting register Timebase timer control register control register (TBCR) Timebase counter clear register (CTBR) Setting the interval time Timebase counter clear Setting method* Refer to 7.1 Refer to 7.5 *: Refer to the number for more information on the setting method.
Chapter 19 Timebase Timer 7.Q & A 7. Q & A 7.1 What are the types of interval time used in the timebase timer (and the timebase counter used by the timebase timer) and how to select them? There are eight types of interval time, and they are set using the interval selection bit (TBCR.TBC[2:0]). Example Interval time Timebase timer Interval time Interval selection bit (TBC[2:0]) FΦ =2MHz FΦ = 32MHz FΦ = 32.768kHz How to select Φ × 211 ? Set the value to “000” 1.024ms 64µs 62.
Chapter 19 Timebase Timer 7.Q & A 7.7 What are the interrupt types? One type of interrupt is available, and an interrupt is generated when the interval time that is set using the interval selection bit (TBCR.TBC[2:0]) has elapsed. (Selection is unnecessary.) 7.8 How is an interrupt enabled? Interrupt request enable and interrupt request flag Setting interrupt enable is conducted using the interrupt request enable bit (TBCR.TBIE).
Chapter 19 Timebase Timer 8.Caution 8. Caution • The main PLL needs the PLL lock wait time after operation enable and after modifying the rate of multiply. We recommend that this main PLL lock wait time be acquired using the timebase interrupt. The lockup time of PLL is approximately 600us. Make sure that the PLL lock wait time is set to a value a little larger than 600us.
Chapter 19 Timebase Timer 8.
Chapter 20 Software Watchdog Timer 1.Overview Chapter 20 Software Watchdog Timer 1. Overview The software watchdog timer consists of a selector that uses the output from a 26-bit timebase counter using the base clock (F) and a one-bit counter. The watchdog timer generates the watchdog reset (initial setting reset) if the generation delay operation (an interval watchdog reset) is disabled due to problems such as program runaway.
Chapter 20 Software Watchdog Timer 3.Configuration 3.
Chapter 20 Software Watchdog Timer 4.Register 4. Register 4.1 RSRR: Watchdog Timer Control Register This register is used to set watchdog timer periods, and execute the startup control. (This register also functions as the reset cause register that stores previously generated reset causes.) Note: Refer also to “Chapter 9 Reset (Page No.139)”.
Chapter 20 Software Watchdog Timer 4.Register 1 RST has been triggered by a software reset. The software reset occurred flag (SRST) is cleared to “0” after reading. • Bit2: Low voltage reset occurred flag Indicates whether a reset (INIT) was triggered by the low voltage detection. LINIT 0 1 Meaning No INIT has been triggered by the low voltage detection. INIT has been triggered by the low voltage detection. The low voltage reset occurred flag (LINIT) is cleared to “0” after reading.
Chapter 20 Software Watchdog Timer 4.Register 4.2 WPR: Watchdog Reset Generation Postponement Register This register is used to postpone the generation of watchdog reset. • WPR: Address 0485h (Access: Byte) 7 D7 X X RX,W 6 D6 X X RX,W 5 D5 X X RX,W 4 D4 X X RX,W 3 D3 X X RX,W 2 D2 X X RX,W 1 D1 X X RX,W 0 D0 X X RX,W bit Initial value (INIT) Initial value (RST) Attribute (Refer to “Meaning of Bit Attribute Symbols (Page No.10)” for the attributes.
Chapter 20 Software Watchdog Timer 5.Operation 5. Operation This section describes the watchdog operation. 5.
Chapter 20 Software Watchdog Timer 5.Operation 5.2 Starting the Watchdog Timer and Setting the Watchdog Timer Period The watchdog timer starts once it first writes data to the RSRR (Reset cause register/Watchdog timer control register) after the reset (RST). At this time, Bits 1 and 0 (WT1 and WT0 bits) set the watchdog timer interval time. Only the setting for the interval time executed first after the reset is valid, and the other settings executed at a later time are invalid. 5.
Chapter 20 Software Watchdog Timer 6.Setting 6. Setting Table 6-1 Setting Required for Using the Watchdog Timer Setting Interval time setting Startup of the watchdog Setting register Watchdog timer control register (RSRR) Setting method Refer to 7.1 Refer to 7.2 *: Refer to the number for more information on the setting method.
Chapter 20 Software Watchdog Timer 7.Q & A 7. Q & A 7.1 What are the types of watchdog interval time and how are they selected? There are four types of the interval period, and they are set using the interval selection bit (RSRR.WT[1:0]). Watchdog Interval time To select Φ × 220 To select Φ × 222 To select Φ × 224 To select Φ × 226 Note: Interval Selection bit (WT[1:0]) Set the value to “00” Set the value to “01” Set the value to “10” Set the value to “11” Example) Interval Time FΦ =80.0MHz FΦ = 2.
Chapter 20 Software Watchdog Timer 8.Caution 8. Caution • Although the watchdog interval time corresponds to the one twice as long as the watchdog 1-bit counter, the watchdog timer clear operation only clears the 1-bit counter used for detecting the watchdog. As a result, the time margin to clear the watchdog timer is different from the interval time.
Chapter 21 Hardware Watchdog Timer 1.Overview Chapter 21 Hardware Watchdog Timer 1. Overview The hardware watchdog timer (R/C oscillation based) provides a system reset if an internal watchdog timer is not cleared within the postponement duration. ● Hardware watchdog timer This watchdog timer starts counting after the setting initialization reset (INIT) automatically. Clearing the counter in the postponement duration is necessary to continue running an application.
Chapter 21 Hardware Watchdog Timer 2.Configuration 2. Configuration Hardware watchdog timer consists of two sub-blocks: • Watchdog timer • Timer control and status register ● Block diagram of the hardware watchdog timer Figure 2-1 Block Diagram of hardware watchdog timer Watchdog timer This is a timer to supervise CPU operation. The counter needs to be cleared periodically after releasing the reset.
Chapter 21 Hardware Watchdog Timer 3.Register 3. Register 3.1 Hardware watchdog timer control and status register Hardware watchdog timer control status register (with reset flag and clear bit).
Chapter 21 Hardware Watchdog Timer 3.Register 3.2 Hardware watchdog timer duration register Hardware watchdog timer duration register (elongation of the trigger duration). • HWWDE: Address 04C6h (Access: Byte) 7 - 6 - 5 - 4 - 3 - 2 - 1 ED1 0 ED0 - - - - - - 0 0 - - - - - - 0 0 RX/W0 RX/W0 RX/W0 RX/W0 RX/W0 RX/W0 R/W R/W bit Initial value (INIT pin input, watchdog reset) Initial value (Software reset) Attribute (See “Meaning of Bit Attribute Symbols (Page No.
Chapter 21 Hardware Watchdog Timer 4.Functions 4. Functions If the watchdog timer is not cleared periodically, a setting initialization reset (INIT) occurs. In this case the value of registers in CPU is not guaranteed. ● Function of the hardware watchdog timer After releasing INITX the hardware watchdog timer starts immediately without stabilization time. If the timer is not cleared periodically, setting initialization (INIT) reset occurs.
Chapter 21 Hardware Watchdog Timer 5.Caution 5. Caution ● Software disabling is not possible The watchdog timer starts counting immediately after reset (release of INITX). Software cannot stop the counting. ● Hardware disabling is only possible on the evaluation device MB91V460 The watchdog timer can be permanently disabled by setting the corresponding jumper of the evaluation board (this is not possible on flash devices with this watchdog timer).
Chapter 22 Main Oscillation Stabilisation Timer 1.Overview Chapter 22 Main Oscillation Stabilisation Timer 1. Overview The main clock oscillation stabilisation timer is a 23-bit counter that counts the main clock. This timer does not affect the selection of clock source operated by MCU/dividing setting. This timer is mainly used for acquiring main clock oscillation stability wait time to resume main clock oscillation after the main clock oscillation has been stopped (OSCCR.
Chapter 22 Main Oscillation Stabilisation Timer 3.Configuration 3.
Chapter 22 Main Oscillation Stabilisation Timer 4.Register 4. Register 4.1 OSCRH: Control Register for the Main Clock Oscillation Stability Wait Timer This register is used to select the interval time, clear the timer, control the interrupt, control the timer such as stop, and confirm the state of the timer.
Chapter 22 Main Oscillation Stabilisation Timer 5.Operation 5. Operation This section describes the main clock oscillation stability wait timer operation. 5.1 Main Clock Oscillation Stability Wait (1) Selects the interval time. (WS[1:0]) (In this example, 217/FCL-MAIC is selected.) (2) (3) (4) (5) Sets timer clear (WCL=“0”) by the software. Sets flag clear (WIF=“0”) and interrupt request enable (WIE=“1”) by the software. Sets timer count enable (WEN=“1”) by the software. Releases main clock stop (OSCCR.
Chapter 22 Main Oscillation Stabilisation Timer 5.Operation 5.2 Interval Interrupt (1) Selects the interval time (WS[1:0]). (In this example, 217/FCL-MAIC is selected.) (2) Clears the timer (WCL=“0”), clears flags (WIF=“0”), enables interrupt request (WIE=“1”), enables timer count (WEN=“1”) by the software. (3) The timer counts up using the main clock (source oscillation). (4) Generates interval interrupt at the selected interval time (Falling of the dividing 217).
Chapter 22 Main Oscillation Stabilisation Timer 6.Setting 6. Setting Figure 6-1 Settings Required for Using the Main Clock Oscillation Stability Wait Timer Setting Setting interval time Count clear Counting operation start Setting register Main clock oscillation stability wait timer control register (OSCRH) Setting method* 7.1 7.4 7.3 *: Refer to the number for more information on the setting method.
Chapter 22 Main Oscillation Stabilisation Timer 7.Q & A 7. Q & A 7.1 What are the types of interval time (wait time) and how are they selected? There are 3 types of interval time, and they are set with the interval selection bit (OSCRH.WS[0:1]). Interval selection bit (WS[1:0]) Interval (Wait time) Example At FCLKP = 4.00MHz To set the value to 212/FCL-MAIN Set the value to “01” 1.00ms To set the value to 217/FCL-MAIN Set the value to “10” 32.
Chapter 22 Main Oscillation Stabilisation Timer 7.Q & A 7.6 What are the types of interrupt? There is one type of interrupt called the main clock oscillation stability wait timer interrupt. (Selection is unnecessary.) 7.7 how is an interrupt enabled? Interrupt request enable and interrupt request flag Setting the interrupt enable is performed with the interrupt request enable bit (OSCRH.WIE).
Chapter 22 Main Oscillation Stabilisation Timer 8.Caution 8. Caution • To wait until the main clock oscillation stability is attained while the subclock is in operation, it is necessary to acquire wait time using the main clock oscillation stability wait timer. (An unstable clock may be supplied to the entire device, and normal operation is not guaranteed if the MCU operation mode is switched from the sub-RUN to the main RUN mode without waiting until the main clock oscillation becomes stable.
Chapter 22 Main Oscillation Stabilisation Timer 8.
Chapter 23 Sub Oscillation Stabilisation Timer 1.Overview Chapter 23 Sub Oscillation Stabilisation Timer 1. Overview The sub oscillation stabilisation timer is a 15-bit counter that is counted up with the subclock. This timer does not affect the selection/dividing setting of the MCU operating clock. This timer is used to acquire subclock oscillation stability wait time if the subclock oscillation is resumed mainly when the subclock oscillation is stopped while the main clock is in operation.
Chapter 23 Sub Oscillation Stabilisation Timer 3.Configuration 3.
Chapter 23 Sub Oscillation Stabilisation Timer 4.Register 4. Register 4.1 WPCRH: Sub oscillation stabilisation timer Control Register This register is used to select interval time, clear the timer, control interrupt, control timer stop etc., and confirm the states.
Chapter 23 Sub Oscillation Stabilisation Timer 4.Register watchdog reset), but the operation initialization reset (Software reset) holds the current value instead of initializing it. 2: If you set the interrupt request enable (WIE=“1”), and the interval period selection (WS[1:0]) after canceling the reset, be sure to simultaneously set the timer interrupt request flag (WIF) and the timer clear (WCL) “0”.
Chapter 23 Sub Oscillation Stabilisation Timer 5.Operation 5. Operation 5.1 Subclock Oscillation Stability Wait Interrupt Figure 5-1 Reference (7) (5) Subclock oscillation example Clock timer counting (8) 0400h (6) 0000h Time (1) 2 10 (Bit 9) (8) Subclock stop bit (4) WCL (2) WIF (3) WIE (3) Operation clock mode (9) (11) (11) Subclock Main clock (10) (1) Selects the interval (WS[1:0]) (In this example, 210/FCL-SUB is selected.
Chapter 23 Sub Oscillation Stabilisation Timer 5.Operation 5.2 Interval Interrupt (Clock Interrupt) Clock timer counting (4) 4000h (4) 2000h (3) (3) 0000h (2) Time (1) 213 (Bit12) WCL (4) (4) (2) WIF (2) WIE (2) (5) (6) (5) (6) (1) Selects the interval time. (WS[1:0]) (In this example, 213/FCL-SUB is selected.) (2) Sets the timer clear (WCL=“0”), flag clear (WIF=“0”) and interrupt request enable (WIE=“1”) by the software. (3) The timer counts up with the subclock (Source oscillation).
Chapter 23 Sub Oscillation Stabilisation Timer 5.Operation 5.3 Returning from the Stop Mode due to Interval Operation (Clock Interrupt) Clock timer counting 7FFFh 4000h (2) 0000h (3) 2 14 (Bit 13) (7) Interval time WCL (1) (10) WIF (8) (4) WIE (5) MCU state Main RUN SubRUN (6) STOP (9) SubRUN STOP SubRUN STOP SubRUN STOP SubRUN STOP SubRUN Oscillation stability wait time (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) The sub oscillation stabilisation timer is cleared by software.
Chapter 23 Sub Oscillation Stabilisation Timer 6.Setting 6. Setting Table 6-1 Settings Required for Using the Sub oscillation stabilisation timer Setting Setting the interval time Count clear Setting register Sub oscillation stabilisation timer control register (WPCRH) Setting method* Refer to 7.1. Refer to 7.4. *: Refer to the number for more information on the setting method.
Chapter 23 Sub Oscillation Stabilisation Timer 7.Q & A 7. Q & A 7.1 What are the types of interval time (wait time) and how are they selected? There are three types of interval time, and they are set with the interval selection bit (WPCRH.WS[1:0]). Interval selection bit (WS[1:0]) Interval (Wait time) Example FCL-SUB = 32.768kHz To set the interval time to 210/FCL-SUB Set the value to “00”. 31.25ms To set the interval time to 213/FCL-SUB Set the value to “01”. 0.
Chapter 23 Sub Oscillation Stabilisation Timer 7.Q & A 7.6 How is the interrupt enabled? The interrupt request enable and the interrupt request flag The interrupt enable is set with the interrupt request enable bit (WPCRH.WIE). Interrupt disable Interrupt enable Interrupt request enable bit (WIE) Set the value to “0” Set the value to “1” The interrupt request is cleared with the interrupt request bit (WPCRH.WIF). Interrupt request clear Interrupt request bit (WIF) Writes “0” 7.
Chapter 23 Sub Oscillation Stabilisation Timer 8.Caution 8. Caution • If the setting request (WIF=“1”) of the timer interrupt request flag and the writing timing where “0” is written to the flag by the software occur simultaneously, the flag is set to “1”. • If the interrupt request is enabled (WIE=“1”) after defeating a reset, and if the interval time is changed, be sure to simultaneously set “0” to the interrupt request enable flag (WIF) and the clear bit (WCL).
Chapter 23 Sub Oscillation Stabilisation Timer 8.
Chapter 24 Interrupt Control 1.Overview Chapter 24 Interrupt Control 1. Overview Interrupt control manages interrupt reception and arbitration. NMI Wakeup Priority judging circuit NMI processing Interrupt requests (peripheral function, INT instruction, and delayed interrupt) Interrupt priority judging circuit Interrupt level/ interrupt vector generator Level HLDREQ cancel request HALT To the CPU Vector number 2.
Chapter 24 Interrupt Control 3.Configuration 3.
Chapter 24 Interrupt Control 4.Registers 4. Registers 4.1 ICR: Interrupt Control Register The register that specifies the interrupt level of an interrupt request.
Chapter 24 Interrupt Control 4.
Chapter 24 Interrupt Control 4.
Chapter 24 Interrupt Control 4.Registers ICR (Interrupt Control Register) is a register in the interrupt controller, and it specifies the interrupt level for each interrupt request. ICR corresponds to each of interrupt request input. ICR is mapped to the I/O space. • ICR00 – ICR63 7 – 6 – 5 – 4 ICR4 3 ICR3 2 ICR2 1 ICR1 0 ICR0 – – – 1 1 1 1 1 RX/WX RX/WX RX/WX R/WX R/W R/W R/W R/W bit Initial value Attribute (About attributes, see “Meaning of Bit Attribute Symbols (Page No.10)”.
Chapter 24 Interrupt Control 4.Registers 4.2 Interrupt Vector Interrupt vector that corresponds to a vector number (#) with TBR register set to 0FFC00h (initial value): #00 #01 : Address : Address : Address ~ : Address FFF00h : Address ~ ~ ~ #143 FFFE0h ~ ~ #63 ~ ~ ~ #07 FFFBCh FFFB8h FFDC0h 32 bits • Set the address of each interruption handling routine to the corresponding vector.
Chapter 24 Interrupt Control 5.Operation 5. Operation The following section explains priority determination operation of interrupt control. The Flow of the Interrupt Process Interrupt cause generated The interrupt request flag is set to “1”. CPU processing Is the interrupt level higher than the interrupt mask level? NO Are interrupt requests enabled? NO (ICR) < (ILM) YES YES Priority determination The interrupt request is transmitted to the interrupt control circuit.
Chapter 24 Interrupt Control 6.Setting 6. Setting Table 6-1 Setting Required to Use Interrupts Setting Setting Registers Setting the interrupt level Clearing the interrupt request flags Enabling interrupt requests I flag setting Interrupt control registers (ICR00 to ICR63) See the corresponding chapter for each peripheral function. See the corresponding chapter for each peripheral function. CCR register Setting Procedure See 7.1 – – See 7.
Chapter 24 Interrupt Control 8.Caution 7.4 How can I set an I flag? −>In C: I flag is set to “1” (interrupt enable) by writing __EI();. I flag is set to “0” (interrupt disable) by writing __DI();. Two underscores 8. Caution Interrupt request flags are not cleared automatically. Make sure to clear them in the interrupt process. (They are usually cleared by writing “0” to the bit of the interrupt request flag, however, there are some exceptions depending on the type of peripheral functions.
Chapter 25 External Interrupt 1.Overview Chapter 25 External Interrupt 1. Overview External interrupt detects a signal input to an external interrupt input pin, and generates an interrupt request. Pins Edge detection circuit Interrupt requests 2.
Chapter 25 External Interrupt 3.Configuration 3. Configuration Figure 3-1 Configuration Diagram External interrupts 0 - 7 Detect level setting External interrupt request enable flag LB0, LB1, LB2, LB3, LB4, LB5, LB6, LB7, LA0 LA1 LA2 LA3 LA4 LA5 LA6 LA7 ELVR0 : bit 1-0, ELVR0 : bit 3-2, ELVR0 : bit 5-4, ELVR0 : bit 7-6, ELVR0 : bit 9-8, ELVR0 : bit 11-10, ELVR0 : bit 13-12, ELVR0 : bit 15-14, EN0, EN1, EN2, EN3, EN4, EN5, EN6, EN7 External interrupt request flag INT0/P24.0 INT1/P24.1 INT2/P24.
Chapter 25 External Interrupt 3.Configuration Figure 3-2 Configuration Diagram External interrupts 8 - 15 Detect level setting LB8, LA8 LB9, LA9 LB10, LA10 LB11, LA11 LB12, LA12 LB13, LA13 LB14, LA14 LB15, LA15 External interrupt request enable flag ELVR1 : bit 1-0, ELVR1 : bit 3-2, ELVR1 : bit 5-4, ELVR1 : bit 7-6, ELVR1 : bit 9-8, ELVR1 : bit 11-10, ELVR1 : bit 13-12, ELVR1 : bit 15-14 External interrupt request flag INT8/RX0/P23.0 INT9/RX1/P23.2 INT10/RX2/P23.4 INT11/RX3/P23.6 INT12/RX4/P22.
Chapter 25 External Interrupt 3.Configuration Figure 3-4 Register List Note: See “Chapter 24 Interrupt Control (Page No.311)” about ICR register and interrupt vectors.
Chapter 25 External Interrupt 4.Registers 4. Registers 4.1 ELVR: Interrupt Request Level Register The register that selects request detection of external interrupts.
Chapter 25 External Interrupt 4.Registers 4.2 EIRR: Interrupt Request Register Status bit of a request of an external interrupt. • EIRR0 (INT0-INT7): Address 030H (access: Byte, Half-word, Word) 7 6 5 4 3 2 1 0 ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0 0 0 0 0 0 0 0 R (RM1), W 0 R (RM1), W Initial value Attribute Bit R (RM1), W R (RM1), W R (RM1), W R (RM1), W R (RM1), W R (RM1), W Bit (About attributes, see “Meaning of Bit Attribute Symbols (Page No.10)”.
Chapter 25 External Interrupt 5.Operation 5. Operation Level detection (2) (1) INT (“H”) (“L”) (1) (2) (3) Valid edge Clear by software (4) Interrupt request (ER) (5) Edge detection Internal clock (CLKP divided by two) (2) INT (rising) (fallling) Required to maintain the level more than before and after the edge (3 x CLKP) (1) (1) (2) Valid edge (3) Interrupt requests (ER) (4) Clear by software (5) (1) External interrupt signal (INT) input (2) Detect interrupt signals (level/edge).
Chapter 25 External Interrupt 6.Setting 6. Setting Table 6-1 Setting Required in Order to Use External Interrupts Setting Setting Registers External interrupt request level setting register (ELVR0 - ELVR1) Data direction register (DDR22, DDR23, DDR24) Port function register (PFR22, PFR23, PFR24) External inputs →Inputs the signal to INT0 - INT15 pins. Setting of detect level Set INT pin as the input. External interrupt Setting Procedures* See 7.1 See 7.
Chapter 25 External Interrupt 7.Q & A 7.3 What interrupt registers are used? Setting of interrupt vectors of external interrupts, and interrupt levels The relationship among external interrupt numbers, interrupt levels, and vectors is shown in the table below. See “Chapter 24 Interrupt Control (Page No.311)” about the details of interrupt levels and interrupt vectors.
Chapter 25 External Interrupt 7.Q & A 7.5 How do I enable, disable, and clear interrupts? Enable flag for interrupt requests, interrupt request flag Use interrupt enabling bits (ENIR0.ENx. x = 0-7) and (ENIR1.ENx. x = 8-15) to enable interrupts. To disable interrupt requests To enable interrupt requests Interrupt enabling bit (En [n = 0-15]) Sets to “0” Sets to “1” Use interrupt request bits (EIRR0.ERx. x = 0-7) and (EIRR1.ERx. x = 8-15) to clear interrupt requests.
Chapter 25 External Interrupt 8.Caution 8. Caution • When the request input is a level (LAn, LBn = “00” or “01”) and when the INT pin input is the set active level, the corresponding bit (ERn) will be re-set to “1” even if the external interrupt request bit (ERn) is set to “0”.
Chapter 25 External Interrupt 8.
Chapter 26 DMA Controller 1.Overview of the DMA Controller (DMAC) Chapter 26 DMA Controller 1. Overview of the DMA Controller (DMAC) The DMA controller (DMAC) is a module that implements DMA (Direct Memory Access) transfer on FR family devices. When this module is used to control DMA transfer, various kinds of data can be transferred at high speed by bypassing the CPU, enhancing system performance.
Chapter 26 DMA Controller 1.Overview of the DMA Controller (DMAC) ■ Block Diagram Figure 1-1"Block Diagram of the DMA Controller (DMAC)" is a block diagram of the DMA controller (DMAC).
Chapter 26 DMA Controller 2.DMA Controller (DMAC) Registers 2. DMA Controller (DMAC) Registers This section describes the configuration and functions of the registers used by the DMA controller (DMAC). ■ DMA Controller (DMAC) registers Figure 2-1"DMA Controller (DMAC) Registers" shows the registers of the DMA controller (DMAC). Figure 2-1 DMA Controller (DMAC) Registers (bit) 31 24 23 16 15 08 07 00 ch.0 Control/status register A (DMACA0) ch.0 Control/status register B (DMACB0) ch.
Chapter 26 DMA Controller 2.DMA Controller (DMAC) Registers If the bit is set while DMA transfer start is disabled (when DMAE of DMACR=0, or DENB of DMACA=0), the setting takes effect when start is enabled. If the bit is set while DMA transfer is temporarily stopped (DMAH[3:0] of DMACR not equal to 0000B or PAUS of DMACA=1), the setting takes effect when temporary stopping is canceled. 2.
Chapter 26 DMA Controller 2.DMA Controller (DMAC) Registers [Bit 30] PAUS (PAUSe)*: Temporary stop instruction This bit temporarily stops DMA transfer on the corresponding channel. If this bit is set, DMA transfer is not performed before this bit is cleared (While DMA is stopped, the DSS bits are 1xxB. If this bit is set before starting, DMA transfer continues to be temporarily stopped.
Chapter 26 DMA Controller 2.DMA Controller (DMAC) Registers [Bits 28 to 24] IS4 to 0 (Input Select)*: Transfer source selection These bits select the source of a transfer request note that the software transfer request by the STRG bit function is always valid regardless of the setting of these bits. As listed in Table 2-1 "Settings for Transfer Request Sources".
Chapter 26 DMA Controller 2.DMA Controller (DMAC) Registers Notes: • If DMA start resulting from an interrupt from a peripheral function is set (IS=1xxxxB), disable interrupts from the selected peripheral function with the ICR register. • If demand transfer mode is selected, only IS[4:0]=01110B, 01111B can be set. Starting by other sources is disabled. • External request input is valid only for CH0, 1, and 2. External request input cannot be selected for CH2, CH3 and 4.
Chapter 26 DMA Controller 2.
Chapter 26 DMA Controller 2.
Chapter 26 DMA Controller 2.
Chapter 26 DMA Controller 2.DMA Controller (DMAC) Registers completed. DTC XXXXB Function Transfer count for the corresponding channel When DMA transfer is started, data in this register is stored in the counter buffer of the DMA-dedicated transfer counter and is decremented by 1 (subtraction) after each transfer unit. When DMA transfer is completed, the contents of the counter buffer are written back to this register and then DMA ends. Thus, the transfer count value during DMA operation cannot be read.
Chapter 26 DMA Controller 2.DMA Controller (DMAC) Registers memory address. Table 2-3 Settings for the Transfer Types TYPE Function 00B 2-cycle transfer (initial value) 01B Fly-by: Memory --> I/O transfer 10B Fly-by: I/O --> memory transfer 11B Setting disabled • When reset: Initialized to 00B. • These bits are readable and writable.
Chapter 26 DMA Controller 2.DMA Controller (DMAC) Registers [Bits 29, 28] MOD (MODe)*: Transfer mode setting These bits are the transfer mode setting bits and set the operating mode of the corresponding channel. Table 2-4 Settings for Transfer Modes MOD Function 00B Block/step transfer mode (initial value) 01B Burst transfer mode 10B Demand transfer mode 11B Setting disabled • When reset: Initialized to 00B. • These bits are readable and writable.
Chapter 26 DMA Controller 2.DMA Controller (DMAC) Registers [Bit 25] SADM (Source-ADdr. Count-Mode select)*: Transfer source address count mode specification This bit specifies the address processing of the transfer source address of the corresponding channel in each transfer operation. An address increment is added or an address decrement is subtracted after each transfer operation according to the specified transfer source address count width (SASZ).
Chapter 26 DMA Controller 2.DMA Controller (DMAC) Registers [Bit 23] DTCR (DTC-reg. Reload)*: Transfer count register reload specification This bit controls reloading of the transfer count register for the corresponding channel. If reload operation is enabled by this bit, the count register value is restored to its initial value after the transfer is completed then DMAC stops and then waiting starts for new transfer requests (an activation request by STRG or IS setting).
Chapter 26 DMA Controller 2.DMA Controller (DMAC) Registers [Bit 21] DADR (Dest.-ADdr.-reg. Reload)*: Transfer destination address register reload specification This bit controls reloading of the transfer destination address register for the corresponding channel. If this bit enables reloading, the transfer destination address register value is restored to its initial value after the transfer is completed. The details of other functions are the same as those described for Bit22 (SADR).
Chapter 26 DMA Controller 2.DMA Controller (DMAC) Registers [Bits 18 to 16] DSS2 to 0 (DMA Stop Status)*: Transfer stop source indication These bits indicate a code (end code) of 3 bits that indicates the source of stopping or termination of DMA transfer on the corresponding channel. For a list of end codes, see Table 2-6"End Codes".
Chapter 26 DMA Controller 2.DMA Controller (DMAC) Registers [Bits 7 to 0] DASZ (Des Addr count SiZe)*: Transfer destination address count size specification These bits specify the increment or decrement width for the transfer destination address (DMADA) of the corresponding channel in each transfer operation. The value set by these bits becomes the address increment/decrement for each transfer unit.
Chapter 26 DMA Controller 2.DMA Controller (DMAC) Registers [Bits 31 to 0] DMADA (DMA Destination Addr)*: Transfer destination address setting These bits set the transfer destination address. If DMA transfer is activated, data in this register is stored in the counter buffer of the DMA-dedicated address counter and then the address is calculated according to the settings for the transfer operation.
Chapter 26 DMA Controller 2.DMA Controller (DMAC) Registers DMA operation can be forced to stop by writing 0 to this bit. However, be sure to force stopping (0 write) only after temporarily stopping DMA using the DMAH[3:0] bits [Bit27 to 24 of DMACR]. If forced stopping is carried out without first temporarily stopping DMA, DMA stops, but the transfer data cannot be guaranteed. Check whether DMA is stopped using the DSS[2:0] bits [Bit18 to 16 of DMACB].
Chapter 26 DMA Controller 2.DMA Controller (DMAC) Registers ■ Pin Function of the DACK, and DEOP, and DREQ pins To use the DACK, DEOP, or DREQ pins for external transfer, a switch must be made from the port function to the DMA pin function. To make the switch, set the PFR register.
Chapter 26 DMA Controller 3.DMA Controller (DMAC) Operation 3. DMA Controller (DMAC) Operation A DMA controller (DMAC) is built into all FR family devices. The FR family DMAC is a multi-functional DMAC that controls data transfer at high speed without the use of CPU instructions. This section describes the operation of the DMAC. ■ Principal Operations • Functions can be set for each transfer channel independently.
Chapter 26 DMA Controller 3.DMA Controller (DMAC) Operation ● Fly-by transfer (I/O --> memory) The DMA controller operates using a write operation as its unit of operation. Otherwise, operation is the same as fly-by transfer (memory --> I/O) operation. Access areas used for MB91460 series fly-by transfer must be external areas. ■ Transfer Address The following types of addressing are available and can be set independently for each channel transfer source and transfer destination.
Chapter 26 DMA Controller 3.DMA Controller (DMAC) Operation • End of the specified transfer count (DMACA:BLK[3:0] x DMACA:DTC[15:0]) => Normal end • A transfer stop request from a peripheral circuit or the external pin (DSTP) occurred => Error • An address error occurred => Error • A reset occurred => Reset The transfer stop source is indicated (DSS) and the transfer end interrupt or error interrupt for the end source is generated. 3.
Chapter 26 DMA Controller 3.DMA Controller (DMAC) Operation always be caused. If a software request occurs together with a start (transfer enable) request, the transfer is started by immediate output of a DMA transfer request to the bus controller. 3.2 Transfer Sequence The transfer type and the transfer mode that determine, for example, the operation sequence after DMA transfer has started can be set independently for each channel (Settings for TYPE[1:0] and MOD[1:0] of DMACB).
Chapter 26 DMA Controller 3.
Chapter 26 DMA Controller 3.DMA Controller (DMAC) Operation Table 3-3 Specifiable transfer addresses (demand transfer 2-cycle transfer) Transfer source address Direction Transfer destination addressing External area External area External area Built-in IO External area Built-in RAM Built-in IO External area Built-in RAM External area Note: For a demand transfer, be sure to set an external area address for the transfer source or transfer destination or both.
Chapter 26 DMA Controller 3.DMA Controller (DMAC) Operation • If a transfer request for another channel with a higher priority is received during transfer, the channel is switched after the transfer is stopped and then restarted. Priority in a step transfer is valid only if transfer requests occur simultaneously. [Block transfer] If any value other than 1 is specified as the block size, a block transfer sequence is generated.
Chapter 26 DMA Controller 3.DMA Controller (DMAC) Operation ● Transfer count register reloading After transfer is performed the specified number of times, the initial value is set in the transfer count register again and waiting for a start request starts. Set this type of reloading when the entire transfer sequence is to be performed repeatedly. If reload is not specified, the count register value remains 0 after the transfer is performed the specified number of times and no further transfer is performed.
Chapter 26 DMA Controller 3.DMA Controller (DMAC) Operation ■ Features of the Address Register This register has the maximum 32-bit length. With 32-bit length, all space in the memory map can be accessed. ■ Function of the Address Register • The address register is read in each access operation and the read value is sent to the address bus. • At the same time, the address for the next access is calculated by the address counter and the address register is updated using the calculated address.
Chapter 26 DMA Controller 3.DMA Controller (DMAC) Operation ■ Transfer Count Control Set the transfer count value in the transfer count register (DTC of DMACA). The register value is stored in the temporary storage buffer when the transfer starts and is decremented by the transfer counter. When the counter value becomes 0, end of transfer end for the specified count is detected, and the transfer on the channel is stopped or waiting for a restart request starts (when reload is specified).
Chapter 26 DMA Controller 3.DMA Controller (DMAC) Operation Note: • Since the register has only four bits, this function cannot be used for multiple interrupts exceeding 15 levels. • Be sure to assign the priority of the DMA tasks at a level that is at least 15 levels higher than other interrupt levels. 3.8 Hold Arbitration When a device is operating in external bus extended mode, an external hold function can be used.
Chapter 26 DMA Controller 3.DMA Controller (DMAC) Operation If edge detection is selected for the external pin start source and a transfer request is detected, the request is retained within DMAC until the clear conditions are met (when the external pin start source is selected for block, step, or burst transfer). If level detection or peripheral interrupt start is selected for the external pin start source, DMAC continues the transfer until all transfer requests are cleared.
Chapter 26 DMA Controller 3.DMA Controller (DMAC) Operation ● Disabling all channels If the operation of all channels is disabled with the DMA operation enable bit DMAE, all DMAC operations, including operations on active channels, are stopped. Then, even if the operation of all channels is enabled again, no transfer is performed unless a channel is restarted. In this case, no interrupt whatever occurs.
Chapter 26 DMA Controller 3.DMA Controller (DMAC) Operation ■ Occurrence of an Address Error If inappropriate addressing, as shown below in parenthesis, occurs in an addressing mode, an address error is detected (if an overflow or underflow occurs in the address counter when a 32-bit address is specified). If an address error is detected, "An address error occurred" is displayed as the end code and transfer on the corresponding channel is stopped. 3.
Chapter 26 DMA Controller 3.DMA Controller (DMAC) Operation 3.11 Channel Selection and Control Up to five channels can be simultaneously set as transfer channels. In general, an independent function can be set for each channel. ■ Priority Among Channels Since DMA transfer is possible only on one channel at a time, priority must be set for the channels. Two modes, fixed and rotation, are provided as the priority settings and can be selected for each channel group (described later).
Chapter 26 DMA Controller 3.DMA Controller (DMAC) Operation ■ Channel Group The order of priority is set as shown in the following table. MODE Priority Remarks Fixed ch0 > ch1 − ch0 > ch1 Rotation ch0 < ch1 The initial state is the top row. If transfer occurs for the top row, the priority is reversed. 3.12 Supplement on External Pin and Internal Operation Timing This section provides supplementary information about external pins and internal operation timing.
Chapter 26 DMA Controller 3.
Chapter 26 DMA Controller 3.DMA Controller (DMAC) Operation Even if DREQ is reasserted earlier, it is ignored because the transfer has not been completed. If no transfer requests for other channels occur, transfer over the same channel is restarted by reasserting DREQ when the DACK pin output is asserted. ■ Timing of DACK Pin Output The DACK output of this DMAC indicates that transfer with respect to an accepted transfer request is being performed.
Chapter 26 DMA Controller 3.DMA Controller (DMAC) Operation ■ AC Characteristics of DMAC DREQ pin input, DACK pin output, and DEOP pin output are provided as the external pins related to the DMAC,. Output timing is synchronized with external bus access (refer to the AC standard for the DMAC).
Chapter 26 DMA Controller 4.Operation Flowcharts 4. Operation Flowcharts This section contains operation flowcharts for the following transfer modes: • Block transfer • Burst transfer • Demand transfer ■ Block Transfer Figure 4-1"Operation Flowchart for Block Transfer" shows the flowchart for block transfer.
Chapter 26 DMA Controller 4.
Chapter 26 DMA Controller 4.
Chapter 26 DMA Controller 5.Data Bus 5. Data Bus This section shows the flow of data during 2-cycle transfer and fly-by transfer. ■ Flow of Data During 2-Cycle Transfer Figure 14.5-1 shows examples of six types of transfer during 2-cycle transfer.
Chapter 26 DMA Controller 5.
Chapter 26 DMA Controller 5.
Chapter 26 DMA Controller 6.DMA External Interface 6. DMA External Interface This section provides operation timing charts for the DMA external interface. ■ DMA External Interface Pins DMA channels 0-3 have the following DMA-dedicated pins (DREQ, DACK, and DEOP): • DREQ: DMA transfer request input pin for demand transfer. A transfer is requested with an input. • DACK: This pin becomes active (L output) when DMA accesses an external area via the external interface.
Chapter 26 DMA Controller 6.DMA External Interface ■ Timing of Demand Transfer For demand transfer, set the DMA start source to level detection. Although there is no rule for starting, synchronize with RD/WRn of the DMA transfer when stopping a transfer. The sense timing is the rise of MCLK in the final external access. Figure 6-2"Timing Chart for Demand Transfer" shows the timing chart for demand transfer.
Chapter 26 DMA Controller 6.DMA External Interface Figure 6-3 Timing Chart in 2-Cycle Transfer Mode RD DQMU/L WR/WRn DACK (AKxx=111 B ) * DACK (AKxx=001 B ) * DACK (AKxx=010 B ) * Same timing as the chip select 2-cycle transfer setting disabled DACK (AKxx=011 B ) * DACK (AKxx=100 B ) * DACK (AKxx=101 B ) * DACK (AKxx=110 B ) * * : AKxx is the setting value in the PFR register that corresponds to the DMA channel.
Chapter 26 DMA Controller 6.
Chapter 27 Delayed Interrupt 1.Overview Chapter 27 Delayed Interrupt 1. Overview The delayed interrupt, or the delayed interrupt module is used to generate an interrupt used for task switching. Delay interrupt control circuit Software request Interrupt request (#63) 2. Features • Type: Interrupt request bit (There is no interrupt request enable bit) • Quantity: 1 • Other: • The software generates/releases interrupt request. • Real time OS uses the delayed interrupt for task switching. 3.
Chapter 27 Delayed Interrupt 4.Register 4. Register 4.1 DICR: Delayed Interrupt Control Register This register controls to generate/clear the delayed interrupt. • DICR: Address 0038h (Access: Byte) 7 – – 6 – – 5 – – 4 – – RX/WX RX/WX RX/WX RX/WX 3 – – RX/ WX 2 – – 1 – – 0 DLYI 0 bit Initial value RX/WX RX/WX R/W Attribute (Refer to “Meaning of Bit Attribute Symbols (Page No.10)” for the attributes.) • Bit7-1: Undefined: Writing does not affect operation. The read value is undefined.
Chapter 27 Delayed Interrupt 6.Setting 6. Setting Table Setting required for the delayed interrupt generation/clear Table 6-1 Setting required for the delay interrupt generation/clear Setting Vector for delay interrupt Delayed interrupt setting. Generating interrupt request/Releasing interrupt request Setting register Refer to “Chapter 24 Interrupt Control (Page No.311)” Delayed interrupt control register (DICR) Setting method* Refer to 7.1 Refer to 7.2 *: Refer to the number for the setting method. 7.
Chapter 27 Delayed Interrupt 8.
Chapter 28 Bit Search 1.Overview Chapter 28 Bit Search 1. Overview The bit search module is used to detect 0, 1 or changing position for data written in specific registers. 0-position register 1-position register Detection circuit (0-position, 1-pos. and changing position) Result register Changing-pos. register 2. Features • Function: Detects the first changing position by scanning data written in data register from MSB to LSB. • 0 detection Detects the first ‘0’ changing position.
Chapter 28 Bit Search 3.Configuration 3.
Chapter 28 Bit Search 4.Register 4. Register 4.1 BSD0: 0 Detection Register / BSD1:1 Detection Register / BSDC: Changing position Detection Data Register This is a register for setting the bit search detection data.
Chapter 28 Bit Search 4.Register 4.2 BSRR: Detection Result Register This register is used to read a bit search result. • BSRR: Address 03FCH (Access: Word) 31 0 bit BSRR Indefinite R Initial value Attribute (For the attributes, refer to “Meaning of Bit Attribute Symbols (Page No.10)”.) • Detection result for data written in the 0 detection register BSD0, the 1-detection register BSD1 and the changing-position-detection register BSDC can be read. Data last written can be read.
Chapter 28 Bit Search 5.Operation 5. Operation 5.1 Zero detection Bit position from MSB Data 11111111111 111 11 2 0123456 789 ABCDEF0123456789AB CDEF 0 1111111 111 000 000 0000000000 000 000 Scan >>>>>>>>>> 0 Detection result AH (10 Decimal) (1) Bit position from MSB (2) Written data (Starts to search once data is written.) (3) Detects “0” by scanning from MSB.
Chapter 28 Bit Search 5.Operation 5.3 Changing Position Detection 11111111111 11 111 2 0123456789 AB CDEF0123456789ABCDEF 0 Bit position from MSB 0000000000 00 000 111000000000 00 000 Data >>>>>>>>>>>>>>>* Scan Detection result F H (15Decimal) (1) Bit position from MSB (2) Written data (Detection starts once data is written.) (3) Detects the changing position by scanning from MSB.
Chapter 28 Bit Search 6.Setting 6. Setting Table 6-1 Settings Required for “Zero” Position Detection Setting Data write & scan start Converted value read Setting register “Zero” position detection data register (BSD0) Detection result register (BSRR) Setting method * Refer to 7.1. Refer to 7.2. *: For detailed description contents, refer to the reference destination number.
Chapter 28 Bit Search 7.Q & A 7. Q & A 7.1 How is data written? Writes data with the detection data registers (BSD0, BSD1, BSDC). Operation mode “Zero” position detection write “One” position detection write Changing position detection write Detection data register Writes data in (BSD0) Writes data in (BSD1) Writes data in (BSDC) 7.2 How is scanning started? Scanning is started once data is written in the detection data registers (BSD0, BSD1, BSDC). 7.
Chapter 28 Bit Search 8.Caution 8. Caution The following are the remarks on using the bit search module. • The macros are for REALOS(OS), and the user cannot use them when using REALOS. • If the relevant detection is not found, a detection result of 32(decimal), 10(hexadecimal) or 10000(binary) is returned. • A value of “0” is not returned for the changing position detection. • The data registers (0-detection/1-detection/ changing-position-detection) is a write-only, and accessed by word.
Chapter 28 Bit Search 8.
Chapter 29 MPU / EDSU 1.Overview Chapter 29 MPU / EDSU 1. Overview Memory Protection Unit (MPU) and Embedded Debug Support Unit (EDSU) for MB91460 series. Remark: The MPU/EDSU module features a clock disable function. For enabling the MPU/EDSU module it is necessary to set the EDSUEN bit in the CSCFG register. See chapter “CSCFG: Clock Source Configuration Register (Page No.196)” for further information. The features are scalable in units of ’Comparator Groups’.
Chapter 29 MPU / EDSU 2.Features 2. Features One Comparator Group offers up to 4 Breakpoints. One Group consists of two full-featured range comparators with the option to use two point registers as mask information. The following features could be partially mixed-up: 4 Instruction Address Breakpoints Up to 4 instruction address breakpoints can be defined. Two instruction breakpoints can be masked. The other two registers can operate as mask registers then.
Chapter 29 MPU / EDSU 3.Break Functions 3. Break Functions 3.1 Instruction address break The instruction address point break is the most basic break that occurs when an instruction is fetched at the address specified by the break address data registers BAD[3:0]. Setting the CTC[1:0] bits of the control register BCR0 to ’00’ provides this mode. The bits EP[3:0] in BCR0 enable the break points. Up to 4 instruction breakpoints from channels 0 to 3 can be set.
Chapter 29 MPU / EDSU 3.Break Functions Break occurs at 0x02345200 to 0x02345300,or at 0x12345200 to 0x12345300,or at 0x22345200 to 0x22345300, etc. The resulting setting of the BD[1:0] status bits indicates the point, respective the area in which the break has occured.
Chapter 29 MPU / EDSU 3.Break Functions Example: CTC 01 Type: Operand Address Break EP0 1 Enable break point on BAD0 EP1 1 Enable break point on BAD1 ER0 1 Enable address range function on BAD0, BAD1 EM0 1 Enable address mask function on BAD0, BAD1 BAD0 0x12345200 Set lower break address BAD1 0x12345300 Set upper break address BAD2 0xF0000000 Set break mask Break occurs at 0x02345200 to 0x02345300,or at 0x12345200 to 0x12345300,or at 0x22345200 to 0x22345300, etc.
Chapter 29 MPU / EDSU 3.Break Functions Table 3-3 Operand size and operand address relations Access data length 32 bit Access address Address set in BOA0, BOA1 4n + 0 4n + 1 4n + 2 4n + 3 4n + 0 Hit Hit Hit Hit 4n + 1 Hit Hit Hit Hit 4n + 2 Hit Hit Hit Hit 4n + 3 Hit Hit Hit Hit In Operand address break mode the Operand Address, causing the break is captured in the BOAC register.
Chapter 29 MPU / EDSU 3.Break Functions 2) The EDSU data break does not always occur immediately after completion of execution of the instruction causing the break event. 3) Please see also information at chapter 3.
Chapter 29 MPU / EDSU 3.Break Functions On break both BD0 and BD2, respective BD1 and BD3 are set. They have to be reset by software in the operand break exception routine.
Chapter 29 MPU / EDSU 3.Break Functions Permissions can be set for the comparator channel CMP1 and CMP0 separately, indicated by the symbol index.
Chapter 29 MPU / EDSU 3.
Chapter 29 MPU / EDSU 4.Registers 4. Registers 4.1 List of EDSU Registers Table 4-1 EDSU Registers Summary Address Register +0 +1 Block +2 F000H BCTRL [R/W] -------- -------- 11111100 00000000 F004H BSTAT [R/W0]1 -------- -----000 00000000 10--0000 F008H BIAC [R] 00000000 00000000 00000000 00000000 F00CH BOAC [R] 00000000 00000000 00000000 00000000 F010H BIRQ [R/W] 00000000 00000000 00000000 00000000 F014H...
Chapter 29 MPU / EDSU 4.
Chapter 29 MPU / EDSU 4.
Chapter 29 MPU / EDSU 4.Registers 4.2 Explanations of Registers ● EDSU Control Register (BCTRL) EDSU Control Register byte 2 Address : F002H 15 14 13 12 11 10 9 8 SR SW SX UR UW UX FCPU FDMA ⇐ Bit no. Read/write ⇒ (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (1) (1) (1) (1) (1) (1) (0) (0) Default value⇒ EDSU Control Register byte 3 Address : F003H Read/write ⇒ Default value⇒ 7 6 EEMM PFD 5 4 SINT1 SINT0 3 2 EINT1 EINT0 1 0 ⇐ Bit no.
Chapter 29 MPU / EDSU 4.
Chapter 29 MPU / EDSU 4.Registers 1 Enable emulation mode If EEMM is set to ’1’ then the emulation mode is entered during Step Trace Mode and EDSU exceptions Instruction Break, Operand Break and Tool NMI. During emulation mode the Watchdog Timer (WDT) is disabled. EDSU triggered emulation mode is left with the RETI instruction. Set to ’0’ disables emulation mode function. The WDT is not stopped during Step Trace and EDSU exceptions.
Chapter 29 MPU / EDSU 4.Registers BIT[3]: EINT1 - Enable extended INTerrupt 1 0 Disable extended interrupt source 1 (default) 1 Enable extended interrupt source 1 If EINT1 is set to ’1’ then a Tool NMI will be generated on an extended interrupt event at source channel 1. Set to ’0’ disables this function. Remark: EINT1 interrupt source is not available for the MB91460 series.
Chapter 29 MPU / EDSU 4.
Chapter 29 MPU / EDSU 4.
Chapter 29 MPU / EDSU 4.Registers BIT[3]: INT1 - INTerrupt on extended source 1 0 Interrupt on extended source channel 1 not detected (default) 1 Interrupt on extended source channel 1 detected INT1 reflects the status of the extended interrupt source channel 1. It is set to ’1’ if a high level on the extended interrupt signal line has been occured. The status of ’1’ is stored until cleared by software. Writing ’0’ resets the INT1 bit to ’0’. Writing ’1’ to this bit is ignored.
Chapter 29 MPU / EDSU 4.Registers ● EDSU Instruction Address Capture Register (BIAC) BIAC Address +0 00000000 F008H [R] +1 +2 00000000 00000000 +3 00000000 This register captures the address of the instruction (IA), which has caused the protection violation or the operand/ data value break. This register could be read only.
Chapter 29 MPU / EDSU 4.Registers • operand address break, • data value break, • combined operand address and data value break and • memory protection violation. Writing ’0’ resets the BD[31:0] bits to ’0’. Writing ’1’ to these bits is ignored. On a Read Modify Write instruction all BD bits are read as ’1’.
Chapter 29 MPU / EDSU 4.Registers ● EDSU Channel Configuration Register (BCR0...BCR7) EDSU Ch. Config Register 0, byte 0 Address : F020H Read/write ⇒ Default value⇒ EDSU Ch. Config Register 0, byte 1 Address : F021H Read/write ⇒ Default value⇒ EDSU Ch. Config Register 0, byte 2 Address : F022H 31 30 29 28 27 26 25 24 - - - - - - - - (-) (X) (-) (X) (-) (X) (-) (X) (-) (X) (-) (X) (-) (X) (-) (X) 23 22 21 20 19 18 17 16 SRX1 SW1 SRX0 SW0 URX1 UW1 URX0 UW0 ⇐ Bit no.
Chapter 29 MPU / EDSU 4.
Chapter 29 MPU / EDSU 4.Registers • CTC=2: IA range 0 defines execute permissions and OA range 1 defines read/write permissions. Data value (DT) detection by setting CTC=3 is not possible to use in MPU mode. Permission configurations exist for read, write and execute for two CPU modes, the super visor mode and the user mode. Super visor permissions are valid for SV=1 and user permissions are valid for SV=0.
Chapter 29 MPU / EDSU 4.
Chapter 29 MPU / EDSU 4.Registers 1 The group of channels operates in memory protection mode Some restrictions apply with the setting of the MPE bit.
Chapter 29 MPU / EDSU 4.Registers The COMB bit set to ’1’ causes the IA comparator CMP0 to use the same BADx point definitions as the OA comparator CMP1. Point 3 and Point 2 define the address range for both comparators CMP0 and CMP1. This has the effect that the entry of Point 0/Mask 0 is not allocated for the Point set-up and could be used for masking either one or both comparators. The Point 1 entry is not useable in this case.
Chapter 29 MPU / EDSU 4.Registers Datasize OBS1 1 OBS0 1 Access type OBT1 All (Byte, Hword, Word) 1 OBT0 1 All (Read, RMW, Write) The operand break size register OBS configures the datasize and the operand break type register OBT configures the access type if the channel is configured to operand address break or data value break detection. Setting to ’all’ in datasize will cause detection of byte, halfword and word data sizes.
Chapter 29 MPU / EDSU 4.Registers The input value and the point value is masked if the mask function is enabled by EM0. On a compare match a break exception will be executed. CTC and MPE control the selection of the input value and the type of the break exception.
Chapter 29 MPU / EDSU 4.Registers The selection of the appropriate BADx register (point 0 or 2) for the mask value depends on EP0 and ER0. If at least one of both bits are enabled, the mask usage switches to point 2 due to the allocation of point 0. Otherwise the default mask stored in point 0 applies for CMP0. If MPE=1 and COMB=1 the mask is taken from point 0, regardless of the setting of EP0 and ER0.
Chapter 29 MPU / EDSU 4.Registers BAD1 (BAD5 BAD9, ..., BAD29) Address F084H +0 XXXXXXXX +1 XXXXXXXX [R/W] +2 XXXXXXXX +3 XXXXXXXX This register sets the 32 bit comparison value for break point 1 of CMP0. In range mode (set with ER0) the register value of BAD1 functions as upper address limit. In the special case of MPE=1 and COMB=1 BAD1 is not used for the point definition. CMP0 gets its point configuration then from BAD3. BAD2 (BAD6, BAD10, ...
0xF0FC BAD31 0xF0F8 BAD30 0xF0F4 BAD29 0xF0F0 BAD28 ... 0xF08C BAD3 0xF088 BAD2 0xF084 BAD1 0xF080 BAD0 0xF03C BCR7 ...
Chapter 29 MPU / EDSU 5.
Chapter 30 I/O Ports 1.I/O Ports Functions Chapter 30 I/O Ports 1. I/O Ports Functions For enabling the resource functions, please refer to section ........
Chapter 30 I/O Ports 1.I/O Ports Functions Pin Name I/O Signal Circuit Type P00_3 P00_3 TP04_0 Function General purpose I/O. This function is enabled in the single-chip mode or by setting the corresponding PFR to ‘0’. D27 I/O pin for bit 27 of the external data bus. This function is enabled when the external bus is enabled. P00_2 General purpose I/O. This function is enabled in the single-chip mode or by setting the corresponding PFR to ‘0’.
Chapter 30 I/O Ports 1.I/O Ports Functions Pin Name I/O Signal Circuit Type P01_0 P01_0 TP04_0 D16 Function General purpose I/O. This function is enabled in the single-chip mode or by setting the corresponding PFR to ‘0’. I/O pin for bit 16 of the external data bus. This function is enabled when the external bus is enabled. Port 02 P02_7 P02_7 TP04_0 General purpose I/O. This function is enabled in the single-chip mode or by setting the corresponding PFR to ‘0’.
Chapter 30 I/O Ports 1.I/O Ports Functions Pin Name I/O Signal Circuit Type P03_5 P03_5 TP04_0 Function General purpose I/O. This function is enabled in the single-chip mode or by setting the corresponding PFR to ‘0’. D5 I/O pin for bit 5 of the external data bus. This function is enabled when the external bus is enabled. P03_4 General purpose I/O. This function is enabled in the single-chip mode or by setting the corresponding PFR to ‘0’.
Chapter 30 I/O Ports 1.I/O Ports Functions Pin Name I/O Signal Circuit Type P04_2 P04_2 TP04_0 Function General purpose I/O. This function is enabled in the single-chip mode or by setting the corresponding PFR to ‘0’. A26 I/O pin for bit 26 of the external address bus. This function is enabled when the external bus is enabled. P04_1 General purpose I/O. This function is enabled in the single-chip mode or by setting the corresponding PFR to ‘0’.
Chapter 30 I/O Ports 1.I/O Ports Functions Pin Name I/O Signal Circuit Type P06_7 P06_7 TP04_0 Function General purpose I/O. This function is enabled in the single-chip mode or by setting the corresponding PFR to ‘0’. A15 I/O pin for bit 15 of the external address bus. This function is enabled when the external bus is enabled. P06_6 General purpose I/O. This function is enabled in the single-chip mode or by setting the corresponding PFR to ‘0’.
Chapter 30 I/O Ports 1.I/O Ports Functions Pin Name I/O Signal Circuit Type P07_4 P07_4 TP04_0 A4 P07_3 P07_3 TP04_0 A3 P07_2 P07_2 TP04_0 A2 P07_1 P07_1 TP04_0 A1 P07_0 P07_0 TP04_0 A0 Function General purpose I/O. This function is enabled in the single-chip mode or by setting the corresponding PFR to ‘0’. I/O pin for bit 4 of the external address bus. This function is enabled when the external bus is enabled. General purpose I/O.
Chapter 30 I/O Ports 1.I/O Ports Functions Pin Name I/O Signal Circuit Type P08_1 P08_1 TP04_0 Function General purpose I/O. This function is enabled in the single-chip mode or by setting the corresponding PFR to ‘0’. WRX1 Output pin for external bus write strobe. This function is enabled when the external bus is enabled. P08_0 General purpose I/O. This function is enabled in the single-chip mode or by setting the corresponding PFR to ‘0’.
Chapter 30 I/O Ports 1.I/O Ports Functions Pin Name I/O Signal Circuit Type P10_6 P10_6 P10_5 P10_4 TP04_0 General purpose I/O. This function is enabled in the single-chip mode or by setting the corresponding PFR to ‘0’. MCLKE Output pin for external bus memory clock enable. This function is enabled when the external bus is enabled. P10_5 General purpose I/O. This function is enabled in the single-chip mode or by setting the corresponding PFR to ‘0’.
Chapter 30 I/O Ports 1.I/O Ports Functions Pin Name P11_0 I/O Signal P11_0 IORDX Circuit Type TP04_0 Function General purpose I/O. Output pin for DMA I/O to memory fly-by transfer. Port 12 P12_7 P12_7 DEOP3 TP04_0 P12_6 P12_6 DEOTX3 P12_4 P12_3 P12_5 DACKX3 P12_4 DREQ3 P12_3 DEOP2 DEOTX2 TP04_0 TP04_0 TP04_0 P12_0 P12_1 DACKX2 P12_0 DREQ2 General purpose I/O. Output pin for DMA transfer request acknowledgement. General purpose I/O. Input pin for DMA transfer request. General purpose I/O.
Chapter 30 I/O Ports 1.I/O Ports Functions Pin Name I/O Signal Circuit Type P14_7 P14_7 ICU7 TIN7 General purpose I/O. TP00_0 TTG15/7 ICU6 TIN6 TP00_0 TIN5 TP00_0 TIN4 TP00_0 TIN3 TP00_0 TIN2 TP00_0 P14_0 TIN1 Data sample input pin for input capture ICU 2. Event input pin for the reload timer RLT 2. Event input pin for the programmable pulse generators PPG 10 and PPG 2. P14_1 ICU1 Event input pin for the reload timer RLT 3. General purpose I/O.
Chapter 30 I/O Ports 1.I/O Ports Functions Pin Name I/O Signal Circuit Type P15_5 P15_5 P15_4 P15_3 OCU5 General purpose I/O. TP00_0 Output pin for the reload timer RLT 5. P15_4 General purpose I/O. OCU4 TP00_0 P15_0 Waveform output pin for output compare OCU 4. TOT4 Output pin for the reload timer RLT 4. P15_3 General purpose I/O. OCU3 TP00_0 OCU2 Waveform output pin for output compare OCU 3. Output pin for the reload timer RLT 3.
Chapter 30 I/O Ports 1.I/O Ports Functions Pin Name P17_7 P17_6 P17_5 P17_4 P17_3 P17_2 P17_1 P17_0 I/O Signal P17_7 PPG7 P17_6 PPG6 P17_5 PPG5 P17_4 PPG4 P17_3 PPG3 P17_2 PPG2 P17_1 PPG1 P17_0 PPG0 Circuit Type TP00_0 TP00_0 TP00_0 TP00_0 TP00_0 TP00_0 TP00_0 TP00_0 Function General purpose I/O. Waveform output pin for programmable pulse generator PPG 7. General purpose I/O. Waveform output pin for programmable pulse generator PPG 6. General purpose I/O.
Chapter 30 I/O Ports 1.I/O Ports Functions Pin Name I/O Signal Circuit Type P19_7 P19_7 TP00_0 P19_6 P19_6 SCK5 P19_4 P19_3 P19_5 SOT5 P19_4 SIN5 P19_3 SCK4 TP00_0 TP00_0 TP00_0 P19_0 P19_1 SOT4 P19_0 SIN4 General purpose I/O. Serial data output pin for LIN-USART 5. General purpose I/O. Serial data input pin for LIN-USART 5. General purpose I/O. General purpose I/O. TP00_0 CK4 P19_1 Clock I/O pin for LIN-USART 5. Input for the 16-bit I/O Timer FRT 5. P19_2 P19_2 General purpose I/O.
Chapter 30 I/O Ports 1.I/O Ports Functions Pin Name I/O Signal Circuit Type Function Port 21 P21_7 P21_7 TP00_0 P21_6 P21_6 SCK1 General purpose I/O. TP00_0 CK1 P21_5 P21_4 P21_3 P21_5 SOT1 P21_4 SIN1 P21_3 SCK0 TP00_0 TP00_0 TP00_0 P21_0 P21_1 SOT0 P21_0 SIN0 General purpose I/O. Serial data output pin for LIN-USART 1. General purpose I/O. Serial data input pin for LIN-USART 1. General purpose I/O. General purpose I/O. TP00_0 CK0 P21_1 Clock I/O pin for LIN-USART 1.
Chapter 30 I/O Ports 1.I/O Ports Functions Pin Name P23_7 I/O Signal P23_7 TX3 Circuit Type TP00_0 P23_6 P23_6 RX3 P23_5 TX2 TP00_0 P23_3 RX2 TP00_0 TP00_0 Transmission output pin for CAN 2. Reception input pin for CAN 2. INT10 External interrupt request input pin for INT 10. General purpose I/O. TX1 TP00_0 RX1 P23_1 TX0 RX0 Transmission output pin for CAN 1. General purpose I/O. TP00_0 Reception input pin for CAN 1. External interrupt request input pin for INT 9.
Chapter 30 I/O Ports 1.I/O Ports Functions Pin Name I/O Signal Circuit Type Function Port 25 P25_7 P25_6 P25_5 P25_4 P25_3 P25_2 P25_1 P25_0 P25_7 SMC2M5 P25_6 SMC2P5 P25_5 SMC1M5 P25_4 SMC1P5 P25_3 SMC2M4 P25_2 SMC2P4 P25_1 SMC1M4 P25_0 SMC1P4 TP05_0 TP05_0 TP05_0 TP05_0 TP05_0 TP05_0 TP05_0 TP05_0 General purpose I/O. PWM output 2M (-) stepper motor controller 5. General purpose I/O. PWM output 2P (+) stepper motor controller 5. General purpose I/O. PWM output 1M (-) stepper motor controller 5.
Chapter 30 I/O Ports 1.I/O Ports Functions Pin Name I/O Signal Circuit Type P26_0 P26_0 SMC1P2 Function General purpose I/O. TP05_0 AN24 PWM output 1P (+) stepper motor controller 2. Analog input pin 24 for the A/D converter 1. Port 27 P27_7 P27_7 P27_6 P27_5 SMC2M1 General purpose I/O. TP05_0 Analog input pin 23 for the A/D converter 1. P27_6 General purpose I/O. SMC2P1 TP05_0 AN22 Analog input pin 22 for the A/D converter 1. General purpose I/O.
Chapter 30 I/O Ports 1.I/O Ports Functions Pin Name P28_3 P28_2 P28_1 P28_0 I/O Signal P28_3 AN11 P28_2 AN10 P28_1 AN9 P28_0 AN8 Circuit Type TP03_0 TP03_0 TP03_0 TP03_0 Function General purpose I/O. Analog input pin 11 for the A/D converter 1. General purpose I/O. Analog input pin 10 for the A/D converter 1. General purpose I/O. Analog input pin 9 for the A/D converter 1. General purpose I/O. Analog input pin 8 for the A/D converter 1.
Chapter 30 I/O Ports 1.I/O Ports Functions Pin Name P30_0 I/O Signal P30_0 COM0 Circuit Type TP06_0 Function General purpose I/O. Common driver output pin 0 LCD controller. Port 31 P31_7 P31_6 P31_5 P31_4 P31_3 P31_2 P31_1 P31_0 P31_7 SEG39 P31_6 SEG38 P31_5 SEG37 P31_4 SEG36 P31_3 SEG35 P31_2 SEG34 P31_1 SEG33 P31_0 SEG32 TP06_0 TP06_0 TP06_0 TP06_0 TP06_0 TP06_0 TP06_0 TP06_0 General purpose I/O. Segment driver output pin 39 LCD controller. General purpose I/O.
Chapter 30 I/O Ports 1.I/O Ports Functions Pin Name I/O Signal Circuit Type P32_0 P32_0 SEG24 Function General purpose I/O. TP06_0 SIN14 Segment driver output pin 24 LCD controller. Serial data input pin for LIN-USART 14. Port 33 P33_7 P33_7 SEG23 TP06_0 P33_6 P33_6 SEG22 TP06_0 P33_4 General purpose I/O. TP06_0 Serial data output pin for LIN-USART 13. P33_4 General purpose I/O. SEG20 TP06_0 P33_3 SEG19 P33_1 P33_0 SEG18 Segment driver output pin 20 LCD controller.
Chapter 30 I/O Ports 1.I/O Ports Functions Pin Name I/O Signal Circuit Type P34_2 P34_2 P34_1 P34_0 SEG10 Function General purpose I/O. TP06_0 Segment driver output pin 10 LCD controller. SCK10 Clock I/O pin for LIN-USART 10. P34_1 General purpose I/O. SEG9 TP06_0 Segment driver output pin 9 LCD controller. SOT10 Serial data output pin for LIN-USART 10. P34_0 General purpose I/O. SEG8 TP06_0 SIN10 Segment driver output pin 8 LCD controller. Serial data input pin for LIN-USART 10.
Chapter 30 I/O Ports 2.I/O Circuit Types 2. I/O Circuit Types 2.
Chapter 30 I/O Ports 3.Port Register Settings 3. Port Register Settings 3.1 General Rules For all ports, the following rules are valid: 1. All port inputs are disabled by default to avoid transverse current floating before the ports are configured by software. After configuring each port pin according to its function it is necessary to enable the port inputs with the global port enable (PORTEN.GPORTEN). See section Port Input Enable on page 457. 2.
Chapter 30 I/O Ports 3.Port Register Settings 14.Resource output lines are enabled by setting the corresponding PFR and/or EPFR bit in the port. Details see section Port Function Register Setup on page 458. LIN-USART outputs (SOT) must be enabled additionally by setting the SOE bit in the LIN-USART control. 15.Resource bidirectional signals (e.g. SCK of the LIN-USART) are enabled by setting the corresponding PFR and/or EPFR bit in the port.
Chapter 30 I/O Ports 3.Port Register Settings 3.2 I/O Port Block Diagram Port Bus PILR EPILR External bus interface inputs Peripheral inputs PDRD read TTL & Automotive Hysteresis 0 CLKP PDRD CMOS Hysteresis & & 1 STOP or GPORTEN PDR read PPER PPCR Out Driver 1. Peripheral output 2.
Chapter 30 I/O Ports 3.Port Register Settings 3.3 Port Input Enable This section describes the Port Input Enable function. ■ PORTEN: Port Input Enable. PORTEN Addr 7 6 5 4 3 2 1 0 initial 0498h - - - - - - CPORTEN GPORTEN ---- --00 - - - - - - R/W R/W All port inputs are disabled by default to avoid transverse current floating in the IO input stages and the subsequent logic.
Chapter 30 I/O Ports 3.Port Register Settings 3.4 Port Function Register Setup This section describes the Port Function Registers of each port. ■ P00: The functions of Port 00 are controlled by PFR00 Addr 7 6 5 4 3 2 1 0 initial PFR00 0D80h PFR00.7 PFR00.6 PFR00.5 PFR00.4 PFR00.3 PFR00.2 PFR00.1 PFR00.
Chapter 30 I/O Ports 3.Port Register Settings ■ P01: The functions of Port 01 are controlled by PFR01 Addr 7 6 5 4 3 2 1 0 initial PFR01 0D81h PFR01.7 PFR01.6 PFR01.5 PFR01.4 PFR01.3 PFR01.2 PFR01.1 PFR01.0 1111 1111 EPFR01 0DC1h - - - - - - - - ---- ---- R/W R/W R/W R/W R/W R/W R/W R/W If the external bus interface is enabled (by mode pins MD[2:0] or mode vector), P01[7:0] is input/output for data lines D[23:16].
Chapter 30 I/O Ports 3.Port Register Settings ■ P02: The functions of Port 02 are controlled by PFR02 Addr 7 6 5 4 3 2 1 0 initial PFR02 0D82h PFR02.7 PFR02.6 PFR02.5 PFR02.4 PFR02.3 PFR02.2 PFR02.1 PFR02.0 1111 1111 EPFR02 0DC2h - - - - - - - - ---- ---- R/W R/W R/W R/W R/W R/W R/W R/W If the external bus interface is enabled (by mode pins MD[2:0] or mode vector), P02[7:0] is input/output for data lines D[15:8].
Chapter 30 I/O Ports 3.Port Register Settings ■ P03: The functions of Port 03 are controlled by PFR03 Addr 7 6 5 4 3 2 1 0 initial PFR03 0D83h PFR03.7 PFR03.6 PFR03.5 PFR03.4 PFR03.3 PFR03.2 PFR03.1 PFR03.0 1111 1111 EPFR03 0DC3h - - - - - - - - ---- ---- R/W R/W R/W R/W R/W R/W R/W R/W If the external bus interface is enabled (by mode pins MD[2:0] or mode vector), P03[7:0] is input/output for data lines D[7:0].
Chapter 30 I/O Ports 3.Port Register Settings ■ P04: The functions of Port 04 are controlled by PFR04 Addr 7 6 5 4 3 2 1 0 initial PFR04 0D84h PFR04.7 PFR04.6 PFR04.5 PFR04.4 PFR04.3 PFR04.2 PFR04.1 PFR04.0 1111 1111 EPFR04 0DC4h - - - - - - - - ---- ---- R/W R/W R/W R/W R/W R/W R/W R/W If the external bus interface is enabled (by mode pins MD[2:0] or mode vector), P04[7:0] is input/output for address lines A[31:24].
Chapter 30 I/O Ports 3.Port Register Settings ■ P05: The functions of Port 05 are controlled by PFR05 Addr 7 6 5 4 3 2 1 0 initial PFR05 0D85h PFR05.7 PFR05.6 PFR05.5 PFR05.4 PFR05.3 PFR05.2 PFR05.1 PFR05.0 1111 1111 EPFR05 0DC5h - - - - - - - - ---- ---- R/W R/W R/W R/W R/W R/W R/W R/W If the external bus interface is enabled (by mode pins MD[2:0] or mode vector), P05[7:0] is input/output for address lines A[23:16].
Chapter 30 I/O Ports 3.Port Register Settings ■ P06: The functions of Port 06 are controlled by PFR06 Addr 7 6 5 4 3 2 1 0 initial PFR06 0D86h PFR06.7 PFR06.6 PFR06.5 PFR06.4 PFR06.3 PFR06.2 PFR06.1 PFR06.0 1111 1111 EPFR06 0DC6h - - - - - - - - ---- ---- R/W R/W R/W R/W R/W R/W R/W R/W If the external bus interface is enabled (by mode pins MD[2:0] or mode vector), P06[7:0] is input/output for address lines A[15:8].
Chapter 30 I/O Ports 3.Port Register Settings ■ P07: The functions of Port 07 are controlled by PFR07 Addr 7 6 5 4 3 2 1 0 initial PFR07 0D87h PFR07.7 PFR07.6 PFR07.5 PFR07.4 PFR07.3 PFR07.2 PFR07.1 PFR07.0 1111 1111 EPFR07 0DC7h - - - - - - - - ---- ---- R/W R/W R/W R/W R/W R/W R/W R/W If the external bus interface is enabled (by mode pins MD[2:0] or mode vector), P07[7:0] is input/output for address lines A[7:0].
Chapter 30 I/O Ports 3.Port Register Settings ■ P08: The functions of Port 08 are controlled by PFR08 Addr 7 6 5 4 3 2 1 0 initial PFR08 0D88h PFR08.7 PFR08.6 PFR08.5 PFR08.4 PFR08.3 PFR08.2 PFR08.1 PFR08.0 1111 1111 EPFR08 0DC8h - - - - - - - - ---- ---- R/W R/W R/W R/W R/W R/W R/W R/W If the external bus interface is enabled (by mode pins MD[2:0] or mode vector), P08[7:0] is input/output for external bus control signals RDY, BRQ, BGRNTX, RDX, WRX[3:0].
Chapter 30 I/O Ports 3.Port Register Settings ■ P09: The functions of Port 09 are controlled by PFR09 Addr 7 6 5 4 3 2 1 0 initial PFR09 0D89h PFR09.7 PFR09.6 PFR09.5 PFR09.4 PFR09.3 PFR09.2 PFR09.1 PFR09.0 1111 1111 EPFR09 0DC9h - - - - - - - - ---- ---- R/W R/W R/W R/W R/W R/W R/W R/W If the external bus interface is enabled (by mode pins MD[2:0] or mode vector), P09[7:0] is input/output for external bus control signals CSX[7:0].
Chapter 30 I/O Ports 3.Port Register Settings ■ P10: The functions of Port 10 are controlled by PFR10 and EPFR10 Addr 7 6 5 4 3 2 1 0 initial PFR10 0D8Ah - PFR10.6 PFR10.5 PFR10.4 PFR10.3 PFR10.2 PFR10.1 PFR10.0 -111 1111 EPFR10 0DCAh - - EPFR10.5 EPFR10.4 - - - EPFR10.
Chapter 30 I/O Ports 3.Port Register Settings ■ P11: The functions of Port 11 are controlled by PFR11 Addr 7 6 5 4 3 2 1 0 initial PFR11 0D8Bh - - - - - - PFR11.1 PFR11.0 ---- --00 EPFR11 0DCBh - - - - - - - - ---- ---- R/W R/W R/W R/W R/W R/W R/W R/W P11[7:0] is input/output for DMA control signals IOWRX, IORDX. Otherwise, the port can be used as general purpose port. PFR11.1 0 - Port is in general purpose port mode.
Chapter 30 I/O Ports 3.Port Register Settings ■ P12: The functions of Port 12 are controlled by PFR12 and EPFR12 Addr 7 6 5 4 3 2 1 0 initial PFR12 0D8Ch PFR12.7 PFR12.6 PFR12.5 PFR12.4 PFR12.3 PFR12.2 PFR12.1 PFR12.0 0000 0000 EPFR12 0DCCh - EPFR12.6 - - - EPFR12.2 - - -0-- -0-- R/W R/W R/W R/W R/W R/W R/W R/W P12[7:0] is input/output for DMA control signals DEOP, DEOTX, DACKX, DREQ for DMA channels 2 and 3. Otherwise, the port can be used as general purpose port.
Chapter 30 I/O Ports 3.Port Register Settings ■ P13: The functions of Port 13 are controlled by PFR13 and EPFR13 Addr 7 6 5 4 3 2 1 0 initial PFR13 0D8Dh PFR13.7 PFR13.6 PFR13.5 PFR13.4 PFR13.3 PFR13.2 PFR13.1 PFR13.0 0000 0000 EPFR13 0DCDh - EPFR13.6 - - - EPFR13.2 - - -0-- -0-- R/W R/W R/W R/W R/W R/W R/W R/W P13[7:0] is input/output for DMA control signals DEOP, DEOTX, DACKX, DREQ for DMA channels 0 and 1. Otherwise, the port can be used as general purpose port.
Chapter 30 I/O Ports 3.Port Register Settings ■ P14: The functions of Port 14 are controlled by PFR14 and EPFR14 Addr 7 6 5 4 3 2 1 0 initial PFR14 0D8Eh PFR14.7 PFR14.6 PFR14.5 PFR14.4 PFR14.3 PFR14.2 PFR14.1 PFR14.0 0000 0000 EPFR14 0DCEh EPFR14.7 EPFR14.6 EPFR14.5 EPFR14.4 EPFR14.3 EPFR14.2 EPFR14.1 EPFR14.0 0000 0000 R/W R/W R/W R/W R/W R/W R/W R/W P14[7:0] is input/output for Input Capture inputs ICU[7:0], Reload Timer triggers TIN[7:0] and PWM inputs TTG[15:0].
Chapter 30 I/O Ports 3.Port Register Settings Resource function is TIN1 and TTG9/1 input, and EPFR14.1 0 - Resource function is ICU1 input 1 - ICU1 is internally connected to LSYN of LIN-UART 1/9 PFR14.0 0 - Port is in general purpose port mode. 1 - Port is in resource function mode: Resource function is TIN0 and TTG8/0 input, and EPFR14.
Chapter 30 I/O Ports 3.Port Register Settings ■ P15: The functions of Port 15 are controlled by PFR15 and EPFR15 Addr 7 6 5 4 3 2 1 0 initial PFR15 0D8Fh PFR15.7 PFR15.6 PFR15.5 PFR15.4 PFR15.3 PFR15.2 PFR15.1 PFR15.0 0000 0000 EPFR15 0DCFh EPFR15.7 EPFR15.6 EPFR15.5 EPFR15.4 EPFR15.3 EPFR15.2 EPFR15.1 EPFR15.0 0000 0000 R/W R/W R/W R/W R/W R/W R/W R/W P15[7:0] is input/output for Output Compare outputs OCU[7:0] and Reload Timer outputs TOT[7:0].
Chapter 30 I/O Ports 3.Port Register Settings ■ P16: The functions of Port 16 are controlled by PFR16 and EPFR16 Addr 7 6 5 4 3 2 1 0 initial PFR16 0D90h PFR16.7 PFR16.6 PFR16.5 PFR16.4 PFR16.3 PFR16.2 PFR16.1 PFR16.0 0000 0000 EPFR16 0DD0h EPFR16.7 EPFR16.6 EPFR16.5 EPFR16.
Chapter 30 I/O Ports 3.Port Register Settings ■ P17: The functions of Port 17 are controlled by PFR17 Addr 7 6 5 4 3 2 1 0 initial PFR17 0D91h PFR17.7 PFR17.6 PFR17.5 PFR17.4 PFR17.3 PFR17.2 PFR17.1 PFR17.0 0000 0000 EPFR17 0DD1h - - - - - - - - ---- ---- R/W R/W R/W R/W R/W R/W R/W R/W P17[7:0] is input/output for Programmable Pulse Generator outputs PPG[15:8]. Otherwise, the port can be used as general purpose port. PFR17.
Chapter 30 I/O Ports 3.Port Register Settings ■ P18: The functions of Port 18 are controlled by PFR18 and EPFR18 Addr 7 6 5 4 3 2 1 0 initial PFR18 0D92h - PFR18.6 PFR18.5 PFR18.4 - PFR18.2 PFR18.1 PFR18.0 -000 -000 EPFR18 0DD2h - EPFR18.6 EPFR18.5 - - EPFR18.2 EPFR18.
Chapter 30 I/O Ports 3.Port Register Settings ■ P19: The functions of Port 19 are controlled by PFR19 and EPFR19 Addr 7 6 5 4 3 2 1 0 initial PFR19 0D93h - PFR19.6 PFR19.5 PFR19.4 - PFR19.2 PFR19.1 PFR19.0 -000 -000 EPFR19 0DD3h - EPFR19.6 - - - EPFR19.2 - - -0-- -0-- R/W R/W R/W R/W R/W R/W R/W R/W P19[7:0] is input/output for LIN-UART serial communication signals SCK, SOT, SIN of channels 4 and 5, and Free Run Timer FRT inputs CK of channels 4 and 5.
Chapter 30 I/O Ports 3.Port Register Settings ■ P20: The functions of Port 20 are controlled by PFR20 and EPFR20 Addr 7 6 5 4 3 2 1 0 initial PFR20 0D94h - PFR20.6 PFR20.5 PFR20.4 - PFR20.2 PFR20.1 PFR20.0 -000 -000 EPFR20 0DD4h - EPFR20.6 EPFR20.5 - - EPFR20.2 EPFR20.
Chapter 30 I/O Ports 3.Port Register Settings ■ P21: The functions of Port 21 are controlled by PFR21 and EPFR21 Addr 7 6 5 4 3 2 1 0 initial PFR21 0D95h - PFR21.6 PFR21.5 PFR21.4 - PFR21.2 PFR21.1 PFR21.0 -000 -000 EPFR21 0DD5h - EPFR21.6 - - - EPFR21.2 - - -0-- -0-- R/W R/W R/W R/W R/W R/W R/W R/W P21[7:0] is input/output for LIN-UART serial communication signals SCK, SOT, SIN of channels 0 and 1, and Free Run Timer FRT inputs CK of channels 0 and 1.
Chapter 30 I/O Ports 3.Port Register Settings ■ P22: The functions of Port 22 are controlled by PFR22 Addr 7 6 5 4 3 2 1 0 initial PFR22 0D96h PFR22.7 PFR22.6 PFR22.5 PFR22.4 PFR22.3 PFR22.2 PFR22.1 PFR22.
Chapter 30 I/O Ports 3.Port Register Settings Resource function is RX4 input, and INT12 input Remark: This pin supports external interrupt wake up from STOP-HIZ mode. Because of this the internal input line is not forced to low in STOP-HIZ mode if the PFR is set to ‘1’ and interrupt is enabled with ENIR1.EN12 set to ‘1’. Remark: It is generally possible to use input only resource functions (like e.g. INT, ICU, CAN.RX, UART.SIN) also in the Port I/O input mode (PFR=’0’ and DDR=’0’).
Chapter 30 I/O Ports 3.Port Register Settings ■ P23: The functions of Port 23 are controlled by PFR23 Addr 7 6 5 4 3 2 1 0 initial PFR23 0D97h PFR23.7 PFR23.6 PFR23.5 PFR23.4 PFR23.3 PFR23.2 PFR23.1 PFR23.0 0000 0000 EPFR23 0DD7h - - - - - - - - ---- ---- R/W R/W R/W R/W R/W R/W R/W R/W P23[7:0] is input/output for CAN serial communication signals TX, RX of channels 0 to 3, and External Interrupt Triggers INT[11:8].
Chapter 30 I/O Ports 3.Port Register Settings Resource function is RX0 input, and INT8 input Remark: This pin supports external interrupt wake up from STOP-HIZ mode. Because of this the internal input line is not forced to low in STOP-HIZ mode if the PFR is set to ‘1’ and interrupt is enabled with ENIR1.EN8 set to ‘1’. Remark: It is generally possible to use input only resource functions (like e.g. INT, ICU, CAN.RX, UART.SIN) also in the Port I/O input mode (PFR=’0’ and DDR=’0’).
Chapter 30 I/O Ports 3.Port Register Settings ■ P24: The functions of Port 24 are controlled by PFR24 Addr 7 6 5 4 3 2 1 0 initial PFR24 0D98h PFR24.7 PFR24.6 PFR24.5 PFR24.4 PFR24.3 PFR24.2 PFR24.1 PFR24.0 0000 0000 EPFR24 0DD8h - - - - - - - - ---- ---- R/W R/W R/W R/W R/W R/W R/W R/W P24[7:0] is input/output for I2C serial communication signals SCL, SDA of channels 2 and 3, and External Interrupt Triggers INT[7:0].
Chapter 30 I/O Ports 3.Port Register Settings Remark: This pin supports external interrupt wake up from STOP-HIZ mode. Because of this the internal input line is not forced to low in STOP-HIZ mode if the PFR is set to ‘1’ and interrupt is enabled with ENIR0.EN2 set to ‘1’. PFR24.1 0 - Port is in general purpose port mode. 1 - Port is in resource function mode: Resource function is INT1 input Remark: This pin supports external interrupt wake up from STOP-HIZ mode.
Chapter 30 I/O Ports 3.Port Register Settings ■ P25: The functions of Port 25 are controlled by PFR25 Addr 7 6 5 4 3 2 1 0 initial PFR25 0D99h PFR25.7 PFR25.6 PFR25.5 PFR25.4 PFR25.3 PFR25.2 PFR25.1 PFR25.0 0000 0000 EPFR25 0DD9h - - - - - - - - ---- ---- R/W R/W R/W R/W R/W R/W R/W R/W P25[7:0] is input/output for Stepper Motor PWM output signals and Comparator Inputs SMC2M, SMC2P, SMC1M, SMC1P of channels 4 and 5.
Chapter 30 I/O Ports 3.Port Register Settings ■ P26: The functions of Port 26 are controlled by PFR26 and EPFR26 Addr 7 6 5 4 3 2 1 0 initial PFR26 0D9Ah PFR26.7 PFR26.6 PFR26.5 PFR26.4 PFR26.3 PFR26.2 PFR26.1 PFR26.0 0000 0000 EPFR26 0DDAh EPFR26.7 EPFR26.6 EPFR26.5 EPFR26.4 EPFR26.3 EPFR26.2 EPFR26.1 EPFR26.
Chapter 30 I/O Ports 3.Port Register Settings ■ P27: The functions of Port 27 are controlled by PFR27 and EPFR27 Addr 7 6 5 4 3 2 1 0 initial PFR27 0D9Bh PFR27.7 PFR27.6 PFR27.5 PFR27.4 PFR27.3 PFR27.2 PFR27.1 PFR27.0 0000 0000 EPFR27 0DDBh EPFR27.7 EPFR27.6 EPFR27.5 EPFR27.4 EPFR27.3 EPFR27.2 EPFR27.1 EPFR27.
Chapter 30 I/O Ports 3.Port Register Settings ■ P28: The functions of Port 28 are controlled by PFR28 Addr 7 6 5 4 3 2 1 0 initial PFR28 0D9Ch PFR28.7 PFR28.6 PFR28.5 PFR28.4 PFR28.3 PFR28.2 PFR28.1 PFR28.0 0000 0000 EPFR28 0DDCh - - - - - - - - ---- ---- R/W R/W R/W R/W R/W R/W R/W R/W P28[7:0] is input/output for A/D converter analogue inputs AN[15:8], and D/A converter analogue outputs DA[1:0]. Otherwise, the port can be used as general purpose port. PFR28.
Chapter 30 I/O Ports 3.Port Register Settings ■ P29: The functions of Port 29 are controlled by PFR29 Addr 7 6 5 4 3 2 1 0 initial PFR29 0D9Dh PFR29.7 PFR29.6 PFR29.5 PFR29.4 PFR29.3 PFR29.2 PFR29.1 PFR29.0 0000 0000 EPFR29 0DDDh - - - - - - - - ---- ---- R/W R/W R/W R/W R/W R/W R/W R/W P29[7:0] is input/output for A/D converter analogue inputs AN[7:0]. Otherwise, the port can be used as general purpose port. PFR29.7 0 - Port is in general purpose port mode.
Chapter 30 I/O Ports 3.Port Register Settings ■ P30: The functions of Port 30 are controlled by PFR30 Addr 7 6 5 4 3 2 1 0 initial PFR30 0D9Eh PFR30.7 PFR30.6 PFR30.5 PFR30.4 PFR30.3 PFR30.2 PFR30.1 PFR30.0 0000 0000 EPFR30 0DDEh - - - - - - - - ---- ---- R/W R/W R/W R/W R/W R/W R/W R/W P30[7:0] is input/output for LCD controller reference voltage analogue inputs V[3:0], and LCD controller common driver outputs COM[3:0].
Chapter 30 I/O Ports 3.Port Register Settings ■ P31: The functions of Port 31 are controlled by PFR31 Addr 7 6 5 4 3 2 1 0 initial PFR31 0D9Fh PFR31.7 PFR31.6 PFR31.5 PFR31.4 PFR31.3 PFR31.2 PFR31.1 PFR31.0 0000 0000 EPFR31 0DDFh - - - - - - - - ---- ---- R/W R/W R/W R/W R/W R/W R/W R/W P31[7:0] is input/output for LCD controller segment driver outputs SEG[39:32]. Otherwise, the port can be used as general purpose port. PFR31.
Chapter 30 I/O Ports 3.Port Register Settings ■ P32: The functions of Port 32 are controlled by PFR32 and EPFR32 Addr 7 6 5 4 3 2 1 0 initial PFR32 0DA0h PFR32.7 PFR32.6 PFR32.5 PFR32.4 PFR32.3 PFR32.2 PFR32.1 PFR32.0 0000 0000 EPFR32 0DE0h - EPFR32.6 EPFR32.5 EPFR32.4 - EPFR32.2 EPFR32.1 EPFR32.
Chapter 30 I/O Ports 3.Port Register Settings ■ P33: The functions of Port 33 are controlled by PFR33 and EPFR33 Addr 7 6 5 4 3 2 1 0 initial PFR33 0DA1h PFR33.7 PFR33.6 PFR33.5 PFR33.4 PFR33.3 PFR33.2 PFR33.1 PFR33.0 0000 0000 EPFR33 0DE1h - EPFR33.6 EPFR33.5 EPFR33.4 - EPFR33.2 EPFR33.1 EPFR33.
Chapter 30 I/O Ports 3.Port Register Settings ■ P34: The functions of Port 34 are controlled by PFR34 and EPFR34 Addr 7 6 5 4 3 2 1 0 initial PFR34 0DA2h PFR34.7 PFR34.6 PFR34.5 PFR34.4 PFR34.3 PFR34.2 PFR34.1 PFR34.0 0000 0000 EPFR34 0DE2h - EPFR34.6 EPFR34.5 EPFR34.4 - EPFR34.2 EPFR34.1 EPFR34.
Chapter 30 I/O Ports 3.Port Register Settings ■ P35: The functions of Port 35 are controlled by PFR35 and EPFR35 Addr 7 6 5 4 3 2 1 0 initial PFR35 0DA3h PFR35.7 PFR35.6 PFR35.5 PFR35.4 PFR35.3 PFR35.2 PFR35.1 PFR35.0 0000 0000 EPFR35 0DE3h - EPFR35.6 EPFR35.5 EPFR35.4 - EPFR35.2 EPFR35.1 EPFR35.
Chapter 30 I/O Ports 3.Port Register Settings 3.5 Port Input Level Selection The input levels of each port can be programmed bit-wise between CMOS Hysteresis type A and B, Automotive Hysteresis and TTL level. CMOS Hysteresis type A: CMOS Hysteresis type B: Automotive Hysteresis: TTL VIL=0.3 x VDD VIL=0.2 x VDD VIL=0.5 x VDD VIL=0.8 V VIH=0.7 x VDD VIH=0.8 x VDD VIH=0.8 x VDD VIH=2.1 V For setup, the Port Input Level Registers (PILR, EPILR) of each port are used. PILRx.y EPILRx.
Chapter 30 I/O Ports 3.Port Register Settings PILR20 0E54h PILR20.7 PILR20.6 PILR20.5 PILR20.4 PILR20.3 PILR20.2 PILR20.1 PILR20.0 0000 0000 PILR21 0E55h PILR21.7 PILR21.6 PILR21.5 PILR21.4 PILR21.3 PILR21.2 PILR21.1 PILR21.0 0000 0000 PILR22 0E56h PILR22.7 PILR22.6 PILR22.5 PILR22.4 PILR22.3 PILR22.2 PILR22.1 PILR22.0 0000 0000 PILR23 0E57h PILR23.7 PILR23.6 PILR23.5 PILR23.4 PILR23.3 PILR23.2 PILR23.1 PILR23.0 0000 0000 PILR24 0E58h PILR24.7 PILR24.
Chapter 30 I/O Ports 3.
Chapter 30 I/O Ports 3.Port Register Settings PPER02 0EC2h PPER02.7 PPER02.6 PPER02.5 PPER02.4 PPER02.3 PPER02.2 PPER02.1 PPER02.0 0000 0000 PPER03 0EC3h PPER03.7 PPER03.6 PPER03.5 PPER03.4 PPER03.3 PPER03.2 PPER03.1 PPER03.0 0000 0000 PPER04 0EC4h PPER04.7 PPER04.6 PPER04.5 PPER04.4 PPER04.3 PPER04.2 PPER04.1 PPER04.0 0000 0000 PPER05 0EC5h PPER05.7 PPER05.6 PPER05.5 PPER05.4 PPER05.3 PPER05.2 PPER05.1 PPER05.0 0000 0000 PPER06 0EC6h PPER06.7 PPER06.
Chapter 30 I/O Ports 3.Port Register Settings Port Pull-Up/Pull-Down Control Registers Bit PPCRx.y 0 1 (default) Pull Down is selected Pull-Up is selected Addr 7 6 5 4 3 2 1 0 initial PPCR00 0F00h PPCR00.7 PPCR00.6 PPCR00.5 PPCR00.4 PPCR00.3 PPCR00.2 PPCR00.1 PPCR00.0 1111 1111 PPCR01 0F01h PPCR01.7 PPCR01.6 PPCR01.5 PPCR01.4 PPCR01.3 PPCR01.2 PPCR01.1 PPCR01.0 1111 1111 PPCR02 0F02h PPCR02.7 PPCR02.6 PPCR02.5 PPCR02.4 PPCR02.3 PPCR02.2 PPCR02.1 PPCR02.
Chapter 30 I/O Ports 3.Port Register Settings PPCR28 0F1Ch PPCR28.7 PPCR28.6 PPCR28.5 PPCR28.4 PPCR28.3 PPCR28.2 PPCR28.1 PPCR28.0 1111 1111 PPCR29 0F1Dh PPCR29.7 PPCR29.6 PPCR29.5 PPCR29.4 PPCR29.3 PPCR29.2 PPCR29.1 PPCR29.0 1111 1111 PPCR30 0F1Eh PPCR30.7 PPCR30.6 PPCR30.5 PPCR30.4 PPCR30.3 PPCR30.2 PPCR30.1 PPCR30.0 1111 1111 PPCR31 0F1Fh PPCR31.7 PPCR31.6 PPCR31.5 PPCR31.4 PPCR31.3 PPCR31.2 PPCR31.1 PPCR31.0 1111 1111 PPCR32 0F20h PPCR32.7 PPCR32.
Chapter 30 I/O Ports 3.Port Register Settings PODR14 0E0Eh PODR14.7 PODR14.6 PODR14.5 PODR14.4 PODR14.3 PODR14.2 PODR14.1 PODR14.0 0000 0000 PODR15 0E0Fh PODR15.7 PODR15.6 PODR15.5 PODR15.4 PODR15.3 PODR15.2 PODR15.1 PODR15.0 0000 0000 PODR16 0E10h PODR16.7 PODR16.6 PODR16.5 PODR16.4 PODR16.3 PODR16.2 PODR16.1 PODR16.0 0000 0000 PODR17 0E11h PODR17.7 PODR17.6 PODR17.5 PODR17.4 PODR17.3 PODR17.2 PODR17.1 PODR17.0 0000 0000 PODR18 0E12h PODR18.7 PODR18.
Chapter 30 I/O Ports 3.
Chapter 30 I/O Ports 3.
Chapter 31 External Bus 1.Overview of the External Bus Interface Chapter 31 External Bus The external bus interface controller controls the interfaces with the internal bus for chips and with external memory and I/O devices. This chapter explains each function of the external bus interface and its operation. 1. Overview of the External Bus Interface 1.1 Features ● The external bus interface has the following features: • Addresses of up to 32 bits (4 GB space) can be output.
Chapter 31 External Bus 1.Overview of the External Bus Interface • Capable of setting timing values such as the CAS latency and RAS - CAS delay (SDRAM area) • Capable of controlling the distributed/centralized auto - refresh, self - refresh, and other refresh timings (SDRAM area) ● Fly-by transfer by DMA can be performed. • • • • Transfer between memory and I/O can be performed in a single access operation. The memory wait cycle can be synchronized with the I/O wait cycle in fly-by transfer.
Chapter 31 External Bus 1.Overview of the External Bus Interface 1.
Chapter 31 External Bus 1.Overview of the External Bus Interface 1.3 I/O Pins The I/O pins are external bus interface pins (Some pins have other uses).
Chapter 31 External Bus 1.
Chapter 31 External Bus 2.External Bus Interface Registers 2. External Bus Interface Registers This section explains the registers used in the external bus interface.
Chapter 31 External Bus 2.
Chapter 31 External Bus 2.External Bus Interface Registers select area. Figure 2-2 "Configuration of Area Configuration Registers 0-7 (ACR0-7)" shows the configuration of area configuration registers 0-7 (ACR0-7).
Chapter 31 External Bus 2.
Chapter 31 External Bus 2.
Chapter 31 External Bus 2.External Bus Interface Registers Table 2-3 Setting of the Maximum Burst Length of Each Chip Select BST1 BST0 Maximum burst length 1 0 4 bursts (address boundary: 2 bits) 1 1 8 bursts (address boundary: 3 bits) In areas for which a burst length other than the single access is set, continuous burst access is performed within the address boundary determined by the burst length only when prefetch access is performed or data having a size exceeding the bus width is read.
Chapter 31 External Bus 2.External Bus Interface Registers WREN 1 Write enable/disable Enable write If an area for which write operations are disabled is accessed for a write operation from the internal bus, the access is ignored and no external access at all is performed. Set the WREN bit of areas for which write operations are not required, such as data areas, to 0. [Bit 4] LEND (Little ENDian select) This bit sets the order of bytes of each chip select area as indicated in the following table.
Chapter 31 External Bus 2.External Bus Interface Registers Table 2-4 Access Type Settings for Each Chip Select Area TYP3 TYP2 TYP1 TYP0 1 1 1 1 Access type Mask area setting (The access type is the same as that of the overlapping area) *3 *1: If this setting is made, WR0-WR3 can be used as the enable of each bit. *2: Only the ACR6 and ACR7 registers are valid. The ACR0, ACR1, ACR2, ACR3, ACR4, and ACR5 registers are disabled. *3: See the CS area mask setting function (next bullet).
Chapter 31 External Bus 2.External Bus Interface Registers 2.3 Area Wait Register (AWR0-7) This section explains the configuration and functions of the area wait registers (AWR0-7). ■ Configuration of the Area Wait Registers (AWR0-7) The area wait registers (AWR0-7: Area Wait Register 0-7) specify various kinds of waits for each chip select area. Figure 2-3 "Configuration of the Area Wait Registers registers (AWR0-7).
Chapter 31 External Bus 2.
Chapter 31 External Bus 2.External Bus Interface Registers [Bits 15-12] W15-12 (First Wait Cycle) These bits set the number of auto-wait cycles to be inserted into the first access cycle of each cycle. Except for the burst access cycles, only this wait setting is used. Table 2-5 "Settings for the Number of Auto-Wait Cycles (During First Access)" lists the settings for the number of auto-wait cycles during first access.
Chapter 31 External Bus 2.External Bus Interface Registers [Bits 7,6] W07-06 (Read -> Write Idle Cycle) The read -> write idle cycle is set to prevent collision of read data and write data on the data bus when a write cycle follows a read cycle. During an idle cycle, all chip select signals are negated and the data terminals maintain the high impedance state.
Chapter 31 External Bus 2.External Bus Interface Registers [Bits 3] W03 (WR0-WR3, WRn Output Timing Selection) The WR0-WR3, WRn output timing setting selects whether to use write strobe output as an asynchronous strobe or synchronous write enable. The asynchronous strobe setting corresponds to normal memory/IO. The synchronous enable setting corresponds to clock-synchronized memory/IO (such as the memory in an ASIC).
Chapter 31 External Bus 2.External Bus Interface Registers [Bits 2] W02 (Address -> CSn Delay) The address -> CSn delay setting is made when a certain type of setup is required for the address when CSn falls or CSn edges are needed for successive accesses to the same chip select area. Set the address and set the delay from AS output to CS0-CS7 output. W02 Address -> CSn delay 0 No delay 1 Delay If no delay is selected by setting 0, assertion of CS0-CS7 starts at the same timing that AS is asserted.
Chapter 31 External Bus 2.External Bus Interface Registers [Bits 0] W00 (RD/WRn -> CSn Hold Extension Cycle) The RD/WRn -> CSn hold extension cycle is set to extend the period before negating CSn after the read/write strobe is negated. One hold extension cycle is inserted before CSn is negated after the read/write strobe is negated.
Chapter 31 External Bus 2.External Bus Interface Registers Table 2-10 Setting the Number of Cycles from RAS Output to CAS Output W14 W13 W12 RAS-CAS delay cycle 1 1 1 8 cycles For all the areas connected to SDRAM/FCRAM, set these bits to the same RAS - CAS delay cycle. [Bit 11] W11: Reserved bit Be sure to set this bit to 0. [Bits 10 - 8] W10 to W08 (CAS latency Cycle): CAS latency Set these bits to the CAS latency. Table 4.2 - 20 lists the settings for the CAS latency.
Chapter 31 External Bus 2.External Bus Interface Registers Table 4.2 - 22 lists the settings for the write recovery cycle. Table 2-13 Write recovery cycle W05 W04 Write recovery cycle 0 0 Prohibited 0 1 2 cycles 1 0 3 cycles 1 1 4 cycles For all the areas connected to SDRAM/FCRAM, set these bits to the same write recovery cycle. [Bits 3 - 2] W03 and W02 (RAS Active time): RAS active time Set these bits to the minimum number of cycles for RAS active time. Table 4.
Chapter 31 External Bus 2.External Bus Interface Registers ■ Structure of the Memory Setting Register (MCRA for SDRAM/FCRAM auto - precharge OFF mode) Memory setting register (MCRA for SDRAM/FCRAM auto - precharge OFF mode) The memory setting register (MCRA: Memory Setting Register for extend type - A for SDRAM/FCRAM auto precharge OFF mode) is used to make various settings for SDRAM/FCRAM connected to the chip select area.
Chapter 31 External Bus 2.External Bus Interface Registers Table 2-27 lists the settings for burst write. Table 2-18 Settings for burst write WBST Settings for burst write 0 Single write 1 Burst write For connecting FCRAM, be sure to set the bit to 1. FCRAM supports neither burst read nor single write mode. [BIt 26] BANK (BANK type select): Bank number setting Set this bit to the number of banks of SDRAM to be connected. Table 2-28 lists the settings for bank number.
Chapter 31 External Bus 2.
Chapter 31 External Bus 2.External Bus Interface Registers ■ Functions of Bits in the I/O Wait Registers for DMAC (IOWR0-3) The following explains the functions of the bits in the I/O wait registers for DMAC. [Bits 31, 23] RYE0,1 (RDY enable 0,1) These bits set the wait control, using RDY, of channels 0-3 during DMAC fly-by access. RYEn RDY function setting 0 Disable RDY input for I/O access. 1 Enable RDY input for I/O access.
Chapter 31 External Bus 2.External Bus Interface Registers is set to the high impedance state.
Chapter 31 External Bus 2.External Bus Interface Registers [Bits 27-24, 19-16, 11-8] IW03-00,IW13-10 (I/O Access Wait) These bits set the number of auto-wait cycles for I/O access during DMA fly-by access. Table 2-23 "Settings for the Number of I/O Wait Cycles" lists the settings for the number of I/O wait cycles. Table 2-23 Settings for the Number of I/O Wait Cycles IWn3 IWn2 IWn1 IWn0 0 0 0 0 0 cycle 0 0 0 1 1 cycle ... 1 1 Number of I/O wait cycles ...
Chapter 31 External Bus 2.External Bus Interface Registers Before setting this register, be sure to make all settings required for the corresponding chip select areas. CSE7-0 Area control 0 Disable 1 Enable Table 2-24 " CSn Corresponding to the Chip Select Enable Bits" lists the corresponding CSn for the chip select enable bits.
Chapter 31 External Bus 2.External Bus Interface Registers [Bits 23-16] CHE7-0 (Cache Enable 7-0) These bits enable and disable each chip select area for transfers to the built-in cache. CHEn Cache area setting 0 Not a cache area (data read from the applicable area is not saved in the cache) 1 Cache area (data read from the applicable area is saved in the cache) 2.
Chapter 31 External Bus 2.External Bus Interface Registers [Bit 6] PSUS (Prefetch suspend) This bit controls temporary stopping of prefetch to all areas. PSUS Prefetch control 0 Enable prefetch 1 Suspend prefetch If 1 is set, no new prefetch operation is performed before 0 is written. Since during this time the contents of the prefetch buffer are not deleted unless a prefetch buffer occurs, clear the prefetch buffer using the PCLR bit function (bit 5) before restarting prefetch.
Chapter 31 External Bus 2.External Bus Interface Registers 2.10 Refresh Control Register (RCR) This section describes the bit configuration and functions of the refresh control register (RCR). ■ Structure of the Refresh Control Register (RCR) The refresh control register (RCR) is used to make various refresh control settings for SDRAM. The setting of this register is meaningless as long as SDRAM control is not set for any area, in that case the register value must not be updated from the initial state.
Chapter 31 External Bus 2.External Bus Interface Registers When read by a Read - modify - Write instruction, the SELF, RRLD, and PON bits always return to 0. (Bit 30) RRLD (Refresh counter ReLoaD): Refresh counter start control This bit is used to start and reload the fresh counter. Table 4.2-43 shows the function of refresh counter startup control.
Chapter 31 External Bus 2.External Bus Interface Registers [Bits 22 - 20] RFC2, RFC1, RFC0 (ReFresh Count): Refresh count Set these bits to the number of times a refresh must be performed to refresh all SDRAM. Table 4.2-45 shows the number of times to refresh.
Chapter 31 External Bus 2.External Bus Interface Registers Table 4.2-47 lists the settings for the refresh cycle (tRC).
Chapter 31 External Bus 3.Setting Example of the Chip Select Area 3. Setting Example of the Chip Select Area In the external bus interface, a total of eight chip select areas can be set. This section presents an example of setting the chip select area. ■ Example of Setting the Chip Select Area The address space of each area can be placed, in units of a minimum of 64 KB, anywhere in the 4 GB space using ASR0-7 (Area Select Registers) and ACR0-7 (Area Configuration Registers).
Chapter 31 External Bus 4.Endian and Bus Access 4. Endian and Bus Access There is a one-to-one correspondence between the WR0-WR3 control signal and the byte location regardless of the endian method (big or little) and the data bus width. The following summarizes the location of bytes on the data bus of the MB91460 series used according to the specified data bus width and the corresponding control signal for each bus mode.
Chapter 31 External Bus 4.Endian and Bus Access ● SDRAM Interface Figure 4-3 Data bus width of the SDRAM (FCRAM) interface and its control signals a)32-bit bus width Data bus b)16-bit bus width Control signal Data bus c)8-bit bus width Control signal Data bus Control si D31 DQMUU DQMUU DQMUL DQMUL - - DQMUU DQMLU - - - - DQMLL - - - - D0 (D15 to 0 are not used.) (D23 to 0 are not used.) 4.
Chapter 31 External Bus 4.
Chapter 31 External Bus 4.
Chapter 31 External Bus 4.
Chapter 31 External Bus 4.
Chapter 31 External Bus 4.Endian and Bus Access Figure 4-13 Example of Connecting the MB91460 Series to External Devices This LSI D31 D23 D15 D07 to to to to D24 D16 D08 D00 WR3 WR0 WR1 WR2 00 01 10 * For 16/8-bit devices, use the data bus on the MSB side of this LSI. 11 D31 D24 D23 D16 D15 D08 D07 0 D00 D15 32-bit device (low-order 2 bits of the address 00 to 11) 1 D08 D07 D00 *16-bit device (low-order 1 bit of the address 0/1) 0 D07 D00 *8-bit device 4.
Chapter 31 External Bus 4.Endian and Bus Access ● Halfword access The byte data on the MSB side for the big endian address 0 becomes byte data on the LSB side when the little endian method is used. For halfword access, the byte locations of two bytes are reversed. 0 -> 1, 1 -> 0 ● Byte access There is no difference between little endian and big endian. ■ Restrictions on the Little Endian Area • If prefetch is enabled for a little endian area, always use word access to access the area.
Chapter 31 External Bus 4.
Chapter 31 External Bus 4.Endian and Bus Access ● 8-bit bus width Figure 4-19 Relationship between the Internal Register and External Data Bus in the 8-bit Bus Width Internal register Output address low-order digits External bus "00" "01" D31 D23 read/write AA DD "10" "11" CC BB D31 AA BB D15 CC D07 DD ■ Examples of Connection with External Devices The following shows examples of connecting the MB91460 series to external devices for each bus width.
Chapter 31 External Bus 4.
Chapter 31 External Bus 4.Endian and Bus Access 4.3 Comparison of Big Endian and Little Endian External Access This section shows a comparison of big endian and little endian external access in word access, halfword access, and byte access for each bus width.
Chapter 31 External Bus 4.
Chapter 31 External Bus 4.
Chapter 31 External Bus 4.
Chapter 31 External Bus 4.
Chapter 31 External Bus 4.
Chapter 31 External Bus 4.
Chapter 31 External Bus 4.
Chapter 31 External Bus 5.Operation of the Ordinary bus interface 5. Operation of the Ordinary bus interface This section explains operation of the ordinary bus interface. ■ Ordinary Bus Interface For the ordinary bus interface, two clock cycles are the basic bus cycles for both read access and write access. The following operational phases of the ordinary bus interface are explained below with the use of a timing chart.
Chapter 31 External Bus 5.Operation of the Ordinary bus interface Figure 5-1 Basic Timing (For Successive Accesses) MCLK A[31:0] #2 #1 AS CSn RD READ D[31:0] #1 #2 WRn WRITE D[31:0] #1 #2 • AS is asserted for one cycle in the bus access start cycle. • A31-0 continues to output the address of the location of the start byte in word/halfword/byte access from the bus access start cycle to the bus access end cycle.
Chapter 31 External Bus 5.Operation of the Ordinary bus interface Figure 5-2 Timing Chart for the WRn + Byte Control Type MCLK A[31:0] AS CSn * RD WR0,WR1 READ WR2,WR3 D[31:0] WR WR0,WR1 WRITE WR2,WR3 D[31:0] • Operation of AS, CSn, RD, A31-0, and D31-16 is the same as that described in 5.1 "Basic Timing". WRn is asserted from the 2nd cycle of the bus access. Negation occurs after the wait cycle of bits W15-W12 of the AWR register is inserted.
Chapter 31 External Bus 5.Operation of the Ordinary bus interface 5.3 Read -> Write Operation This section shows the operating timing for read -> write. ■ Operation Timing of Read -> Write Figure 5-3 "Timing Chart for Read -> Write" shows the operation timing for (TYP3-0=0000B, AWR=0048H). Figure 5-3 Timing Chart for Read -> Write Read Idle * Write MCLK A[31:0] AS CSn RD WRn D[31:0] • Setting of the W07/W06 bits of the AWR register enables 0-3 idle cycles to be inserted.
Chapter 31 External Bus 5.Operation of the Ordinary bus interface Figure 5-4 Timing Chart for the Write -> Write Operation Write Write recovery * Write MCLK A[31:0] AS CSn WRn D[31:0] • Setting of the W05/W04 bits of the AWR register enables 0-3 write cycles to be inserted. • After all of the write cycles, recovery cycles are generated. • Write recovery cycles are also generated if write access is divided into phases for access with a bus width wider than that specified. 5.
Chapter 31 External Bus 5.Operation of the Ordinary bus interface Figure 5-5 Timing Chart for the Auto-Wait Cycle Basic cycle Wait cycle * MCLK A[31:0] AS CSn RD D[31:0] WRn D[31:0] Setting of the W15-12 bits (first wait cycles) of the AWR register enables 0-15 auto-wait cycles to be set. In Figure 5-5 "Timing Chart for the Auto-Wait Cycle", two auto-wait cycles are inserted, making a total of four cycles for access.
Chapter 31 External Bus 5.Operation of the Ordinary bus interface Figure 5-6 Timing Chart for the External Wait Cycle Basic cycle 2 auto-wait cycles Wait cycle by RDY MCLK A[31:0] AS CSn RD D[31:0] WRn D[31:0] Release RDY Wait Setting 1 for the TYP0 bit of the ACR register and enabling the external RDY input pin enables external wait cycles to be inserted. In Figure 4.5 - 6, the oblique - lined portion of the RDY pin is invalid because the wait based on the automatic wait cycle remains in effect.
Chapter 31 External Bus 5.Operation of the Ordinary bus interface Figure 5-7 Timing Chart for Synchronous Write Enable Output MCLK A[31:0] #2 #1 AS CSn * RD Read D[31:0] #1 #2 WRn Write D[31:0] #1 #2 • If synchronous write enable output is enabled (If the W03 bit of the AWR is 1), operation is as follows. • WR0-WR3 and WRn pin output asserts synchronous write enable output at the timing at which AS pin output is asserted.
Chapter 31 External Bus 5.
Chapter 31 External Bus 5.Operation of the Ordinary bus interface 5.9 CSn -> RD/WRn Setup and RD/WRn -> CSn Hold Setting This section shows the operation timing for the CSn -> RD/WRn setup and RD/WRn -> CSn hold settings. ■ Operation Timing for the CSn -> RD/WRn Setup and RD/WRn -> CSn Hold Settings Figure 5-9 "Timing Chart for the CSn -> RD/WRn Setup and RD/WRn -> CSn Hold Settings" shows the operation timing for (TYP3-0=0000B AWR=000BH).
Chapter 31 External Bus 5.Operation of the Ordinary bus interface ■ Operation Timing for DMA Fly-By Transfer (I/O -> Memory) Figure 5-10 "Timing Chart for DMA Fly-By Transfer (I/O -> Memory)" shows the operation timing for (TYP30=0000B, AWR=0008H, IOWR=51H). This timing chart shows a case in which a wait is not set on the memory side.
Chapter 31 External Bus 5.Operation of the Ordinary bus interface Figure 5-11 Timing Chart for DMA Fly-By Transfer (Memory -> I/O) Basic cycle I/O wait I/O hold I/O idle cycle *1 wait *2 cycle Basic cycle I/O wait I/O hold cycle *1 wait *2 MCLK A[31:0] AS CSn RD D[31:0] IOWR • Setting 1 for the HLD bit of the IOWR0-3 registers enables the I/O read cycle to be extended by one cycle. • Setting the WR1,0 bits of the IOWR0-3 registers enables 0-3 write recovery cycles to be inserted.
Chapter 31 External Bus 6.Burst Access Operation 6. Burst Access Operation In the external bus interface, the operation that transfers successive data items in one access sequence is called burst access. The normal access cycle (that is, not burst access) is called single access. One access sequence starts with an assertion of AS and CSn and ends with negation of CSn. Multiple data items two or more units of data of the unit set for the area. This section explains burst access operation.
Chapter 31 External Bus 6.Burst Access Operation the minimum number of the first access cycles is the wait cycles + 2 cycles (three cycles in the timing chart shown in Figure 6-1 "Timing Chart for Burst Access"). • Setting of the W11-W08 bits of the AWR register enables 0-15 page wait cycles to be inserted.
Chapter 31 External Bus 7.Address/data Multiplex Interface 7. Address/data Multiplex Interface This section explains the following three cases of operation of the address/data multiplex interface: • Without external wait • With external wait • CSn -> RD/WRn setup ■ Without External Wait Figure 7-1 "Timing Chart for the Address/Data Multiplex Interface (without External Wait)" shows the operation timing chart for (TYP3-0=0100B, AWR=0008H).
Chapter 31 External Bus 7.Address/data Multiplex Interface • As with the normal interface, auto-wait (AWR15-12), read -> write idle cycle (AWR7-6), write recovery (AWR54), address -> CSn delay (AWR2), CSn -> RD/WRn setup delay (AWR1), and RD/WRn -> CSn hold delay (AWR0) can be set. • In areas for which the address/data multiplex interface is set, set 1(DBW1-0=00B) as the burst length.
Chapter 31 External Bus 7.
Chapter 31 External Bus 8.Prefetch Operation 8. Prefetch Operation This section explains the prefetch operation. ■ Prefetch Operation The external bus interface controller contains a prefetch buffer consisting of 16 x 8 bits. If the PSUS bit of the TCR register is 0 and read access to an area to which the PFEN bit of the ACR register is set to 1 occurs, the subsequent address is prefetched and then stored in the prefetch buffer.
Chapter 31 External Bus 8.Prefetch Operation During burst access, successive accesses occur only within the address boundary that that is determined by the burst length.
Chapter 31 External Bus 8.Prefetch Operation • • If a buffer read error occurs. A buffer read error is if any of the following events occurs: • When no address is found in the buffer that matches in an to read from a prefetch-enabled area. In this case, the external bus is accessed again. Data read in this case is not stored in the buffer, but the prefetch access is started from the subsequent address to store addresses in the buffer.
Chapter 31 External Bus 9.SDRAM/FCRAM Interface Operation 9. SDRAM/FCRAM Interface Operation This section describes the operations of the SDRAM/FCRAM interface. ■ SDRAM/FCRAM interface The chip select areas can be used as SDRAM/FCRAM interface by setting the TYP3 to TYP0 bits in the area configuration register (ACR) to 100XB. This section provides timing charts to describe the following operations of the SDRAM/FCRAM interface.
Chapter 31 External Bus 9.SDRAM/FCRAM Interface Operation Figure 9-2 Single Read/Write Timing Chart MCLK A #1 #1 D SRAS,SCAS, SWE #1 #1 READ WRIT Read Cas Latency Write Idle cycle Write cycle Read cycle Set the W07 and W06 bits in the area wait register (AWR) to the read - to - write idle cycle according to the SDRAM/FCRAM standards. ■ Single Read Operation Timing Figure 9-3 shows the operation timings assuming that page misses, CAS latency 3, and no auto - precharge are set.
Chapter 31 External Bus 9.SDRAM/FCRAM Interface Operation Figure 9-4 Single Read/Write Timing Chart MCLK A Row D Col Row Col #1 SRAS,SCAS, SWE ACTV WRITA Row Col #2 #3 ACTV READA ACTV CL+BL-1 CL+BL-1 WRITA • Setting TYP to 1001B causes a read/write command with auto - precharge to be issued. Since the cycle from READA/WRITA issuance to ACTV issuance is fixed at CL + BL - 1, however, TYP can be set to 1001B only when FCRAM is connected.
Chapter 31 External Bus 9.SDRAM/FCRAM Interface Operation ■ Self Refresh Writing 1 to the SELF bit in the refresh control register (RCR) causes the SDRAM/FCRAM interface to initiate the self - refresh transition sequence. After executing auto - refreshing the number of times set in the RFC2 to RFC0 bits, the SDRAM/FCRAM interface issues the SELF command to SDRAM/FCRAM to enter the self - refresh mode.
Chapter 31 External Bus 9.SDRAM/FCRAM Interface Operation 9.3 Connecting SDRAM/FCRAM to Many Areas This section shows the connecting SDRAM/FCRAM to many areas. ■ Connecting SDRAM/FCRAM to Many Areas SDRAM/FCRAM can basically be set for all chip select areas. When connecting SDRAM/FCRAM to several areas, connect the same type of modules. Also it needs considerations about bus load when connecting SDRAM/ FCRAM to several areas. More precisely, connect the modules common in the following register settings.
Chapter 31 External Bus 9.
Chapter 31 External Bus 9.SDRAM/FCRAM Interface Operation Table 9-1 SDRAM/FCRAM Interface to SDRAM/FCRAM Connection Table SDRAM/ FCRAM interface pin SDRAM/ FCRAM pin Remarks SWE (WR) WE CS0 to CS7 CS All chip select areas can be set as SDRAM/FCRAM space. A0 to A9 A0 to A9 Addresses do not have to be shifted depending on the bus width. A10/AP A10/AP A10 for row address output; otherwise AP A11 to A13 A11 to A13 Connected to the address used for SDRAM/FCRAM.
Chapter 31 External Bus 9.SDRAM/FCRAM Interface Operation Figure 9-7 Using 64 - Mbit SDRAM CS6 or CS7 This LSI A14 A11-A0 DQMLU DQMUU MCLKO SRAS SCAS SWE MCLKE DQMUL DQMLL DQ31-0 [31-24] CS BA IA11-IA0 RAS CAS WE CKE DQM CLK DQ7-DQ0 SDRAM(No.1) [23-16] CS BA IA11-IA0 RAS CAS WE CKE DQM CLK DQ7-DQ0 SDRAM(No.2) [15-8] CS BA IA11-IA0 RAS CAS WE CKE DQM CLK DQ7-DQ0 SDRAM(No.3) [7-0] CS BA IA11-IA0 RAS CAS WE CKE DQM CLK DQ7-DQ0 SDRAM(No.
Chapter 31 External Bus 9.SDRAM/FCRAM Interface Operation Figure 9-8 Using 64 - Mbit SDRAM This LSI CS7 CS6A15 A14 A11-A0 DQMUU DQMLU DQMUL DQMLL MCLKO SRAS SCAS SWE MCLKE DQ31-0 [31-16] CS BA1BA0 IA11-IA0 RAS CAS WE CKE DQMU DQML CLK DQ15-DQ0 SDRAM(No.1) [15-0] CS BA1BA0 IA11-IA0 RAS CAS WE CKE DQMUDQML CLK DQ15-DQ0 SDRAM(No.2) [31-16] CS BA1BA0 IA11-IA0 RAS CAS WE CKE DQMU DQML CLK DQ15-DQ0 SDRAM(No.
Chapter 31 External Bus 9.SDRAM/FCRAM Interface Operation SDRAM No. 2 is not required when the device is used with only one SDRAM module.
Chapter 31 External Bus 10.DMA Access Operation 10. DMA Access Operation This section explains DMA access operation. ■ DMA Access Operation This section explains the following five DMA operations: • DMA fly-by transfer (I/O -> memory) • DMA fly-by transfer (memory -> I/O) • 2-cycle transfer (internal RAM -> I/O, RAM) • 2-cycle transfer (external -> I/O) • 2-cycle transfer (I/O -> external) 10.1 DMA Fly-By Transfer (I/O -> Memory) This section explains DMA fly-by transfer (I/O -> memory).
Chapter 31 External Bus 10.DMA Access Operation Figure 10-1 Timing Chart for DMA Fly-By Transfer (I/O -> Memory) Basic cycle I/O wait cycle I/O hold wait MCLK A[31:0] memory address AS CSn WRn D[31:0] DACKn FR30 compatible mode DEOPn Basic mode DACKn DEOPn IORD DREQn Sense timing in demand mode n = 0, 1, 2 • Setting 1 for the W01 bit of the AWR register enables the CSn -> RD/WRn setup delay to be set. Set this bit to extend the period between assertion of chip select and the read/write strobe.
Chapter 31 External Bus 10.DMA Access Operation 10.2 DMA Fly-By Transfer (Memory -> I/O) This section explains DMA fly-by transfer (memory -> I/O). ■ DMA Fly-By Transfer (Memory -> I/O) Figure 10-2 "Timing chart for DMA Fly-By Transfer (Memory -> I/O)" shows the operation timing chart for (TYP30=0000B, AWR=0008H, IOWR=41H). Figure 10-2 "Timing chart for DMA Fly-By Transfer (Memory -> I/O)" shows a case in which a wait is not set on the memory side.
Chapter 31 External Bus 10.DMA Access Operation Reference: For memory on the data output side, a read strobe of three bus cycles extended by the I/O wait cycle and I/O hold wait cycle is generated. For I/O on the receiving side, a write strobe of two bus cycles extended by the I/ O wait cycle is generated. The I/O hold wait cycle does not affect the write strobe. However, the address and CS signal are retained until the fly-by bus access cycles end. 10.
Chapter 31 External Bus 10.
Chapter 31 External Bus 10.DMA Access Operation • For the I/O device on the data output side, a read strobe of three bus cycles extended by the I/O wait cycle and I/O hold wait cycle is generated. • For SDRAM/FCRAM on the receiving side, a WRIT command is issued at the timing that allows writing after the I/O wait cycle. The I/O wait cycle may be longer depending on the SDRAM/FCRAM bank active state and SDRAM/FCRAM wait setting. • The I/O hold wait cycle does not affect the write strobe.
Chapter 31 External Bus 10.
Chapter 31 External Bus 10.DMA Access Operation If SDRAM access is shorter than I/O access, the SDRAM access is extended by the I/O access (base access plus I/O wait). Figure 4.10 - 5 shows an operation timing chart assuming TYP3 to TYP0 set to 1000B, AWR set to 0051H, and IOWR set to 42H.
Chapter 31 External Bus 10.DMA Access Operation • For the I/O device on the receiving side, a write strobe of two bus cycles extended by the I/O wait cycle is generated. • The I/O hold wait cycle does not affect the write strobe. • Fly - by transfer must always be performed between data buses having the same bus width. • When the I/O wait cycle is used to reserve data setup time, the I/O wait value must be set according to the page miss condition. A page hit therefore generates a penalty.
Chapter 31 External Bus 10.
Chapter 31 External Bus 10.DMA Access Operation 10.5 2-Cycle Transfer (Internal RAM -> External I/O, RAM) This section explains 2-cycle transfer (internal RAM -> external I/O, RAM) operation. The timing is the same as for external I/O, RAM -> internal RAM. ■ 2-Cycle Transfer (Internal RAM -> External I/O, RAM) Figure 10-8 "Timing Chart for 2-cycle Transfer (Internal RAM -> External I/O, RAM)" shows the operation timing chart for (TYP3-0=0000B, AWR=0008H, IOWR=00H).
Chapter 31 External Bus 10.DMA Access Operation ■ 2-Cycle Transfer (External -> I/O) Figure 10-9 "Timing Chart for 2-Cycle Transfer (External -> I/O" shows the operation timing chart for (TYP30=0000B, AWR=0008H, IOWR=00H). Figure 10-9 "Timing Chart for 2-Cycle Transfer (External -> I/O" shows a case in which a wait is not set for memory and I/O.
Chapter 31 External Bus 10.DMA Access Operation ■ 2-Cycle Transfer (I/O -> External) Figure 10-10 "Timing Chart for 2-Cycle Transfer (I/O -> External)" shows the operation timing chart for (TYP30=0000B, AWR=0008H, IOWR=00H). Figure 10-10 "Timing Chart for 2-Cycle Transfer (I/O -> External)" shows a case in which a wait is not set for memory and I/O.
Chapter 31 External Bus 10.DMA Access Operation ■ 2-Cycle Transfer (I/O -> SDRAM/FCRAM) Figure 4.10 - 11 shows an operation timing chart assuming TYP3 to TYP0 set to 1000B, AWR set to 0051H, and IOWR set to 00H. Figure 10-11 Timing Chart for Two - cycle Transfer (I/O to SDRAM/FCRAM) MC LK A31 to 0 I/O address idle memory address AS CS n SRAS SCAS WR n(SWE) CSn RD D31 to 0 FR30 compatible mode DACKn DEOPn DACKn Basic mode DEOPn DREQn 10.
Chapter 31 External Bus 10.
Chapter 31 External Bus 10.DMA Access Operation • Bus access is the same as that of the interface for non - DMA transfer. • In base mode, DACKn/DEOPn is output at both of transfer source bus access and transfer destination bus access.
Chapter 31 External Bus 11.Bus Arbitration 11. Bus Arbitration This section shows timing charts for releasing the bus right and for acquiring the bus right. ■ Releasing the Bus Right Figure 11-1 "Timing Chart for Releasing the Bus Right" shows the timing chart for releasing the bus right. Figure 11-2 "Timing Chart for Releasing the Bus Right" shows the timing chart for acquiring the bus right.
Chapter 31 External Bus 11.Bus Arbitration Figure 11-2 Timing Chart for Acquiring the Bus Right MCLK A23 to A0 AS CSn * WE Read D31 to D16 BRQ BGRNT 1 cycle • Setting 1 for the BREN bit of the TRC register enables bus arbitration by BRQ/BGRNT to be performed. • When the bus right is released, the pin is set to high impedance and then BGRNT is asserted one cycle later. • When the bus right is acquired, BGRNT is negated and then each pin is activated one cycle later.
Chapter 31 External Bus 12.Procedure for Setting a Register 12. Procedure for Setting a Register This section explains the procedure for setting a register. ■ Procedure for Setting a Register Using the following procedures to make external bus interface settings: 1. Before rewriting the contents of a register, be sure to set the CSER register so that the corresponding area is not used (0). If you change the settings while 1 is set, access before and after the change cannot be guaranteed. 2.
Chapter 31 External Bus 13.Notes on Using the External Bus Interface 13. Notes on Using the External Bus Interface This section explains some notes when using the external bus interface.
Chapter 31 External Bus 13.
Chapter 32 USART (LIN / FIFO) 1.Overview Chapter 32 USART (LIN / FIFO) 1. Overview This chapter explains the function and operation of the USART. The USART with LIN (Local Interconnect Network) - Function is a general-purpose serial data communication interface for performing synchronous or asynchronous communication with external devices. 16 bytes transmission and reception FIFOs are available for selected channels.
Chapter 32 USART (LIN / FIFO) 1.Overview Table 1-1 USART functions (continued) Master-slave communication function (multiprocessor mode) One-to-n communication (one master to n slaves) (This function is supported both for master and slave system).
Chapter 32 USART (LIN / FIFO) 1.
Chapter 32 USART (LIN / FIFO) 2.USART Configuration 2.
Chapter 32 USART (LIN / FIFO) 2.
Chapter 32 USART (LIN / FIFO) 2.USART Configuration • Reception Data Register This register retains reception data. Serial input data is converted and stored in this register. If the FIFO is enabled up to 16 receptions can be saved, the trigger level is progammable. • Transmission Control Circuit The transmission control circuit consists of a transmission bit counter, transmission start circuit, and transmission parity counter.The transmission bit counter counts transmission data bits.
Chapter 32 USART (LIN / FIFO) 2.USART Configuration • Specifying a data length • Selecting a frame data format in mode 1 • Clearing the error flags • Specifying whether to enable transmission • Specifying whether to enable reception • Serial Status Register This register checks the transmission and reception status and error status, and enables and disables transmission and reception interrupt requests.
Chapter 32 USART (LIN / FIFO) 3.USART Pins 3. USART Pins ■ USART Pins The USART pins also serve as general ports. Table 3-1 lists the pin functions, I/O formats, and settings required to use USART.
Chapter 32 USART (LIN / FIFO) 4.USART Registers 4. USART Registers The following table defines the USART04 registers: Table 4-1 USART04 Registers Address bit 15 bit 8 bit 7 bit 0 060H, 061H SCR04 (Serial Control Register) SMR04 (Serial Mode Register) 062H, 063H SSR04 (Serial Status Register) RDR04/TDR04 (Rx, Tx Data Register) 064H, 065H ESCR04 (Extended Status/Control Reg.) ECCR04 (Extended Comm. Contr. Reg.
Chapter 32 USART (LIN / FIFO) 4.
Chapter 32 USART (LIN / FIFO) 4.USART Registers Table 4-2 Functions of each bit of control register 04 (SCR04) Bit name Function bit15 PEN: Parity enable bit This bit selects whether to add a parity bit during transmission in serial asynchronous mode or detect it during reception. Parity is only provided in mode 0 and in mode 2 if SSM of the ECCR04 is selected. This bit is fixed to 0 (no parity) in mode 3 (LIN).
Chapter 32 USART (LIN / FIFO) 4.USART Registers 4.2 Serial Mode Register 04 (SMR04) This register selects an operation mode and baud rate clock and specifies whether to enable output of serial data and clocks to the corresponding pin.
Chapter 32 USART (LIN / FIFO) 4.USART Registers Table 4-4 Bit function of the Serial Mode register 04 (SMR04) Bit name Function bit7 bit6 MD1 and MD0: Operation mode selection bits These two bits sets the USART operation mode. bit5 OTO: One-to-one external clock selection bit This bit sets an external clock directly to the USART’s serial clock.
Chapter 32 USART (LIN / FIFO) 4.
Chapter 32 USART (LIN / FIFO) 4.USART Registers Table 4-5 Functions of each bit of status register 04 (SSR04) Bit name Function bit15 PE: Parity error flag bit • This bit is set to 1 when a parity error occurs during reception and is cleared when 0 is written to the CRE bit of the serial control register (SCR04). • A reception interrupt request is output when this bit and the RIE bit are 1. • Data in the reception data register (RDR04) is invalid when this flag is set.
Chapter 32 USART (LIN / FIFO) 4.USART Registers Table 4-5 Functions of each bit of status register 04 (SSR04) Bit name bit8 Function • This bit enables or disables output of a request for transmission interrupt to the CPU. • A transmission interrupt request is output when this bit and the TDRE bit are 1. TIE: Transmission interrupt request enable bit 4.4 Reception and Transmission Data Register (RDR04 / TDR04) The reception data register (RDR04) holds the received data.
Chapter 32 USART (LIN / FIFO) 4.USART Registers enabled, a transmission interrupt is generated. Write the next part of transmission data when a transmission interrupt is generated or the TDRE bit is 1. 4.5 Extended Status/Control Register (ESCR04) This register provides several LIN functions, direct access to the SIN04 and SOT04 pin and setting for USART synchronous clock mode.
Chapter 32 USART (LIN / FIFO) 4.USART Registers Table 4-6 Function of each bit of the Extended Status/Control Register (ESCR4) Bit name Function bit15 LBIE: LIN break detection interrupt enable bit This bit enables a reception interrupt, if a LIN break was detected. bit14 LBD: LIN break detected flag This bit goes 1 if a LIN break was detected. Writing a 0 to it clears this bit and the corresponding interrupt, if it is enabled. Note: RMW instructions always return "1".
Chapter 32 USART (LIN / FIFO) 4.
Chapter 32 USART (LIN / FIFO) 4.USART Registers Table 4-8 Function of each bit of the Extended Communication Control Register (ECCR04) Bit name Function bit7 INV: Invert serial data This bit inverts the serial data at SIN04 and SOT04 pin. SCK04 is not affected (see ESCR04: SCES). Writing "0": The serial data format is NRZ (default) Writing "1": The serial data is inverted (RZ format) RMW instructions do not affect this bit.
Chapter 32 USART (LIN / FIFO) 4.
Chapter 32 USART (LIN / FIFO) 4.USART Registers 4.
Chapter 32 USART (LIN / FIFO) 4.
Chapter 32 USART (LIN / FIFO) 4.USART Registers 4.
Chapter 32 USART (LIN / FIFO) 4.USART Registers Table 4-10 Functions of each bit of FIFO status Register Bit name Function bit 0 FIFO: number of valid Data • shows the number of valid FIFO - Data for RX and TX Fifo, depending on selection bit. bit 1 FIFO: number of valid Data • shows the number of valid FIFO - Data for RX and TX Fifo, depending on selection bit. bit 2 FIFO: number of valid Data • shows the number of valid FIFO - Data for RX and TX Fifo, depending on selection bit..
Chapter 32 USART (LIN / FIFO) 5.USART Interrupts 5. USART Interrupts The USART uses both reception and transmission interrupts. An interrupt request can be generated for either of the following causes: • Receive data is set in the Reception Data Register (RDR04), or a reception error occurs. • Transmission data is transferred from the Transmission Data Register (TDR04) to the transmission shift register.
Chapter 32 USART (LIN / FIFO) 5.USART Interrupts • - Framing error, i. e. a stop bit was expected, but a "0"-bit was received: FRE • - Parity error, i. e. a wrong parity bit was detected: PE If at least one of these flag bits above go "1" and the reception interrupt is enabled (SSR04: RIE = 1), a reception interrupt request is generated. If the Reception Data Register (RDR04) is read, the RDRF flag is automatically cleared to "0". Note that this is the only way to reset the RDRF flag.
Chapter 32 USART (LIN / FIFO) 5.USART Interrupts Figure 5-1 Bus idle interrupt generation Transmission data Reception data TBI RBI Reception IRQ : Start bit : Stop bit : Data bit 5.1 Reception Interrupt Generation and Flag Set Timing The following are the reception interrupt causes: Completion of reception (SSR04: RDRF) and occurrence of a reception error (SSR04: PE, ORE, or FRE).
Chapter 32 USART (LIN / FIFO) 5.USART Interrupts (Note) "7p1" and "8N1" (p = "E" [even] or "O" [odd]), all in NRZ data format (ECCR04: INV = 0). **ORE only occurs, if the reception data is not read by the CPU (RDRF = 1) and another data frame is read. Figure 5-3 ORE set timing Receive data RDRF ORE 5.2 Transmission Interrupt Generation and Flag Set Timing A transmission interrupt is generated when the next data to be sent is ready to be written to the output data register (TDR04).
Chapter 32 USART (LIN / FIFO) 6.USART Baud Rates ■ Transmission Interrupt Request Generation Timing If the TDRE flag is set to 1 when a transmission interrupt is enabled (SSR04: TIE=1) a transmission interrupt request is generated. A transmission completion interrupt is generated immediately after the transmission interrupt is enabled (TIE=1) because the TDRE bit is set to 1 as its initial value. TDRE is a read-only bit that can be cleared only by writing new data to the output data register (TDR04).
Chapter 32 USART (LIN / FIFO) 6.
Chapter 32 USART (LIN / FIFO) 6.USART Baud Rates ■ Suggested Division Ratios for different machine speeds and baud rates The following settings are suggested for different MCU clock speeds and baud rates: Table 6-1 Suggested Baud Rates and reload values at different machine speeds. 8 MHz Baud rate 10 MHz 16 MHz 20 MHz 24 MHz 32 MHz value % dev. value % dev. value % dev. value % dev. value % dev. value % dev.
Chapter 32 USART (LIN / FIFO) 6.USART Baud Rates Figure 6-2 Counting example of the reload counters Transmission/ Reception Clock Reload Count 001 000 832 831 830 829 828 827 413 412 411 410 reload count value Transmission/ Reception Clock Reload Count (Note) 417 416 415 414 The falling edge of the Serial Clock Signal always occurs after | (v + 1) / 2 |. 6.
Chapter 32 USART (LIN / FIFO) 6.USART Baud Rates Figure 6-3 Reload Counter Restart example MCU Clock Reload Counter Clock Outputs REST Reload Value 37 36 35 100 99 98 97 96 95 94 93 92 91 90 89 88 87 Read BGR0/1 Data Bus 90 : don’t care In this example the number of MCU clock cycles (cyc) after REST is then: cyc = v - c + 1 = 100 - 90 + 1 = 11, where v is the reload value and c is the read counter value.
Chapter 32 USART (LIN / FIFO) 7.USART Operation 7. USART Operation USART operates in operation mode 0 for normal bidirectional serial communication, in mode 2 and 3 in bidirectional communication as master or slave, and in mode 1 as master or slave in multiprocessor communication. ■ Operation of USART • Operation modes There are four USART operation modes: modes 0 to 3. As listed in table 7-1, an operation mode can be selected according to the inter-CPU connection method and data transfer mode.
Chapter 32 USART (LIN / FIFO) 7.USART Operation TXE) and reception (SCR04: RXE). If each of the operations is disabled, stop it as follows: • If reception operation is disabled during reception (data is input to the reception shift register), finish frame reception and read the received data of the reception data register (RDR04). Then stop the reception operation.
Chapter 32 USART (LIN / FIFO) 7.USART Operation If transmission interrupt is enabled (TIE = 1), the interrupt is generated by the TDRE flag. Note, that the initial value of the TDRE flag is "1", so that in this case if TIE is set to "1" an interrupt will occur immediately. ■ Reception Operation Reception operation is performed every time it is enabled by the Reception Enable (RXE) flag bit of the SCR04. If a start bit is detected, a data frame is received according to the format specified by the SCR04.
Chapter 32 USART (LIN / FIFO) 7.USART Operation ■ Transfer data format In the synchronous mode, 8-bit data is transferred with no start or stop bits if the SSM bit of the Extended Communication Control Register (ECCR04) is 0. A special clock signal belongs to the data format in mode 2. The figure below illustrates the data format during a transmission in the synchronous operation mode.
Chapter 32 USART (LIN / FIFO) 7.USART Operation SPI). This will make sure, that the transmission data is valid and stable at any falling clock edge. (Necessary, if the receiving device samples the data at falling clock edge). This function is disabled when CCO is enabled. If the Serial Clock Edge Select (SCES) bit of the ESCR is set, the USARTs clock is inverted and thus samples the reception data at the falling clock edge.
Chapter 32 USART (LIN / FIFO) 7.
Chapter 32 USART (LIN / FIFO) 7.USART Operation LIN break Interrupt is enabled (LBIE = 1) USART will generate a reception interrupt, if a synchronization break of the LIN master is detected, and indicates it with the LBD flag of the ESCR04. Writing a "0" to this bit clears the interrupt. The next step is to analyze the baud rate of the LIN master. The first falling edge of the Synch Field is detected by USART.
Chapter 32 USART (LIN / FIFO) 7.
Chapter 32 USART (LIN / FIFO) 7.USART Operation 7.5 Bidirectional Communication Function (Normal Mode) In operation mode 0 or 2, normal serial bidirectional communication is available. Select operation mode 0 for asynchronous communication and operation mode 2 for synchronous communication. ■ Bidirectional Communication Function The settings shown in figure 7-8 are required to operate USART in normal mode (operation mode 0 or 2).
Chapter 32 USART (LIN / FIFO) 7.USART Operation ■ Master-slave Communication Function The settings shown in figure 7-10 are required to operate USART in multiprocessor mode (operation mode 1).
Chapter 32 USART (LIN / FIFO) 7.
Chapter 32 USART (LIN / FIFO) 7.USART Operation Figure 7-12 Master-slave communication flowchart (Master CPU) (Slave CPU) Start Start Set operation mode 1 Set operation mode 1 Set SIN pin as the serial data input pin. Set SOT pin as the serial data output pin. Set SIN pin as the serial data input pin. Set SOT pin as the serial data output pin. Set 7 or 8 data bits. Set 1 or 2 stop bits. Set 7 or 8 data bits. Set 1 or 2 stop bits. Set “1” in AD bit Set TXE = RXE = 1. Set TXE = RXE = 1.
Chapter 32 USART (LIN / FIFO) 7.USART Operation 7.7 LIN Communication Function USART communication with LIN devices is available for both LIN master or LIN slave systems. ■ LIN-Master-Slave Communication Function The settings shown in the figure below are required to operate USART in LIN communication mode (operation mode 3).
Chapter 32 USART (LIN / FIFO) 7.USART Operation ■ USART as master device Figure 7-15 USART LIN master flow chart START Initialization: Set Operat. mode 3 (8N1 data format) TIE = 0, RIE = 0 Send Message? N Y Send Sleep Mode TDR = 0x80 TIE = 0 Send Synch Break: write "1" to ECCR: LBR; TIE = 1; Send Synch Field: TDR = 0x55 Wake up from CPU? TDRE = 1 Transm.
Chapter 32 USART (LIN / FIFO) 7.USART Operation ■ USART as slave device Figure 7-16 USART LIN slave flow chart (part1) START A B Initialization: Set Operat. mode 3 (8N1 data format) Slave address N match? Errors occurred? Y C C Y E N RIE = 0; LBIE = 1; RXE = 0 Master wants to N send data? waiting (slave action) Y LBD = 1 LIN break interrupt Awaiting message from LIN master. Write "0" to LBD to clear interrupt.
Chapter 32 USART (LIN / FIFO) 7.
Chapter 32 USART (LIN / FIFO) 8.Notes on using USART 8. Notes on using USART Notes on using USART are given below. ■ Enabling Operations In USART, the control register (SCR04) has TXE (transmission) and RXE (reception) operation enable bits. Both, transmission and reception operations, must be enabled before the transfer starts because they have been disabled as the default value (initial value).
Chapter 32 USART (LIN / FIFO) 8.Notes on using USART ■ Baud Rate Detection Using the Input Capture Units The USARTs provide the signal LSYN that can be connected to the ICU so that LSYN’s pulse length can be measured to derive the baud rate.
Chapter 33 I2C Controller 1.Overview Chapter 33 I2C Controller 1. Overview The I2C interface is a serial I/O port supporting the Inter IC bus, operating as a master/slave device on the I2C bus.
Chapter 33 I2C Controller 1.Overview ■ Block Diagram ICCR I2C enable EN R-Bus Clock (CLKP) ICCR Clock Divider 1 2 3 4 5 ...
Chapter 33 I2C Controller 2.I2C Interface Registers 2. I2C Interface Registers This section describes the function of the I2C interface registers in detail. ■ Bus Control Register (IBCR0) Bus control register 15 Address : 0000D0H 14 13 12 BER BEIE SCC MSS 11 10 9 ACK GCAA INTE 8 INT ⇐ Bit no.
Chapter 33 I2C Controller 2.I2C Interface Registers ■ Seven bit slave address MasK register (ISMK0) Seven Bit Address Mask register Address : 0000D6H 15 14 13 12 ENSB SM6 SM5 SM4 11 10 9 8 SM3 SM2 SM1 SM0 ⇐ Bit no.
Chapter 33 I2C Controller 2.I2C Interface Registers 2.1 Bus Control Register (IBCR0) The bus control register (IBCR0) has the following functions: • Interrupt enabling flags • Interrupt generation flag • Bus error detection flag • Repeated start condition generation • Master / slave mode selection • General call acknowledge generation enabling • Data byte acknowledge generation enabling Write access to this register should only occur while the INT=‘1’ or if a transfer is to be started.
Chapter 33 I2C Controller 2.I2C Interface Registers [bit 14] BEIE (Bus Error Interrupt Enable) This bit enables the bus error interrupt. It can only be changed by the user. 0 Bus error interrupt disabled. 1 Bus error interrupt enabled. Setting this bit to ‘1’ enables MCU interrupt generation when the BER bit is set to ‘1’. [bit 13] SCC (Start Condition Continue) This bit is used to generate a repeated start condition. It is write only - it always reads ‘0’. 0 No effect.
Chapter 33 I2C Controller 2.I2C Interface Registers This bit is not valid when receiving address bytes in slave mode - if the interface detects its 7 or 10 bit slave address, it will acknowledge if the corresponding enable bit (ENTB in ITMK0 or ENSB in ISMK0) is set.
Chapter 33 I2C Controller 2.I2C Interface Registers While this bit is ‘1’ the SCL line will hold an ‘L’ level signal. Writing ‘0’ to this bit clears the setting, releases the SCL line, and executes transfer of the next byte or a repeated start or stop condition is generated. Additionally, this bit is cleared if a ‘1’ is written to the SCC bit or the MSS bit is being cleared.
Chapter 33 I2C Controller 2.I2C Interface Registers 2.2 Bus Status Register (IBSR0) The bus status register (IBSR0) has the following functions: • Bus busy detection • Repeated start condition detection • Arbitration loss detection • Acknowledge detection • Data transfer direction indication • Addressing as slave detection • General call address detection • Address data transfer detection This register is read-only, all bits are controlled by the hardware.
Chapter 33 I2C Controller 2.I2C Interface Registers • a repeated start condition is generated by another master in the first bit of a data byte • the interface could not generate a start or stop condition because another slave pulled the SCL line low before [bit 4] LRB (Last Received Bit) This bit is used to store the acknowledge message from the receiving side at the transmitter side. 0 Receiver acknowledged. 1 Receiver did not acknowledge.
Chapter 33 I2C Controller 2.I2C Interface Registers 1 General call address received as slave. This bit is cleared by a (repeated-) start or stop condition. [bit 0] ADT (Address Data Transfer) This bit indicates the detection of an address data transfer. 0 Incoming data is not address data (or bus is not in use). 1 Incoming data is address data. This bit is set to ‘1’ by a start condition.
Chapter 33 I2C Controller 2.I2C Interface Registers 2.3 Ten Bit Slave Address Register (ITBA0) This register (ITBAH0 / ITBAL0) designates the ten bit slave address. Write access to this register is only possible if the interface is disabled (EN=‘0’ in ICCR0).
Chapter 33 I2C Controller 2.I2C Interface Registers 2.4 Ten Bit Address Mask Register (ITMK0) This register contains the ten bit slave address mask and the ten bit slave address enable bit.
Chapter 33 I2C Controller 2.I2C Interface Registers IBSR0 register is ‘1’. Note: If the address mask is changed after the interface had been enabled, the slave address should also be set again since it could have been overwritten by a previously received slave address.
Chapter 33 I2C Controller 2.I2C Interface Registers 2.5 Seven Bit Slave Address Register (ISBA0) This register designates the seven bit slave address. Write access to this register is only possible if the interface is disabled (EN=‘0’ in ICCR0). Seven Bit Address register Address : 0000D7H Read/write ⇒ Default value⇒ 7 6 --- SA6 (-) (0) 5 4 SA5 SA4 3 2 SA3 SA2 1 0 SA1 SA0 ⇐ Bit no. ISBA0 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) [bit 7] Not used.
Chapter 33 I2C Controller 2.I2C Interface Registers 2.6 Seven Bit Slave Address Mask Register (ISMK0) This register contains the seven bit slave address mask and the seven bit mode enable bit. Write access to this register is only possible if the interface is disabled (EN=‘0’ in ICCR0). Seven Bit Address Mask register Address : 0000D6H 15 14 13 12 ENSB SM6 SM5 SM4 11 10 9 8 SM3 SM2 SM1 SM0 ⇐ Bit no.
Chapter 33 I2C Controller 2.I2C Interface Registers 2.7 Data Register (IDAR0) Data register Address : 0000D9H Read/write ⇒ Default value⇒ 7 6 5 4 3 2 1 0 ⇐ Bit no. D7 D6 D5 D4 D3 D2 D1 D0 IDAR0 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) [bit 15] - [bit 8] Not used. These bits always read ‘0’. [bit 7] - [bit 0] Data bits (D7-D0) The data register is used in serial data transfer, and transfers data MSB-first.
Chapter 33 I2C Controller 2.I2C Interface Registers 2.8 Clock Control Register (ICCR0) The clock control register (ICCR0) has the following functions: • Enable IO pad noise filters • Enable I2C interface operation • Setting the serial clock frequency Clock Control register Address : 0000DAH Read/write ⇒ Default value⇒ 15 14 13 12 --- NSF EN CS4 (-) (0) 11 10 CS3 CS2 9 8 CS1 CS0 ⇐ Bit no. ICCR0 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (1) (1) (1) (1) (1) [bit 15] Not used.
Chapter 33 I2C Controller 2.I2C Interface Registers Bitrate = (Note) φ n*12 + 19 (+1) Noise filter enabled n>0; φ : R-Bus clock CLKP (set by DIVR0 register) (+1): Unaccurancy caused by noise filter operation Because of the noise filter (depending on relationship between external signal and internal clock it will cause different delays ) the divider in the second formula can vary between (12n + 19) and (12n + 20).
Chapter 33 I2C Controller 2.I2C Interface Registers ■ SCL Waveforms Figure 2-1 SCL Waveforms Address sending 9 6 7 5 7 5 Data sending 9 7 5 7 5 7 Time unit: Prescaler cycles Figure 2-1 shows the SCL waveform for sending of address and data bits. The timings given in the figure are prescaler periods (e.g. ‘9’ means 9 times the prescaler count based on the R-Bus clock). The timings in the figure are only valid if no other device on the I2C bus influences the SCL timing.
Chapter 33 I2C Controller 3.I2C Interface Operation 3. I2C Interface Operation The I2C bus executes communication using two bi-directional bus lines, the serial data line (SDA) and serial clock line (SCL). The I2C interface has two open-drain I/O pins (SDA/SCL) corresponding to these lines, enabling wired logic applications. ■ Start Conditions When the bus is free (BB=‘0’ in IBSR0, MSS=‘0’ in IBCR2), writing ‘1’ to the MSS bit places the I2C interface in master mode and generates a start condition.
Chapter 33 I2C Controller 3.I2C Interface Operation ■ Slave Address Masking Only the bits set to ‘1’ in the mask registers (ITMK0 / ISMK0) are used for address comparision, all other bits are ignored. The received slave address can be read from the ITBA0 (if ten bit address received, RAL=‘1’) or ISBA0 (if seven bit address received, RAL=‘0’) register if the AAS bit in the IBSR0 register is ‘1’.
Chapter 33 I2C Controller 4.Programming Flow Charts 4. Programming Flow Charts ■ Example Of Slave Addressing And Sending Data Addressing a 7 bit slave Sending data Start Start Address slave for write Clear BER bit (if set); Enable Interface EN:=1; IDAR0 := Data Byte; INT := 0 IDAR0 := sl.
Chapter 33 I2C Controller 4.
Chapter 33 I2C Controller 4.
Chapter 33 I2C Controller 4.
Chapter 34 CAN Controller 1.Overview Chapter 34 CAN Controller 1. Overview The CAN performs communication according to the CAN protocol version 2.0 part A and B. The bit rate can be programmed to values up to 1MBit/s. For the connection to the physical layer additional transceiver hardware is required. ■ The CAN implements the following features: • Supports CAN protocol version 2.
Chapter 34 CAN Controller 2.Register Description 2. Register Description This section lists the CAN registers and describes the function of each register in detail. 2.1 Programmer’s Model The CAN module allocates an address space of 256 bytes (64 words). The CAN registers can be accessed from the CPU in byte, halfword and word. The two sets of interface registers (IF1 and IF2) control the CPU access to the Message RAM.
Chapter 34 CAN Controller 2.Register Description Register Address Note +0 Base-addr + 0x10 +1 IF1 Command Request +3 IF1 Command Mask bit[15:8] bit[7:0] bit[15:8] bit[7:0] Busy Mess. No. [5:0] reserved see descr.
Chapter 34 CAN Controller 2.Register Description Register Address Note +0 Base-addr + 0x40 +1 IF2 Command Request IF2 Command Mask bit[7:0] bit[15:8] bit[7:0] Busy Mess. No. [5:0] reserved see descr.
Chapter 34 CAN Controller 2.Register Description Register Address Note +0 Base-addr + 0x80 +1 +2 +3 Transmission Request Register 2 Transmission Request Register 1 bit[15:8] bit[7:0] bit[15:8] bit[7:0] TxRqst[32-25] TxRqst[24-17] TxRqst[16-9] TxRqst[8-1] Reset: 0x00 Reset: 0x00 Reset: 0x00 Reset: 0x00 Base-addr + 0x84 Transmission Request Register is read only. Reserved ( >32..128 Message buffer) Base-addr + 0x90 New Data 2 New Data 1 New Data is read only.
Chapter 34 CAN Controller 2.Register Description Additionally the busoff state is reset and the output CAN_TX is set to recessive(HIGH). The value 0x0001 (Init = ‘1’) in the CAN Control Register enables the software initialisation. The CAN does not influence the CAN bus until the CPU resets Init to ‘0’. The data stored in the Message RAM is not affected by a hardware reset. After power-on, the contents of the Message RAM is undefined. 2.
Chapter 34 CAN Controller 2.Register Description ■ Function of the CAN Control Register (CTRLR) [bit15 - bit8] [bit7] [bit6] Reserved Bits Test Test Mode Enable 0 1 Normal Operation. Test Mode. CCE 0 1 [bit5] DAR 0 1 Configuration Change Enable The CPU has no write access to the Bit Timing Register. The CPU has write access to the Bit Timing Register (while Init = 1) Disable Automatic Retransmission Automatic Retransmission of disturbed messages enabled. Automatic Retransmission disabled.
Chapter 34 CAN Controller 2.Register Description (Note) recovery sequence, the Error Management Counters will be reset. During the waiting time after the resetting of Init, each time a sequence of 11 recessive bits has been monitored, a Bit0Error code is written to the Status Register, enabling the CPU to readily check up whether the CAN bus is stuck at dominant or continuously disturbed and to monitor the proceeding of the busoff recovery sequence.
Chapter 34 CAN Controller 2.Register Description ■ Function of the Status Register (STATR) [bit15 - bit8] [bit7] Reserved Bits BOff 0 1 [bit6] EWarn 0 1 [bit5] EPass 0 1 [bit4] RxOk 0 1 [bit3] TxOk 0 1 [bit2 - bit0] LEC Busoff Status The CAN module is not busoff. The CAN module is in busoff state. Warning Status oth error counters are below the error warning limit of 96. At least one of the error counters in the EML has reached the error warning limit of 96.
Chapter 34 CAN Controller 2.Register Description 5 Bit0Error During the transmission of a message (or acknowledge bit or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value ‘0’), but the monitored Bus value was recessive. During busoff recovery this status is set each time a sequence of 11 recessive bits has been monitored.
Chapter 34 CAN Controller 2.Register Description ■ Function of the Error Counter (ERRCNT) [bit15] RP 0 1 [bit14 - bit8] REC6-0 Receive Error Passive The Receive Error Counter is below the error passive level. The Receive Error Counter has reached the error passive level as defined in the CAN Specification. Receive Error Counter Actual state of the Receive Error Counter. Values between 0 and 127. [bit7 - bit0] TEC7-0 Transmit Error Counter Actual state of the Transmit Error Counter.
Chapter 34 CAN Controller 2.Register Description ■ Function of the Bit Timing Register (BTR) [bit15] res [bit14 - bit12] TSeg2 The time segment after the sample point 0x0-0x7 Valid values for TSeg2 are [ 0 … 7 ]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.
Chapter 34 CAN Controller 2.Register Description ■ Function of the Test Register (TESTR) [bit15-bit8] res Reserved bits [bit7] Rx Monitors the actual value of the CAN_RX Pin 0 1 [bit6-bit5] Tx1-0 00 01 10 11 [bit4] LBack 0 1 [bit3] Silent 0 1 [bit2] Basic 0 1 [bit1-bit0] res The CAN bus is dominant (CAN_RX = ‘0’). The CAN bus is recessive (CAN_RX = ‘1’). Control of CAN_TX pin Reset value, CAN_TX is controlled by the CAN Core. Sample Point can be monitored at CAN_TX pin.
Chapter 34 CAN Controller 2.
Chapter 34 CAN Controller 2.
Chapter 34 CAN Controller 2.Register Description ■ Function of the IFx Command Request Registers (IFxCREQ) [bit15] BUSY 0 1 [bit14-bit8] res [bit5-bit0] [bit7-bit0] Reserved Bits Not a valid Message Number, interpreted as 0x20. Valid Message Number, the Message Object in the Message RAM is selected for data transfer. Not a valid Message Number, interpreted as 0x01-0x1F.
Chapter 34 CAN Controller 2.Register Description ■ Function of the IFx Command Mask Register (IFxCMSK) [bit15-bit8] res [bit7] WR/RD 0 1 Reserved Bits Write / Read Read: Transfer data from the Message Object addressed by the Command Request Register into the selected Message Buffer Registers. Write: Transfer data from the selected Message Buffer Registers to the Message Object addressed by the Command Request Register.
Chapter 34 CAN Controller 2.Register Description 0 1 (Note) Data Bytes 4-7 unchanged. Transfer Data Bytes 4-7 to Message Object. If a transmission is requested by programming bit TxRqst/NewDat in the IFx Command Mask Register, bit TxRqst in the IFx Message Control Register will be ignored. • Direction = Read [bit6] Mask 0 1 [bit5] Arb 0 1 [bit4] Control 0 1 [bit3] CIP 0 1 [bit2] TxReq/ NewDat 0 1 [bit1] Data A 0 1 [bit0] Data B 0 1 (Note) Access Mask Bits Mask bits unchanged.
Chapter 34 CAN Controller 2.Register Description IFx Mask 2 Register high byte 15 14 13 12 11 10 9 8 res Msk28-24 Read/write ⇒ (R/W) (R/W) (1) (1) Default value⇒ (R) (1) (R/W) (R/W) (R/W) (R/W) (R/W) (1) (1) (1) (1) (1) IFx Mask 2 Register low byte Address : Base + 0x15H & Base + 0x45H Read/write ⇒ Default value⇒ IFx Mask 1 Register high byte 7 6 5 4 3 2 ⇐ Bit no. IFxMSK2H MXtd MDir Address : Base + 0x14H & Base + 0x44H 1 0 ⇐ Bit no.
Chapter 34 CAN Controller 2.Register Description IFx Arbitration 1 Register high byte 15 14 13 12 11 10 9 ⇐ Bit no. 8 IFxARB1H ID15-8 Address : Base + 0x1AH & Base + 0x4AH Read/write ⇒ (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) Default value⇒ 7 IFx Arbitration 1 Register low byte Address : Base + 0x1BH & Base + 0x4BH Read/write ⇒ Default value⇒ 6 5 4 3 2 1 ⇐ Bit no.
Chapter 34 CAN Controller 2.Register Description 2.5 Message Object in the Message Memory There are 32 Message Objects (up to 128 depending on the implementation) in the Message RAM. To avoid conflicts between CPU access to the Message RAM and CAN message reception and transmission, the CPU cannot directly access the Message Objects, these accesses are handled via the IFx Interface Registers. Figure 2-4 gives an overview of the two structures of a Message Object.
Chapter 34 CAN Controller 2.Register Description 1 MXtd 0 1 (Note) Dir 0 1 MDir 0 1 The 29-bit (“extended”) Identifier will be used for this Message Object. Mask Extended Identifier The extended identifier bit (IDE) has no effect on the acceptance filtering The extended identifier bit (IDE) is used for acceptance filtering. When 11-bit (“standard”) Identifiers are used for a Message Object, the identifiers of received Data Frames are written into bits ID28 to ID18.
Chapter 34 CAN Controller 2.Register Description MsgLst 0 1 RxIE 0 1 TxIE 0 1 IntPnd 0 1 RmtEn 0 1 TxRqst 0 1 DLC3-0 0-8 9-15 (Note) Data 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Message Lost (only valid for Message Objects with direction = receive) No message lost since last time this bit was reset by the CPU. The Message Handler stored a new message into this object when NewDat was still set, the CPU has lost a message.
Chapter 34 CAN Controller 2.Register Description (Note) Byte Data 0 is the first data byte shifted into the shift register of the CAN Core during a reception, byte Data 7 is the last. When the Message Handler stores a Data Frame, it will write all the eight data bytes into a Message Object. If the Data Length Code is less than 8, the remaining bytes of the Message Object will be overwritten by non specified values. 2.6 Message Handler Registers All Message Handler registers are read-only.
Chapter 34 CAN Controller 2.Register Description 0x80010xFFFF unused. If several interrupts are pending, the CAN Interrupt Register will point to the pending interrupt with the highest priority, disregarding their chronological order. An interrupt remains pending until the CPU has cleared it. If IntId is different from 0x0000 and IE is set, the interrupt line to the CPU is active.
Chapter 34 CAN Controller 2.
Chapter 34 CAN Controller 2.Register Description These registers hold the NewDat bits of the 32 Message Objects. By reading out the NewDat bits, the CPU can check for which Message Object the data portion was updated. The NewDat bit of a specific Message Object can be set/reset by the CPU via the IFx Message Interface Registers or by the Message Handler after reception of a Data Frame or after a successful transmission.
Chapter 34 CAN Controller 2.Register Description 1 This message object is the source of an interrupt. These registers hold the IntPnd bits of the 32 Message Objects. By reading out the IntPnd bits, the CPU can check for which Message Object an interrupt is pending. The IntPnd bit of a specific Message Object can be set/reset by the CPU via the IFx Message Interface Registers or by the Message Handler after reception or after a successful transmission of a frame.
Chapter 34 CAN Controller 2.Register Description MsgVal32-1 0 1 Message Valid Bits (of all Message Objects) This Message Object is ignored by the Message Handler. This Message Object is configured and should be considered by the Message Handler. These registers hold the MsgVal bits of the 32 Message Objects. By reading out the MsgVal bits, the CPU can check which Message Object is valid. The MsgVal bit of a specific Message Object can be set/reset by the CPU via the IFx Message Interface Registers.
Chapter 34 CAN Controller 3.Functional Description 3. Functional Description This chapter provides an overview of the CAN module’s operating modes and how to use them. 3.1 Software Initialisation The software initialization is started by setting the bit Init in the CAN Control Register, either by software or by a hardware reset, or by going Bus_Off. While Init is set, all message transfers from and to the CAN bus are stopped, the status of the CAN bus output CAN_TX is recessive (HIGH).
Chapter 34 CAN Controller 3.Functional Description Automatic Retransmission mode is enabled by setting the bit DAR in the CAN Control Register to one. In this operation mode the programmer has to consider the different behaviour of bits TxRqst and NewDat in the Control Registers of the Message Buffers: When a transmission starts bit TxRqst of the respective Message Buffer is reset, while bit NewDat remains set. When the transmission completed successfully bit NewDat is reset.
Chapter 34 CAN Controller 3.Functional Description Figure 3-2 CAN Core in Loop Back Mode This mode is provided for self-test functions. To be independent from external stimulation, the CAN Core ignores acknowledge errors (recessive bit sampled in the acknowledge slot of a data/remote frame) in Loop Back Mode. In this mode the CAN Core performs an internal feedback from its Tx output to its Rx input. The actual value of the CAN_RX input pin is disregarded by the CAN Core.
Chapter 34 CAN Controller 3.Functional Description The IF1 Registers are used as Transmit Buffer. The transmission of the contents of the IF1 Registers is requested by writing the Busy bit of the IF1 Command Request Register to ‘1’. The IF1 Registers are locked while the Busy bit is set. The Busy bit indicates that the transmission is pending. As soon as the CAN bus is idle, the IF1 Registers are loaded into the shift register of the CAN Core and the transmission is started.
Chapter 34 CAN Controller 4.CAN Application 4. CAN Application This section describes how to use the CAN module in the application 4.1 Management of Message Objects The configuration of the Message Objects in the Message RAM will (with the exception of the bits MsgVal, NewDat, IntPnd, and TxRqst) not be affected by resetting the chip.
Chapter 34 CAN Controller 4.CAN Application Figure 4-1 Data Transfer between IFx Registers and Message RAM After the partial write of a Message Object, that Message Buffer Registers that are not selected in the Command Mask Register will set to the actual contents of the selected Message Object. After the partial read of a Message Object, that Message Buffer Registers that are not selected in the Command Mask Register will be left unchanged. 4.
Chapter 34 CAN Controller 4.CAN Application 4.5 Acceptance Filtering of Received Messages When the arbitration and control field (Identifier + IDE + RTR + DLC) of an incoming message is completely shifted into the Rx/Tx Shift Register of the CAN Core, the Message Handler FSM starts the scanning of the Message RAM for a matching valid Message Object. To scan the Message RAM for a matching Message Object, the Acceptance Filtering unit is loaded with the arbitration bits from the CAN Core shift register.
Chapter 34 CAN Controller 4.CAN Application MsgVal Arb Data Mask Eo B Dir NewDat MsgLst RxI E TxIE IntPnd RmtEn TxRqst 1 appl. appl. appl. 1 1 0 0 0 appl. 0 appl. 0 Figure 4-2 Initialisation of a Transmit Object The Arbitration Registers (ID28-0 and Xtd bit) are given by the application. They define the identifier and type of the outgoing message. If an 11-bit Identifier (“Standard Frame”) is used, it is programmed to ID28 - ID18, ID17 - ID0 can then be disregarded.
Chapter 34 CAN Controller 4.CAN Application ID18, ID17 - ID0 can then be disregarded. When a Data Frame with an 11-bit Identifier is received, ID17 - ID0 will be set to ‘0’. If the RxIE bit is set, the IntPnd bit will be set when a received Data Frame is accepted and stored in the Message Object. The Data Length Code (DLC3-0) is given by the application. When the Message Handler stores a Data Frame in the Message Object, it will store the received Data Length Code and eight data bytes.
Chapter 34 CAN Controller 4.CAN Application 4.15 Reading from a FIFO Buffer When the CPU transfers the contents of Message Object to the IFx Message Buffer registers by writing its number to the IFx Command Request Register, the corresponding Command Mask Register should be programmed the way that bits NewDat and IntPnd are reset to zero (TxRqst/NewDat = ‘1’ and ClrIntPnd = ‘1’). The values of these bits in the Message Control Register always reflect the status before resetting the bits.
Chapter 34 CAN Controller 4.CAN Application The Status Interrupt has the highest priority. Among the message interrupts, the Message Object’ s interrupt priority decreases with increasing message number. A message interrupt is cleared by clearing the Message Object’s IntPnd bit. The Status Interrupt is cleared by reading the Status Register. The interrupt identifier IntId in the Interrupt Register indicates the cause of the interrupt. When no interrupt is pending, the register will hold the value zero.
Chapter 34 CAN Controller 4.CAN Application Figure 4-5 Bit Timing Parameter Range Remark BRP [1..32] defines the legth of the time quantum tq Sync_Seg 1 tq Prop_Seg [1..8] tq compensates for the physical delay times Phase_Seg1 [1..8] tq may be lengthened temporarily by synchronisation Phase_Seg2 [1..8] tq may be shortened temporarily by synchronisation SJW [1..
Chapter 34 CAN Controller 4.
Chapter 35 Free-Run Timer 1.Overview Chapter 35 Free-Run Timer 1. Overview The free-run timer consists of a 16-bit timer (up counter) and control circuits. The free-run timer can be used with the input capture and the output compare. Internal clock or External clock Clear Up counter Overflow 2.
Chapter 35 Free-Run Timer 3.Configuration Diagram 3. Configuration Diagram Figure 3-1 Configuration Diagram Free-run Timer Count clock 0 0 1 1 CLK1-0 0 1 0 1 TCCS: bit 1-0 CLKP / 4 CLKP / 16 CLKP / 32 CLKP / 64 STOP 0 1 TCCS: bit 4 Input capture IVFE Count operation Stop the count operation 0 1 Count value 0 Overflow flag 0 Peripheral clock C LKP Timer data register Divider IVF TCDT Synchronization circuit CK /SCK/ Pxy.
Chapter 35 Free-Run Timer 4.Registers 4. Registers 4.1 TCCS: Timer Control Register • • • • • • • • A register for controlling the operation of the free-run timer.
Chapter 35 Free-Run Timer 4.Registers • bit4: Stop counting STOP 0 1 Operation Enable counting Disable count (stop) • When the count stop bit is set to “1”, the free-run timer stops. • When the output compare is being used, if the free-run timer stops, the output compare also stops.
Chapter 35 Free-Run Timer 4.Registers • bit3: Clear mode MODE Clear mode 0 Clear the free-run timer by the reset and the clear bit (CLR). 1 Clear the free-run timer by the match with the reset, the clear bit (CLR), and the compare register value of the output compare (OCCP). • Set the clear mode of the free-run timer.
Chapter 35 Free-Run Timer 4.Registers 4.2 TCDT: Timer Data Register This register can read 16-bit free-run timer count values.
Chapter 35 Free-Run Timer 5.Operation 5. Operation 5.
Chapter 35 Free-Run Timer 5.Operation 5.2 Various Clear Operations of the Free-run Timer The count of the free-run timer 0000 h (2) (3) (1) Time (4) Reset Write "0000" Clear Clear by software or the compare-match.
Chapter 35 Free-Run Timer 6.Setting 6. Setting Table 6-1 Setting Required in Order to Use the Free-run Timer Setting Setting of the initialization conditions of the timer Setting of the count clock Selection of the internal clock Selection of the external clock Start the count operation In the case of the external clock Set the clock input pin (CK) as the input. Setting Registers Timer control register (TCCS0-TCCS7) Setting Procedures * See 7.4 See 7.1 See 7.2 See 7.3 Port function register (PFRxy.
Chapter 35 Free-Run Timer 7.Q & A 7. Q & A 7.1 What are the types of the internal clock, and how do I select? There are 4 types of internal clocks, and these are set by the clock selection bit (TCCS.ECLK) and the count clock bit (TCCS.CLK [1:0]). Setting Count period FCLKP = FCLKP = 16MHz 32MHz Internal clock Clock selection Bit (ECLK) Count clock bit (CLK [1:0]) To select FCLKP/4 Set to “0” Sets to “00” 125 ns 250 ns To select FCLKP/16 Set to “0” Set to “01” 0.
Chapter 35 Free-Run Timer 7.Q & A 7.4 How do I clear the free-run timer? You can clear the free-run timer by performing the following operations: • Set with clear bit (TCCS.CLR). Operation To clear the free-run timer Clear bit (CLR) Write “1” • How to clear the free-run timer when the free-run timer value and the compare-register value match Set with the timer initialization condition bit (TCCS.MODE).
Chapter 35 Free-Run Timer 7.Q & A Use interrupt request enable bit (TCCS.IVFE) to enable interrupts. Interrupt request permission bit (IVFE) Disable interrupts Enable interrupts Set to “0” Set to “1” Use interrupt request bit (TCCS.IVF) to clear interrupt requests. Clear interrupt requests Interrupt request bit (IVF) Write “0” 7.8 How do I stop the free-run timer? Set with count operation bit (TCCS.STOP). See “7.3 How do I enable / disable the count operation of the free-run timer? (Page No.742)”. 7.
Chapter 35 Free-Run Timer 8.Caution 8. Caution • Clearing the free-run timer • When you reset (the INIT pin input, the watchdog reset, the software reset), the counter is initialized to “0000” and the counting is stopped. • When the free-run timer is cleared by software, the counter is cleared and the clear request is generated almost at the same time. If the counter is cleared by the compare-match, it is cleared when it is counted up.
Chapter 35 Free-Run Timer 8.
Chapter 36 Input Capture 1.Overview Chapter 36 Input Capture 1. Overview Input Capture records the free-run timer count value using timing detected from an external signal. It is then possible to calculate the time between signals using the record of the repeated count. Free-run timer 0 pin Edge detection circuit Capture Buffer 2.
Chapter 36 Input Capture 3.Configuration 3. Configuration Figure 3-1 Configuration Diagram Input capture 0-1 Edge detection polarity From port data register EG01-00 ICS01:bit 1-0 0 0 No edge detection 0 1 Rising edge detection 1 0 Falling edge detection 1 1 Both edges detection P14 PFR: bit 0 GP Port 0 ICU input 1 ICE0 Capture data register 0 0 1 ICS01:bit 4 Disable interrupts Enable interrupts IPCP0 (CP15-CP0) Edge detection circuit ICU0 / P14.
Chapter 36 Input Capture 4.Register 4. Register 4.1 IPCP: Input Capture Data Register • • • • • • • • A register that, using changes in an external signal as a trigger, stores the free-run timer count and can read it out later.
Chapter 36 Input Capture 4.Register 4.
Chapter 36 Input Capture 4.Register • bit3-bit2: Input capture 1 active edge selection EG11 0 0 1 1 EG10 0 1 0 1 Edge selection Stop input capture Rising edge Falling edge Both edges (rising edge and falling edge) • Select the active capture edge for the input capture signal from external pin (ICU1) • If the active edge selection bit is “00”, input capture 1 is stopped.
Chapter 36 Input Capture 5.Operation 5. Operation The input capture operation is described below. 5.
Chapter 36 Input Capture 5.Operation 5.
Chapter 36 Input Capture 6.Settings 6. Settings Table 6-1 Settings Necessary for Using Input Capture Settings Free-run timer settings Free-run timer activation Input pin ICU0-ICU7 settings Active edge polarity selection for external input Setting register See “Chapter 35 Free-Run Timer (Page No.733)” Port function register (PFR14.0 - PFR14.7) Extra port function register (EPFR14.0 EPFR14.7) Input capture control register (ICS01, ICS23, ICS45, ICS67) Setting procedure* – 7.2 7.
Chapter 36 Input Capture 7.Q&A 7. Q&A 7.1 What are the varieties of active edge polarity for external input, and how do I select them? The active edge polarity varieties consist of rising, falling, and both, for a total of 3, and are set using the external input active edge selection bit (ICS01.EG[01:00]) and (ICS01:EG[11:10]), (ICS23.EG[01:00]) and (ICS23:EG[11:10]), (ICS45.EG[01:00]) and (ICS45:EG[11:10]), (ICS67.EG[01:00]) and (ICS67:EG[11:10]).
Chapter 36 Input Capture 7.Q&A Input Capture 6 #98 Address: 0FFE74h Input Capture 7 #99 Address: 0FFE70h Interrupt level register (ICR41) Address: 0469h Interrupt request flags (ICS01.ICP0), (ICS01.ICP1), (ICS23.ICP0), (ICS23.ICP1), (ICS45.ICP0), (ICS45.ICP1), (ICS67.ICP0), (ICS67.ICP1) are not automatically cleared, so please set the input capture interrupt request flag (ICP1, ICP0) to “0” to clear them before returning from interrupt processing. 7.
Chapter 36 Input Capture 7.Q&A 7.6 How do I measure the pulse width of the input signal? • "H" Width measurement: Specify both edges for edge detection. First detect the rising edge, then detect the falling edge.
Chapter 36 Input Capture 8.Caution 8. Caution • Input capture register The value of the input capture register during reset is indeterminate. Read out of the input capture register must always be done using 16 or 32 bit access. • Read modify write Input capture interrupt request bit (ICP0), (ICP1) will be read as “1” when read with read modify write.
Chapter 37 Output Compare 1.Overview Chapter 37 Output Compare 1. Overview Output compare is a feature that compares the value set to the compare register with the count value of the free-run timer, and reverses the level of the pins when they are equal. Pin 0 0 Match Compare00 Compare Latch Toggle Output Clear Free-run Timer Latch Pin 1 1 Compare Compare11 Match 2. Features • Output wave form: Toggle output 4 channel Trigger output 4 channel T1 or T(max.
Chapter 37 Output Compare 3.Configuration Diagram 3.
Chapter 37 Output Compare 4.Registers 4. Registers 4.1 OCS: Output Control Register A register for controlling the operation of output compare.
Chapter 37 Output Compare 4.Registers • bit7: Interrupt request flag (output compare 1) ICP1 0 1 Status Read Interrupt request not present Interrupt request present Write Clear flag (ICP1) No effect on operation • If free-run timer count value TCDT0 matches the output compare register OCCP1, ICP1 becomes “1”. • Interrupt request is enabled when the interrupt permission bit (ICP1) is set to “1”.
Chapter 37 Output Compare 4.Registers • bit0: Enable operation requests (output compare 0) CST0 0 1 Operation Disable output compare 0 operation Enable output compare 0 operation • A bit that enables a comparison operation between the free-run timer count value and the output compare register (TCDT0 and OCCP0). • Before enabling the operation, always set a value to compare register OCCP0. • If you stop the free-run timer, output compare also stops.
Chapter 37 Output Compare 4.Registers 4.2 OCCP: Compare Register • • • • • • • • Register that sets the value to be compared to the 16 bit free-run timer count value.
Chapter 37 Output Compare 5.Operation 5. Operation 5.
Chapter 37 Output Compare 5.Operation 5.
Chapter 37 Output Compare 6.Settings 6. Settings Table 6-1 Settings Necessary for Using Output Compare Settings Free-run timer setting Compare value setting Setting Register See “Chapter 35 Free-Run Timer (Page No.733)” Compare register (OCCP0 - OCCP7) Compare mode setting Stop compare operation Set initial level of compare pin output Set OCU0-OCU7 pins to output Clear free-run timer Enable compare operation (activate) Output control register (OCS01, OCS23, OCS45, OCS67) Port function register (PFR15.
Chapter 37 Output Compare 7.Q & A 7. Q & A 7.1 How do I set the compare value? Write the compare value to compare registers OCCP0 - OCCP7. 7.2 How do I set the compare mode? (for OCU1, OCU3, OCU5, OCU7 output) This is done using compare mode bits (OCS01.CMOD), (OCS23.CMOD), (OCS45.CMOD), (OCS67.CMOD).
Chapter 37 Output Compare 7.Q & A To enable compare operation Compare 0 Compare 1 Compare 2 Compare 3 Compare 4 Compare 5 Compare 6 Compare 7 Set (OCS01.CST[0]) to “1” Set (OCS01.CST[1]) to “1” Set (OCS23.CST[0]) to “1” Set (OCS23.CST[1]) to “1” Set (OCS45.CST[0]) to “1” Set (OCS45.CST[1]) to “1” Set (OCS67.CST[0]) to “1” Set (OCS67.CST[1]) to “1” 7.4 How do I set the initial level of the compare pin output? Set it with compare pin output specification bit (OCS01.OTD[1:0]), (OCS23.OTD[1:0]), (OCS45.
Chapter 37 Output Compare 7.Q & A 7.5 How do I set the output for compare pins OCU0-OCU7? Set it with port function register (PFR15[7:0]). Operation To set compare 0 pin (OCU0) to output To set compare 1 pin (OCU1) to output To set compare 2 pin (OCU2) to output To set compare 3 pin (OCU3) to output To set compare 4 pin (OCU4) to output To set compare 5 pin (OCU5) to output To set compare 6 pin (OCU6) to output To set compare 7 pin (OCU7) to output Port function bit Set PFR15.0 bit to “1” Set PFR15.
Chapter 37 Output Compare 7.Q & A Output Compare 2 #102 Address: 0FFE64h Output Compare 3 #103 Address: 0FFE60h Output Compare 4 Output Compare 5 Output Compare 6 #104 Address: 0FFE5Ch #105 Address: 0FFE58h #106 Address: 0FFE54h Output Compare 7 #107 Address: 0FFE50h Interrupt level register (ICR43) Address: 046Bh Interrupt level register (ICR44) Address: 046Ch Interrupt level register (ICR45) Address: 046Dh Interrupt request flags (OCS01. ICP[1:0]), (OCS23. ICP[1:0]), (OCS45. ICP[1:0]), (OCS67.
Chapter 37 Output Compare 7.Q & A 7.11 How do I enable interrupts? Enabling of interrupts is done with interrupt request permission bit (OCS01. ICE[1:0]), (OCS23. ICE[1:0]), (OCS45. ICE[1:0]), (OCS67. ICE[1:0]). Interrupt request permission bit (ICE0, ICE1) Set to “0” Set to “1” Interrupt disabled Enable interrupts Interrupt requests are cleared with interrupt request bits (OCS01. ICP[1:0]), (OCS23. ICP[1:0]), (OCS45. ICP[1:0]), (OCS67. ICP[1:0]).
Chapter 37 Output Compare 8.Caution 8. Caution • Compare stop space during compare operation As shown below, for one count directly after the compare value is written to the compare register, the compare operation cannot be used.
Chapter 37 Output Compare 8.
Chapter 38 Reload Timer 1.Overview Chapter 38 Reload Timer 1. Overview The reload timer uses a 16 bit down counter to detect the input signal trigger and perform a count down. The count length is 16 bits. Reload value Soft trigger Reload External event Internal clock or External event Down counter Underflow Reversal Output value Latch Pin ToPPG PPG ToA/D A/D 2.
Chapter 38 Reload Timer 3.Configuration Reload timer 2 : PPG4, PPG5 Reload timer 3 : PPG6, PPG7 Reload timer 4 : PPG8, PPG9 Reload timer 5 : PPG10, PPG11 Reload timer 6 : PPG12, PPG13 Reload timer 7 : PPG14, PPG15 • A/D converter activation trigger source (Reload timer 7 : A/D) 3. Configuration Figure 3-1 Configuration Diagram Reload Timer 0 (Internal clock count) TIN0 PFR14.
Chapter 38 Reload Timer 3.Configuration Figure 3-2 Configuration Diagram Reload timer 0 (External event count) 16 bit reload register TMRLR0 TRG TMCSR:bit0 Trigger (reload + counter activation) 0 No effect 1 Soft trigger Reload/activation/stop / / control circuit OUTL RELD TMCSR: bit5, bit4 0 "L" square wave during count 0 One-shot mode 0 "H" square wave during count 1 0 "L" toggle output on count start 1 Reload mode 1 1 "H" toggle output on count start Stop Counter activation .
Chapter 38 Reload Timer 4.Registers 4. Registers 4.1 TMCSR: Reload Timer Control Status Register • • • • • • • • The control status register controls the operation mode of the reload timer and interrupts.
Chapter 38 Reload Timer 4.Registers • bit9-7: Operation mode selection Reload trigger when internal clock is selected MOD2 0 0 0 0 MOD1 0 0 1 1 MOD0 0 1 0 1 Reload trigger Software trigger External trigger (rising edge) External trigger (falling edge) External trigger (both edges) When the selected reload trigger is input, the value of reload register TMRLR is loaded to the down counter and the count operation is started.
Chapter 38 Reload Timer 4.Registers interrupt request is enabled (INTE=“1”) an interrupt request is generated. • bit1: Enable timer count CNTE 0 1 Enable timer count Stop count operation Enable count operation (waiting for activation trigger) If timer count is enabled, it waits for an activation trigger, and when an activation trigger is generated, the count operation starts. The activation trigger can be a software trigger or an external trigger.
Chapter 38 Reload Timer 4.Registers • bit0: Software trigger TRG 0 1 Software trigger No effect. (The read value is “0”.) Start count operation after data load. If the count operation is enabled (CNTE=“1”) and the software trigger bit is set to “1”, the value of the reload register (TMRLR) is loaded to the down counter and the count operation starts. If the count operation is not enabled (CNTE=“0”), the software trigger has no effect. 4.
Chapter 38 Reload Timer 5.Operation X RX/W X RX/W X RX/W X RX/W X RX/W X RX/W X RX/W X RX/W (For information on attributes, see “Meaning of Bit Attribute Symbols (Page No.10)”.) The reload value for the down counter is stored in reload register TMRLR. Please write using half-word access. 5. Operation 5.1 Internal Clock/Reload Mode In reload mode, a pulse with a 50% duty ratio is output.
Chapter 38 Reload Timer 5.Operation 5.2 Internal Clock/One-shot Mode In one-shot mode, a one-shot pulse is output.
Chapter 38 Reload Timer 5.Operation 5.3 External Event Clock Reload Mode External event reload mode counts external events and outputs a pulse with a 50% duty ratio.
Chapter 38 Reload Timer 5.Operation 5.4 External Event Clock/One-shot Mode In external event one-shot mode, external events are counted and a one-shot pulse is output.
Chapter 38 Reload Timer 5.Operation 5.8 Operation when Returning from Stop Mode When returning due to an external interrupt, the reload timer will continue operation from its stopped state. When returning from a reset (INITX), it will return to the initial state (down counter stopped, no TOT pin output). 5.9 Status Transition The status of the counter is decided by the CNTE bit of the reload timer control register and the internal WAIT signal.
Chapter 38 Reload Timer 6.Setting 6. Setting Table 6-1 Settings Necessary for Moving the Reload Timer (Internal Clock Operation) Setting Reload value settings Setting Registers Reload (TMRLR0-TMRLR7) Setting Procedure* See7.1 Count clock selection (internal clock selection) See 7.2 Enable reload timer count operation See 7.3 Mode selection (reload /one-shot) Output reversal specification See 7.
Chapter 38 Reload Timer 6.Setting Table 6-3 Items Necessary for Performing Reload Timer Interrupts Setting Setting Registers Setting Procedure* Reload timer interrupt vector Reload timer interrupt level setting See “Chapter 24 Interrupt Control (Page No.311)” See 7.11 Reload timer interrupt settings Interrupt request clear Enable interrupt requests Reload timer control status (TMCSR0-TMCSR7) See 7.12 *: For the setting procedure, refer to the section indicated by the number.
Chapter 38 Reload Timer 7.Q & A 7. Q & A 7.1 What is the reload value setting (rewriting) procedure? The reload value is set by the 16 bit reload registers TMRLR0-TMRLR7. The equation for the values to be set is as follows. • Formula TMRLR register value = {reload interval/count clock}-1 • Allowed Range TMRLR register value = 0~FFFh (65535) 7.2 What are the kinds of count clocks and how are they selected? The count clock is chosen from the 4 types in the table below.
Chapter 38 Reload Timer 7.
Chapter 38 Reload Timer 7.Q & A 7.6 What are the kinds of triggers, and how do I select them? • Selection is done via the trigger selection bit (TMCSR.MOD[2:0]). There are 4 types of reload triggers when an internal clock is selected.
Chapter 38 Reload Timer 7.Q & A TIN6 pin TIN7 pin PFR14.6 = ‘1’ PFR14.7 = ‘1’ - 7.10 How do I generate an activation trigger? • Generating a soft trigger The setting is done via the software trigger bit (TMCSR.TRG). When the software trigger bit (TGR) is set to“1”, a trigger is generated. To enable operation and activate at the same time, set the count permission bit (TMCSR.CNTE) and the soft trigger bit (TMCSR.TRG) simultaneously.
Chapter 38 Reload Timer 7.Q & A Enabling of interrupts is done via the interrupt request permission bit (TMCSR0.INTE) ~ (TMCSR7.INTE). To disable interrupt requests To enable interrupt requests Interrupt request permission bit (INTE) Set to “0” Set to “1” Clearing of interrupt requests is done via the interrupt request bit (TMCSR0.UF) ~ (TMCSR7.UF). To disable interrupt requests Interrupt request bit (UF) Set to “0” 7.
Chapter 38 Reload Timer 8.Caution 8. Caution • Count source select bit (TMCSR.CSL[2:0]) settings not in the table: “100”, “111” are disabled. If they are set, disable the reload timer operation before resetting the count source select bit. • Operation mode bit (TMCSR.MOD2) must be set to “0”. If it is set to “1”, disable the reload timer count operation before resetting it. Also the value written during read/modify/write access may be read.
Chapter 39 Programmable Pulse Generator 1.Overview Chapter 39 Programmable Pulse Generator 1. Overview Programmable Pulse Generators (PPGs) are used to gain one-shot (rectangular wave) output or pulse width modulation (PWM) output. With their software-programmable cycle and duty capability, the PPGs comfortably fit into broad applications. Period value Down counter Count clock Reload Borrow Match Invert Output value Pin Latch Buffer Duty value 2.
Chapter 39 Programmable Pulse Generator 2.
Chapter 39 Programmable Pulse Generator 3.Configuration 3.
Chapter 39 Programmable Pulse Generator 3.Configuration Note: For more information about the ICR register and interrupt vector, see “Chapter 24 Interrupt Control (Page No.311)”.
Chapter 39 Programmable Pulse Generator 4.Registers 4. Registers 4.1 PCSR: PPG Cycle Setting Register • • • • • • • • • • • • • • • • Controls the cycle of the PPG.
Chapter 39 Programmable Pulse Generator 4.Registers 4.2 PDUT: PPG Duty Setting Register Sets the duty of the PPG output waveform.
Chapter 39 Programmable Pulse Generator 4.Registers 4.3 PCN: PPG Control Status register Controls the operations and status of PPGs.
Chapter 39 Programmable Pulse Generator 4.Registers • Bit 13: Mode selection MDSE 0 1 Mode PWM operation One-shot operation • When the Mode Selection bit is set to “0”, a PWM operation is enabled to generate pulses in sequence. • When the Mode Selection bit is set to “1”, pulse output takes place only once. • Bit 12: Restart enable RTTG 0 1 Operation Disable restart. Enable restart. When the Enable Restart bit is set to “1”, a trigger (software/internal) is generated to enable a restart.
Chapter 39 Programmable Pulse Generator 4.Registers 1 Interrupt request The operation is unaffected by writing. If the Interrupt Request flag (IRQF) equals “1” and writing “0” to the flag take place at the same time, the setting of the Interrupt Request flag (IRQF=“1”) overrides. • Bit 3-2: Interrupt cause selection IRS1 0 0 1 1 IRS0 0 1 0 1 Selection Software trigger, or, trigger input Counter borrow The counter matches the duty value. Counter borrow, or the counter equals the duty value.
Chapter 39 Programmable Pulse Generator 4.Registers 4.4 GCN1: General Control register 1 Selects a trigger input to PPG0-PPG3, PPG4-PPG7, PPG8-PPG11 and PPG12-PPG15.
Chapter 39 Programmable Pulse Generator 4.Registers 0 0 0 0 0 0 1 1 1 1 TSEL 0 0 0 0 0 1 0 1 1 0 1 0 0 0 0 0 0 1 0 1 None of the above 0 1 0 1 0 1 0 1 0 1 Activation trigger specification EN0 bit (GCN2 register) EN1 bit (GCN2 register) EN2 bit (GCN2 register) EN3 bit (GCN2 register) 16-bit reload timer 0/2/4/6 16-bit reload timer 1/3/5/7 External trigger 0/4 External trigger 1/5 External trigger 2/6 External trigger 3/7 Disabled (See “8. Caution (Page No.821)”.
Chapter 39 Programmable Pulse Generator 4.Registers 4.5 GCN2: General Control Register 2 Generates PPG0-PPG3, PPG4-PPG7, PPG8-PPG11 and PPG12-PPG15 internal trigger levels using software.
Chapter 39 Programmable Pulse Generator 4.Registers 4.6 PTMR: PPG Timer Register • • • • • • • • • • • • • • • • Reads the counts of PPG0-PPG3, PPG4-PPG7, PPG8-PPG11 and PPG12-PPG15.
Chapter 39 Programmable Pulse Generator 5.Operation 5. Operation The MB91460 series features a maximum of 16 programmable pulse generators (PPGs), which provide programmable pulse output independently or jointly. The individual modes of operation are described below. 5.1 PWM Operation In PWM operation, variable-duty pulses are generated from the PPG pin.
Chapter 39 Programmable Pulse Generator 5.Operation • Equation Period = {Period value (PCSR) + 1} x Count clock Duty = {Duty value (PDUT) + 1} x Count clock Width up to pulse output = {Period value (PCSR) – Duty value (PDUT)} x Count clock 5.2 One-Shot Operation In one-shot operation, one-shot pulses are generated from the PPG pin.
Chapter 39 Programmable Pulse Generator 5.Operation 5.3 Restart Operation The restart operation is described below. • Restart available in PWM operation: Rising edge detection Restarted by the trigger Trigger m n 0 PPG N T N = duty, T = cycle • Restart available in one-shot operation: Rising edge detection Restarted by the trigger Trigger m n 0 PPG N T If a restart is not available, the second and subsequent triggers have no effect in both PWM and one-shot operations.
Chapter 39 Programmable Pulse Generator 6.Setting 6. Setting Table 6-1 Settings Needed to Start the PPG Setting Period and duty value settings Enable PPG operation. Operation mode selection (PWM/one-shot) Enable restart. Count clock selection PPG output mask selection Trigger selection Software Internal trigger External trigger Output polarity specification PPG pin output setting Trigger generation (software trigger) (Reload timer) (GCN2.
Chapter 39 Programmable Pulse Generator 6.Setting Table 6-4 Settings Needed to Implement PPG Interrupts PPG interrupt cause selection (Generate an activation trigger, borrow, and duty match) PPG interrupt setting Clear interrupt requests. Enable interrupt requests. 7.13 PPG control status (PCN00-PCN15) *:For the setting procedure, refer to the section indicated by the number. 812 7.
Chapter 39 Programmable Pulse Generator 7.Q & A 7. Q & A 7.1 How do I set (rewrite) a cycle and a duty? Period and duty value settings • Set each cycle value in PPG Period Setting Register PCSR. • Set each duty value in PPG Duty Setting Register PDUT. • The PPG Period Setting and the PPG Duty Setting registers each have a buffer to allow the user to ignore the write timing.
Chapter 39 Programmable Pulse Generator 7.Q & A 7.5 What count clocks are available and how are they selected? Count clock selection The count clock is selectable out of the four choices listed below. Use the count clock selection bit (PCN.CKS[1:0]). Count Clock Selection Bit Count Clock CKS1 0 0 1 1 CLKP CLKP/4 CLKP/16 CLKP/64 CKS0 0 1 0 1 (Example) CLKP = 32 MHz Count Clock 32MHz 8MHz 2MHz 500kHz Period (1 - FFFFh) 62.5ns - 2.048µs 250ns - 8.192µs 1µs - 32.76ms 4µs - 131.0ms (See “8.
Chapter 39 Programmable Pulse Generator 7.Q & A 7.7 What activation triggers are available and how are they selected? • Trigger selection • Activation triggers are broadly grouped into software triggers, internal triggers and external triggers. • Software triggers work at all times. • Internal and external trigger availability depends on each device specification. An trigger is set using the trigger specification bits (GCN1.TSEL0[3:0]), (GCN1.TSEL1[3:0]), (GCN1.TSEL2[3:0]), and (GCN1.TSEL3[3:0]).
Chapter 39 Programmable Pulse Generator 7.Q & A Triggers are selectable for PPG8, PPG9, PPG10, and PPG11 independently.
Chapter 39 Programmable Pulse Generator 7.Q & A 7.8 How do I invert the output polarity? Output polarity specification The polarity in the normal state can be specified as follows: Use the PPG Output Polarity Specification bit (PCN.OSEL) to set. (“Normal state” means the state in which pulse output is not executed.) Output Level in Normal State To enable “L” level output (normal polarity) PPG Output Polarity Specification Bit (OSEL) Set “0”. To enable “H” level output (inverted polarity) Set “1”.
Chapter 39 Programmable Pulse Generator 7.Q & A 7.10 How do I generate an activation trigger? Generating a trigger Methods of generating an activation trigger are described below. • Activating a software trigger Use the Software Trigger bit (PCN.STGR) to set. Write “1” to the Software Trigger bit (STGR) to generate an activation trigger. Always functional, regardless of the internal trigger. • Activating PPGs with reload timers The reload timers need to be set up and activated.
Chapter 39 Programmable Pulse Generator 7.
Chapter 39 Programmable Pulse Generator 7.Q & A 7.13 What interrupts are available and how are they selected? Interrupt cause selection Four kinds of interrupts are selectable as follows: Use the Interrupt Cause Setting bit (PCN.IRS[1:0]) to set. Interrupt Cause Interrupt Cause Setting Bit (IRS[1:0]) Software trigger or Internal trigger generation (PPG0-PPG15) Down counter borrow (cycle match) Duty match Down counter borrow (cycle match) or Duty match Set “00”. Set “01”. Set “10”. Set “11”. 7.
Chapter 39 Programmable Pulse Generator 8.Caution 8. Caution • If the Interrupt Request flag (PCN.IRQF) equals “1” and the Interrupt Request flag is set to “0” at the same time, the setting of the Interrupt Request flag to “1” overrides the flag clear request. • The first load comes with a maximum delay of 2.5T after the activation trigger. (T: Count clock) If the down counter is loaded and counts at the same time, the load operation overrides. Trigger Maximum 2.
Chapter 39 Programmable Pulse Generator 8.
Chapter 40 Pulse Frequency Modulator 1.PFM Overview Chapter 40 Pulse Frequency Modulator This chapter provides an overview of the 16-bit pulse frequency modulator, describes the register structure/functions, and describes the operation of the 16-bit pulse frequency modulator. 1. PFM Overview The 16-bit pulse frequency modulator consists of two 16-bit down-counters, two 16-bit reload registers, prescalers for generating the internal count clocks and control registers.
Chapter 40 Pulse Frequency Modulator 1.
Chapter 40 Pulse Frequency Modulator 1.PFM Overview ■ Block Diagram of the 16-Bit Pulse Frequency Modulator 16 16-bit reload register 8 Reload RELD UF 16-bit down-counter 16 – – INTE GATE UF CSL2 CNTE CSL1 Clock selector TRG CSL0 INV 3 φ φ φ φ φ R-BUS 21 23 25 26 27 Clear prescaler Internal clock OUT Pulse Gen.
Chapter 40 Pulse Frequency Modulator 2.Reload Counter Registers 2. Reload Counter Registers This section describes the 16-bit pulse frequency modulator registers listed below. Control status register (P0TMCSR, P1TMCSR) 16-bit counter register (P0TMR, P1TMR) 16-bit reload register (P0TMRLR, P1TMRLR) ■ Control Status Register (P0TMCSR, P1TMCSR) Controls the operation mode and interrupts for the 16-bit reload counter. Only change the value of bits other than UF and TRG when CNTE = "0".
Chapter 40 Pulse Frequency Modulator 2.Reload Counter Registers Table 2-1 CSL Bit Clock Source Settings CSL2 CSL1 CSL0 Clock source (φ : Machine clock) 0 0 0 φ / 21 0 0 1 φ / 23 0 1 0 φ / 25 0 1 1 Setting disabled 1 0 0 Setting disabled 1 0 1 φ / 26 1 1 0 φ / 27 1 1 1 Setting disabled [Bits 9] Reserved Always set to "0". [Bits 8] MOD1 Sets the Trigger level to Falling edge (MOD1=’1’ is necessary for PFM operation) [Bits 7 to 5] Reserved Always set to "010".
Chapter 40 Pulse Frequency Modulator 2.Reload Counter Registers Writing "1" sets the counter to wait for a trigger. Writing "0" stops count operation. [Bit 0] TRG Software trigger bit. Writing "1" to TRG applies a software trigger, causing the counter to load the reload register contents to the counter and start counting. Writing "0" has no meaning. Reading always returns "0". Applying a trigger using this register is only valid when CNTE = "1". Writing "1" has no effect if CNTE = "0".
Chapter 40 Pulse Frequency Modulator 2.
Chapter 40 Pulse Frequency Modulator 3.Reload Counter Operation 3. Reload Counter Operation This section describes the operations of the 16-bit reload counter: Internal clock operation and Underflow operation ■ Internal Clock Operation The machine clock divided by 2, 8, 32, 64 or 128 can be selected as the clock source when operating the counter from an internal clock. Writing "1" to both the CNTE and TRG bits in the control status register enables and starts counting simultaneously.
Chapter 40 Pulse Frequency Modulator 3.Reload Counter Operation ● Underflow operation timing • When RELD = "1" Count clock Counter 0000H Reload data –1 –1 –1 Data load Underflow set • When RELD = "0" Count clock Counter 0000H FFFFH Underflow set Figure 3-2 Underflow Operation Timing ■ Counter Operation States The counter state is determined by the CNTE bit in the control register and the internal WAIT signal.
Chapter 40 Pulse Frequency Modulator 3.Reload Counter Operation ● Counter state transitions State transitions by hardware State transitions by register access Reset STOP CNTE= "0", WAIT= "1" Counter: Stores the value when counting stopped. Indeterminate after a reset. CNTE= "0" CNTE= "0" CNTE= "1" CNTE= "1" TRG= "1" TRG= "0" WAIT RUN CNTE= "1", WAIT="1" CNTE= "1", WAIT= "0" Counter: Running Counter: Stores the value when counting stopped. Indeterminate after a reset until loaded.
Chapter 40 Pulse Frequency Modulator 4.PFM Operation and Setting 4. PFM Operation and Setting This section describes the following operations of the 16-bit pulse frequency mod (combining the functionality of both reload counters). 1. The underflow output of reload counter channel 0 is connected internally to the trigger input reload counter channel 1. The underflow output of reload counter channel 1 is connected internally to the trigger input of reload counter channel 0. 2.
Chapter 40 Pulse Frequency Modulator 4.
Chapter 41 Up/Down Counter 1.Overview Chapter 41 Up/Down Counter 1. Overview Triggered by an input signal, 16-bit Up/Down Counter counts up or down within the range of 0 to 65535. Specifically, Up/Down Counter running in the phase difference count mode is suitable for counting the encoder pulse of motors and other equipment. When encoder's output signals of phase A, phase B and phase Z are applied, the counter can achieve precise counting of rotation angles or number of revolutions.
Chapter 41 Up/Down Counter 3.Configuration 3.
Chapter 41 Up/Down Counter 3.
Chapter 41 Up/Down Counter 3.
Chapter 41 Up/Down Counter 3.Configuration Figure 3-5 Register List Note: For ICR registers and interrupt vectors, refer to “Chapter 24 Interrupt Control (Page No.311)”. Figure 3-6 Register List Note: For ICR registers and interrupt vectors, refer to “Chapter 24 Interrupt Control (Page No.311)”.
Chapter 41 Up/Down Counter 4.Register 4. Register 4.1 UDCC: Counter Control Register This register is used to control behaviors of Up/Down Counter.
Chapter 41 Up/Down Counter 4.Register FCLKP: Frequency of Peripheral clock (CLKP) This setting is enabled only in the timer mode, in which only countdown is performed. • bit11,10: Select count mode CMS1 0 0 1 1 CMS0 0 1 0 1 Count mode Timer mode (Countdown) Up/down count mode Phase difference count mode (Multiply by 2) Phase difference count mode (Multiply by 4) • bit9,8: Select count clock edge CES1 0 0 1 1 CES0 0 1 0 1 Edge selection Disable edge detection. Detect a falling edge.
Chapter 41 Up/Down Counter 4.Register • bit1,0: Select counter clear/gate edge 842 CGE1 CGE0 0 0 1 1 0 1 0 1 Edge detection/level selection When the counter clear function is selected When the gate function is selected (CGSC=“0”) (CGSC=“1”) Disable edge detection. Disable level detection. (Disable count.) Detect a falling edge. Detect a “L” level. Detect a rising edge. Detect a “H” level. Disable setting. Disable setting.
Chapter 41 Up/Down Counter 4.Register 4.2 UDCS: Count Status Register This register is used to control Up/Down Counter and to indicate the status of the counter.
Chapter 41 Up/Down Counter 4.Register To enable interrupt requests, the interrupt request permission bit must be set (UDIE= “1”).
Chapter 41 Up/Down Counter 4.Register 4.3 UDCR: Up/Down Counter Register This register is used to read the count value of Up/Down Counter. • UDCR10 (Up/Down Counter 0/1): Address 0302H (Access: Byte, Half-Word) • UDCR32 (Up/Down Counter 2/3): Address 0312H (Access: Byte, Half-Word) Depending on the setting of the 16-bit mode enable bit (CCR.M16E), this register behaves differently. ■ 16 Bit Mode (M16E= “1”) In the 16 bit mode, this register functions as 16-bit up/down counter register.
Chapter 41 Up/Down Counter 4.Register 4.4 UDRC: Up/Down Reload/Compare Register This register is used to reload a value to Up/Down Counter and for comparison. This register is also used to write to Up/Down Counter. • UDRC10 (Up/Down Counter 0/1): Address 0300H (Access: Byte, Half-Word) • UDRC32 (Up/Down Counter 2/3): Address 0310H (Access: Byte, Half-Word) Depending on the setting of the 16 bit mode enable bit (CCR.M16E), this register behaves differently.
Chapter 41 Up/Down Counter 4.Register (1) Stop counting. (2) Write a value to the reload/compare register. (3) Write “1”to the counter write bit (CCR.CTUT).
Chapter 41 Up/Down Counter 5.Operation 5. Operation This section describes each operation mode for Up/Down Counter. 5.
Chapter 41 Up/Down Counter 5.Operation 5.
Chapter 41 Up/Down Counter 5.Operation 5.3 Up/Down Count Mode CMS[1:0]=“01” ZIN=Gate control (12) (6) (7) (2) (11) (8) CS TR, RLDE, UCRE UDCC AIN (1) (2) (3) (6) (7) BIN CGE[1:0]=“10” (12) (9) (4) “H” (8) (10) “H” (13) ZIN (Gate) Countgate at the ZIN pin (1) Appropriate bits (Counting enable CSTR, Reload enable RLDE and Clear enable UCRE) are set. (2) Up/Down Counter is cleared. (“0” is written to CGSC).
Chapter 41 Up/Down Counter 5.Operation 5.4 Phase Difference Count Mode (Multiply by 2) CMS[1:0]=“10” Frequency multiplied by 2 in phase difference count mode: On the rising and falling edges at the BIN count pin, Up/Down Counter counts up or down, depending on the voltage level at the AIN pin.
Chapter 41 Up/Down Counter 5.Operation 5.5 Phase Difference Count Mode (Multiply by 4) CMS[1:0]=“11” Frequency multiplied by 4 in phase difference count mode: On the rising and falling edges at the BIN pin, Up/Down Counter counts up or down, depending on the voltage level at the AIN pin, and on the rising and falling edges at the AIN pin, Up/Down Counter counts up or down, depending on the voltage level at the BIN pin.
Chapter 41 Up/Down Counter 5.Operation 5.6 Clear Timing (1) When a clear request (Compare-match, ZIN edge detection and writing “0” to the clear bit UDCLR) is made, clear is performed next time when Up/Down Counter counts up. Compare value 0066 H Count value 0065 H 0066 H 0001 H 0000 H Clear request Countup Clear timing (2) Even if a clear request (Compare-match, ZIN edge detection and writing “0” to the clear bit DCC) is made, clear is not performed when UP/Down Counter counts neither up nor down.
Chapter 41 Up/Down Counter 5.Operation 5.7 Reload Timing The next time when Up/Down Counter counts down below “0000”, an underflow occurs (an interrupt request is made) and then reloading is performed. Compare value 0066 H Count value 0001 H 0000 H 0066 H 0065 H 0064 H Countdown Underflow Reload timing Note: If clear and reload operations occur at the same time, clear takes precedence. 5.
Chapter 41 Up/Down Counter 6.Setting 6. Setting Table 6-1 Required Settings to Run Up/Down Counter in Timer Mode Setting Setting registers Setting procedure* Set the reload value. Reload/compare register (UDRC) See 7.16. (Optional) Set a value to Up/Down Counter or Clear the count value of Up/Down Counter. Reload/compare register (UDRC) See 7.5. Count control register (UDCC) See 7.8. Set a bit length. See 7.1. Set the count mode to timer mode. See 7.2. Select a count source.
Chapter 41 Up/Down Counter 6.Setting Table 6-3 Required Settings to Run Up/Down Counter in Phase Difference Count Mode (Multiply by 2 or 4) Setting Setting registers Setting procedure* Set the reload value/compare value. Reload/compare register (UDRC). See 7.16 (Optional) Set a value to Up/Down Counter or Clear the count value of Up/Down Counter. Reload/compare register (UDRC) See 7.5 Count control register (UDCC) See 7.8 Set a bit length. See 7.
Chapter 41 Up/Down Counter 7.Q&A 7. Q&A 7.1 How do I select a bit length (8 or 16) of Up/Down Counter? Use the 16 bit mode enable bit (UDCC.M16E). Up/Down Counter's bit length To set the bit length to 8 To set the bit length to 16 bit 16 bit mode enable bit (M16E) Set the bit to “0”. Set the bit to “1”. 7.
Chapter 41 Up/Down Counter 7.Q&A 7.7 How do I enable reloading of the reload value (RCR[1:0]) to Up/Down Counter when Up/Down Counter is underflowed? Use the reload enable bit (UDCC.RLDE). When the count-up value agrees with the compare value: To disable reloading of the reload value (RCR) to Up/ Down Counter To enable reloading of the reload value (RCR) to Up/Down Counter Reload enable bit (RLDE) Set the bit to “0”. Set the bit to “1”. 7.
Chapter 41 Up/Down Counter 7.Q&A 7.11 How do I enable/disable Up/Down Counter's count operation? Use the count activate bit (UDCS.CSTR). When the count-up value agrees with the compare value: To disable Up/Down Counter's count operation To enable Up/Down Counter's count operation (To activate count operation) Count activate bits (UDCS.CSTR) Set the bit to “0”. Set the bit to “1”. • How do I start counting? Timer mode Up/down count mode Counting starts using the internal clock (See 7.3.
Chapter 41 Up/Down Counter 7.Q&A 7.15 How do I know that an overflow or underflow has occurred? Use the overflow detection flag (UDCS.OVFF) and the underflow detection flag (UDCS.UDFF). OVFF =“1” indicates that Up/Down Counter has been overflowed. UDFF =“1” indicates that Up/Down Counter has been underflowed. 7.16 How do I set the reload/compare value? Set a value to the reload/compare registers (UDRC). (This value is used as a compare or reload value.) 7.
Chapter 41 Up/Down Counter 7.Q&A 7.19 How do I enable (select), disable or clear interrupts? Interrupt request enable and interrupt request flags To enable (select) interrupts, use the following interrupt request permission bits: • Count direction change interrupt request permission bits: UDCC.CFIE • Compare interrupt request permission bits : UDCS.CITE • Overflow/underflow interrupt request permission bits : UDCS.
Chapter 41 Up/Down Counter 8.Caution 8. Caution • The count direction is set to “countdown” immediately after resetting the counter. So, when the counter counts up immediately after resetting, the count direction change bit (UDCC.CDCF) is set to “1” to indicate a direction change has been made. • When the up/down counter register UDCR has reached the maximum count, the overflow flag is set to 1 and counting continues. This time UDCR is cleared.
Chapter 42 Sound Generator 1.Overview Chapter 42 Sound Generator 1. Overview This Chapter provides an overview of the Sound Generator, describes the register structure and functions, and describe the operation of the Sound Generator. The Sound Generator consists of the Sound Control register, Frequency Data register, Amplitude Data register, Decrement Grade register, Tone Count register, Sound Disable register, PWM pulse generator, Frequency counter, Decrement counter and Tone Pulse counter.
Chapter 42 Sound Generator 2.Block Diagram 2.
Chapter 42 Sound Generator 3.Registers 3.
Chapter 42 Sound Generator 3.Registers 3.
Chapter 42 Sound Generator 3.Registers [bit 2] INTE : Interrupt enable bit This bit enables the interrupt signal of the Sound Generator. When this bit is "1" and the INT bit is set to "1", the Sound Generator signals an interrupt. [bit 1] INT : Interrupt bit This bit is set to "1" when the Tone Pulse counter counts the number of the tone pulses specified by the Tone Count register and Decrement Grade register. This bit is reset to "0" by writing "0". instructions always result in reading "1".
Chapter 42 Sound Generator 3.Registers value represents the amplitude of the sound. The register value is reloaded into the PWM pulse generator at the end of every tone cycle. When the DEC bit is "1" and the Decrement counter reaches its reload value, this register value is decremented by 1(one). And when the register value reaches "00", further decrements are not performed. However the sound generator continues its operation until the ST bit is cleared.
Chapter 42 Sound Generator 3.Registers reaches the reload value it sets the INT bit. They are intended to reduce the frequency of interrupts. The count input of the Tone Pulse counter is connected to the carry-out signal from the Decrement counter. And when the Tone count register is set to "00", the Tone Pulse counter sets the INT bit every carry-out from the Decrement counter. Thus the number of accumulated tone pulses is: ((Decrement Grade register) +1) x ((Tone Count register) +1) i.e.
Chapter 42 Sound Generator 3.
Chapter 43 Stepper Motor Controller 1.Overview Chapter 43 Stepper Motor Controller 1. Overview The stepping motor controller consists of PWM pulse generators, motor drivers, selector logic circuits and A/D converter inputs. The four motor drivers have a high-output driving capability and two motor coils can be connected directly to four pins. The motor rotation is designed to be controlled by a combination of the PWM pulse generators and selector logic circuits.
Chapter 43 Stepper Motor Controller 2.Registers Figure 1-2 Stepping Motor Controller PFR25 PWM control register SC bit PWM Clock Prescaler CK Output enable CE bit PWM1P Selector PWM1 pulse generator EN P25.0/SMC1P4 PWM1M PWM P25.1/SMC1M4 Peripheral clock CLKP PWM1 compare register CK Output enable P25.2/SMC2P4 PWM2P Selector PWM2 pulse generator EN Port 25 PWM1 selection register P25.
Chapter 43 Stepper Motor Controller 2.Registers 2.
Chapter 43 Stepper Motor Controller 2.Registers 2.2 PWM Control Register The PWM control register starts/stops the stepping motor controller, performs interrupt control and performs setting of external output pins, etc., for the stepping motor controller. ■ PWM Control Register PWM Control register (PWC0, PWC1, PWC2, PWC3, PWC4, PWC5) Address 0x0C1, 0x0C3 0x0C5, 0x0C7 0x0C9, 0x0CB P2 [bit 7] Reserved bit Always set the reserved bit to "0".
Chapter 43 Stepper Motor Controller 2.Registers PWM pulse generator operates at 8 bit. [bit 1 to 0] Reserved bits Always set the reserved bits to "00".
Chapter 43 Stepper Motor Controller 2.Registers 2.3 PWM1&2 Compare Registers The value of the two 8(10) bits compare register of PWM1&2 determine the width of the PWM pulse. The stored "00H (000H)" value indicates that the PWM duty is 0%, and the stored "FFH" ("3FFH") value indicates that the PWM duty is 99.6% (99.9%).
Chapter 43 Stepper Motor Controller 2.
Chapter 43 Stepper Motor Controller 2.Registers 2.4 PWM1&2 Selection Registers The PWM1&2 selection registers determine whether to set the output of the external pin of the stepping motor controller to "0", "1", PWM pulse or high impedance.
Chapter 43 Stepper Motor Controller 2.Registers Figure 2-2 load timing of PWM compare register value [Automatic clear of BS bit] Load the values of the registers and reflected in the output signal.
Chapter 43 Stepper Motor Controller 2.Registers [bit 13 to 11] P2 to P0: Output select bits These bits are used to select the output signal for SMC2P. [bit 10 to 8] M2 to M0: Output select bits These bits are used to select the output signal for SMC2M. [bit 7 to 6] Reserved bit Always set the reserved bit to "0". [bit 5 to 3] P2 to P0: Output select bits These bits are used to select the output signal for SMC1P.
Chapter 43 Stepper Motor Controller 3.Operation 3. Operation The operation of the stepping motor controller is explained. ■ Setting Operation of Stepping Motor Controller Figure 3-1 Setting of Stepping Motor Controller PWM1 H width (compare value) is set. PWM2 H width (compare value) is set. Used bit Not used bit 1 is set. 0 is set. Channel No. ■ Operation of PWM-pulse generator When the counter is started (PWC: CE = 1), the counter starts incrementing from 00H on the selected count clock rising.
Chapter 43 Stepper Motor Controller 3.Operation Figure 3-2 Examples of PWM1&2 Waveform Output When the value of compare register is "00H"/"000H"(duty ratio is 0%): Value of counter: PWM waveform: When the value of compare register is "80H"/"200H"(duty ratio is 50%): Value of counter: PWM waveform: When the value of compare register is "FFH"/"3FFH"(duty ratio is 99.6%/99.
Chapter 43 Stepper Motor Controller 4.Caution 4. Caution The caution when using the stepping motor controller are described below. ■ Caution when Changing PWM Setting The PWM compare registers 1&2 (PWC1, PWC2) and the PWM selection registers 1&2 (PWS1, PWS2) can be accessed at any time.
Chapter 43 Stepper Motor Controller 4.
Chapter 44 A/D Converter 1.Overview of A/D Converter Chapter 44 A/D Converter This chapter provides an overview of the A/D converter, describes the register structure and functions, and describes the operation of the A/D converter. • • • • 1. Overview of A/D Converter 2. Block Diagram of A/D Converter 3. Registers of A/D Converter 4. Operation of A/D Converter 1. Overview of A/D Converter The A/D converter converts analog input voltage into digital values and provides the following features.
Chapter 44 A/D Converter 2.Block Diagram of A/D Converter 2. Block Diagram of A/D Converter Following figure shows block diagram of A/D converter.
Chapter 44 A/D Converter 3.Registers of A/D Converter 3. Registers of A/D Converter The A/D converter has the following registers.
Chapter 44 A/D Converter 3.Registers of A/D Converter • ADCS0 (ADC0): Address 01A5h (Access: Half-word, Byte) 7 MD1 6 MD0 5 S10 4 ACH4 3 ACH3 2 ACH2 1 ACH1 0 ACH0 0 0 0 0 0 0 0 0 R/W R/W R/W R R R R R Bit Initial value Attribute (See “Meaning of Bit Attribute Symbols (Page No.10)” for details of the attributes.
Chapter 44 A/D Converter 3.Registers of A/D Converter • ADECH (ADC0): Address 01ABh (Access: Word, Half-word, Byte) 7 - 6 - 5 - 4 ANE4 3 ANE3 2 ANE2 1 ANE1 0 ANE0 - - - 0 0 0 0 0 RX, W0 RX, W0 RX, W0 R/W R/W R/W R/W R/W Bit Initial value Attribute (See “Meaning of Bit Attribute Symbols (Page No.10)” for details of the attributes.) 3.1 A/D Enable Register (ADER) While a pin is used as analog input, corresponding bit in ADER register have to be set to 1.
Chapter 44 A/D Converter 3.Registers of A/D Converter 3.2 A/D Control Status Register (ADCS) A/D control status register controls and shows the status of A/D converter. Do not overwrite ADCS0 register during A/D converting.
Chapter 44 A/D Converter 3.Registers of A/D Converter Cleared by writing "0" or by a reset. (Not cleared at the end of DMA transfer.) However when waiting condition of DMA transfer, this bit cannot be cleared. Regarding protect function of converted data, see Section “4. Operation of A/D Converter". [bit 3, 2] STS1, STS0 (Start source select) These bits initialized "00" by reset. These bits select the A/D activation source.
Chapter 44 A/D Converter 3.Registers of A/D Converter Continuous mode: Repeated A/D conversion cycles from selected channels ANS4 to ANS0 to selected channels ANE4 to ANE0. Stop mode: A/D conversion for each channel from selected ANS4 to ANS0 to selected channels ANE4 to ANE0, followed by a pause. Restart is determined by the occurrence of a start source. When A/D conversion is started in continuous mode or stop mode, conversion operation continued until stopped by the BUSY bit.
Chapter 44 A/D Converter 3.Registers of A/D Converter 2-bit. The register values are updated at the completion of each conversion. The registers normally store the results of the previous conversion. ■ Data register (ADCR1, ADCR0) • ADCR1 (ADC0): Address 01A6h (Access: Word, Half-word, Byte) 15 - 14 - 13 - 12 - 11 - 10 - 9 D9 8 D8 - - - - - - X X RX, W0 RX, W0 RX, W0 RX, W0 RX, W0 RX, W0 R R Bit Initial value Attribute (See “Meaning of Bit Attribute Symbols (Page No.
Chapter 44 A/D Converter 3.Registers of A/D Converter Conversion time = CT value * CLKP cycle * 10 + (4 * CLKP) Remarks : Do not set conversion time over 500 us. [bit 9 to 0] ST9-0 (Analog input sampling time set) These bits specify sampling time of analog input. Initialized these bits to "0000101100" by reset. Sampling time = ST value * CLKP cycle Remarks : Do not set sampling time below 1.2 us when AVCC is below 4.5 V. Necessary sampling time and ST value are calculated by following.
Chapter 44 A/D Converter 3.Registers of A/D Converter • ADECH (ADC0): Address 01ABh (Access: Word, Half-word, Byte) 7 - 6 - 5 - 4 ANE4 3 ANE3 2 ANE2 1 ANE1 0 ANE0 - - - 0 0 0 0 0 RX, W0 RX, W0 RX, W0 R/W R/W R/W R/W R/W Bit Initial value Attribute (See “Meaning of Bit Attribute Symbols (Page No.10)” for details of the attributes.) These bits set the start and end channel for A/D converter.
Chapter 44 A/D Converter 4.Operation of A/D Converter 4. Operation of A/D Converter The A/D converter operates using the successive approximation method with 10-bit or 8-bit resolution. As only one 16-bit register is provided to store conversion results, the conversion data register (ADCR0 and ADCR1) is updated each time conversion completes. Therefore, as the A/D converter on its own is not suitable for performing continuous conversion, it is recommended that you use the DMA service.
Chapter 44 A/D Converter 4.Operation of A/D Converter 4.
Chapter 44 A/D Converter 4.Operation of A/D Converter 4.
Chapter 44 A/D Converter 5.Setting 5. Setting Table 5-1 Settings needed to use A/D - Single-Shot Conversion Mode Setting Mode selection (Single-shot conversion) Bit length selection Channel selection Conversion time setting To program the AN pin as an input Setting Registers A/D control (ADCS) Conversion time setting (ADCT) Port Function (PFR26-PFR29) and Extra Port Function (EPFR26-EPFR27) A/D activation trigger selection Setting Procedure* See 7.1 See 7.2 See 7.3 See 7.4 See 7.5 See 7.
Chapter 44 A/D Converter 5.Setting Table 5-3 Forcing A/D operations to Stop Setting Forced stop Setting Registers A/D control (ADCS) Setting Procedure* See 7.10 *: For the setting procedure, refer to the section indicated by the number. Table 5-4 Items needed to enable A/D Interrupts Setting A/D interrupt vector and A/D interrupt level settings A/D interrupt cause selection (A/D conversion end) A/D interrupt setting Clear interrupt requests. Enable interrupt requests.
Chapter 44 A/D Converter 6.Q & A 6. Q & A 6.1 What conversion modes are available and how are they selected? Two modes of conversion are available: • Single-shot conversion mode, in which the conversion takes place only once. • Scan conversion mode, in which a specified sequence of channels are converted. Mode selection is made using the conversion mode selection bits (ADCS.MD[1:0]).
Chapter 44 A/D Converter 6.Q & A 6.3 How do I set a conversion time? Use Conversion Time Setting registers ADCT to set. [bit 15 to 10] CT5-0 (A/D conversion time set) These bits specify clock division of conversion time. Setting "000001" means one division (=CLKP). Do not set these bits "000000". Initialized these bits to "000100" by reset. Conversion time = CT value * CLKP cycle * 10 + (4 * CLKP) Remarks : Do not set conversion time over 500 us.
Chapter 44 A/D Converter 6.
Chapter 44 A/D Converter 6.Q & A To specify a software trigger To specify an external trigger/software trigger To specify a reload timer/software trigger To specify an external trigger/reload timer/software trigger Set “00”. Set “01”. Set “10”. Set “11”. The converter A/D is activated on the first instance of any one of these causes selected. 6.7 To activate the A/D converter • Generating a software trigger A software trigger is generated using A/D Conversion Software Trigger bits (ADCS.STRT).
Chapter 44 A/D Converter 6.Q & A 6.11 What interrupt registers are used? A/D interrupt vector, A/D interrupt level setting The table below summarizes the relationships among the machine cycle, A/D number, interrupt level, and interrupt vector. For more information about the interrupt level and interrupt vector, see “Chapter 24 Interrupt Control (Page No.311).” AD0 Interrupt Vector (Default) #134 Address: 0FFDE4h Interrupt Level Setting Bit (ICR[4:0]) Interrupt Level register (ICR59) Address: 047Bh 6.
Chapter 44 A/D Converter 7.Caution 7. Caution Tips on using the A/D converter are summarized as follows: • Power-on sequence Be sure to turn on the MCU power (Vdd*) before turning on the power to the A/D converter (AVcc, AVRH) and applying a voltage to the analog input. • Input impedance of the analog input pin The A/D converter has a built-in sample hold circuit to receive the voltage present on the analog input pin in the sample hold capacitor after the activation of an A/D conversion.
Chapter 44 A/D Converter 7.Caution ■ Definitions of A/D Converter Terms • Resolution Analog change identifiable to an A/D converter.
Chapter 44 A/D Converter 7.Caution • Overall error Difference between an actual vale and a theoretical value, containing a zero transition error/full transition error/linearity error 1LSB’(Ideal value) = AVRH - AVSS 1024 [V] VOT’ (Ideal value) = VFST’ (Ideal value) = AVSS + 0.5LSB’ AVRH - 1.5LSB’ [V] [V] Overall error of digital output N = VNT - {1LSB’ × (N - 1) + 0.5LSB’} 1LSB’ VNT: Voltage at which digital output transit from (N+1) to N Overall error 3FF 1.
Chapter 45 D/A Converter 1.Overview Chapter 45 D/A Converter 1. Overview The D/A converter converts digital values to analog output values on an R-2R type conversion basis. Pin Digital value D/A converter Analog output 2. Features Method Quantity Conversion time Resolution Output range Interrupt Others : R-2R type conversion : 2 (Output: DA0 pin and DA1 pin) : 0.45us (Typ) (Load capacitance = 20pF) 2.
Chapter 45 D/A Converter 3.Configuration 3. Configuration Figure 3-1 Configuration Diagram D/A converter (0-1) Register number (:bit) DAE 0 1 DADR0/ DADR1 DACR: bit 0 DACR: bit 1 D/A output disable (0 V output) D/A output enable D/A 0 1 Data DADR0 DADR1 2R R DA0 DA1 1 R From Port Data register AVcc Pin DA0 PFR28: bit 6 DA1 PFR28: bit 7 0 General-purpose port output 1 D/A output only 2R 2R Port function DACR.DAE0 PFR28.6 DACR.DAE1 PFR28.7 Control 2R 2 R 2R R 0 DA0/P28.6 DA1/P28.
Chapter 45 D/A Converter 4.Registers 4. Registers 4.1 DADR: D/A Data Register The D/A Data Register sets the output voltage of the D/A converter.
Chapter 45 D/A Converter 4.Registers • bit2: D/A 8-/10-bit mode control MD08 0 1 Operation D/A resolution is 10 bits D/A resolution is 8 bits • In case MD08=’1’ the 8-bit value of DA7-DA0 (DADR[7:0]) is output.
Chapter 45 D/A Converter 5.Operation 5. Operation The operations of the D/A converter are described below.
Chapter 45 D/A Converter 6.Setting 6. Setting Table 6-1 Settings Needed to Use D/A Setting Digital value settings Pin settings Output enabled Setting Registers D/A Data Registers (DADR) Port Function Register (PFR28.7, PFR28.6) D/A Control Registers (DACR) Setting Procedure* See 7.1. See 7.2. See 7.3. *:For the setting procedure, refer to the section indicated by the number.
Chapter 45 D/A Converter 7.Q & A 7. Q & A 7.1 Where should I set digital values? Write digital values to the D/A Data Registers (DADR[7:0] for 8-bit mode, DADR[9:0] for 10-bit mode). Access in a byte or halfword format. D/A conversion begins immediately on writing. 7.2 How do I program the D/A pins for D/A output? DA Pin output setting Setting is accomplished by writing “1” to the output specification bits (PFR28.7 for DA1), (PFR28.6 for DA0). (Switch the port to DA pin output by software programming.
Chapter 45 D/A Converter 8.Caution 8. Caution • The table below lists the output voltages of the D/A converter (in 10-bit resolution mode). DADR Settings D/A Converter Output Voltage Value 000H 0V (AVss=0.0V) 001H 1/1024 x AVCC V 002H 2/1024 x AVCC V ~ 3FDH ~ 1021/1024 x AVCC V 3FEH 1022/1024 x AVCC V 3FFH 1023/1024 x AVCC V When stopped 0V (Avss=0.0V) • The table below lists the output voltages of the D/A converte (in 8-bit resolution mode)r.
Chapter 46 Alarm Comparator 1.Overview Chapter 46 Alarm Comparator 1. Overview This chapter provides an overview of the Alarm Comparator (also called Under/Overvoltage Detection), describes the register structure and functions, and describes the operation of the Alarm Comparator. 2. Block Diagram Alarm comparator - analog part Alarm comparator - digital part AVDD RST OUT1 D 0.8 AVDD CLKP Q STOP CK ACSR ALARM PD OUT2 0.
Chapter 46 Alarm Comparator 3.Alarm Comparator Control/Status Register (ACSR) 3.
Chapter 46 Alarm Comparator 4.Operation Modes Bit 1: IEN Interrupt enable bit. 1 Interrupt assertion enabled 0 Interrupt assertion disabled [Initial value] Bit 0: PD Power down bit. 1 Power down (analog part) 0 Runmode (analog part) [Initial value] 4. Operation Modes The alarm comparator circuit can operate in interrupt or polling mode. The internal interrupt logic will detect each interrupt event independent from setting of the IEN bit. 4.
Chapter 46 Alarm Comparator 4.Operation Modes 4.
Chapter 47 LCD Controller 1.Overview Chapter 47 LCD Controller 1. Overview LCD allows display of up to 160 cells and selection of a duty cycle from 1/2, 1/3 and 1/4. LCD has many applications. Internal Divided Resistors or External Divided Resistors Driver bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 Segment VRAM1 VRAM2 Common Driver Timing Circuit Sub-clock Prescaler Peripheral clock AC Circuit VRAM19 2.
Chapter 47 LCD Controller 3.Configuration 3. Configuration Figure 3-1 Configuration Diagram LCD Controller FP1,0 LCR0: bit1,0 0 0 0 1 1 0 1 1 LCR0: bit7 1 Subclock FCL-SUB /(2 3 FCL-SUB /(2 4 FCL-SUB /(2 5 FCL-SUB /(2 6 LCDCMR MS1,0 LCR0: bit3,2 0 0 Deactivate 0 1 1/2 duty cycle 1 0 1/3 duty cycle 1 1 1/4 duty cycle N) N) N) N) From port data register COM0 0 Timing Control Circuit Prescaler Sub clock COM0 PFR30.0 : : COM3 PFR30.3 0 General-purp.
Chapter 47 LCD Controller 3.
Chapter 47 LCD Controller 4.Registers 4. Registers 4.1 LCR0: LCDC Control Register 0 This register is used to select a frame period and its clock and the display mode, to enable/disable LCD display and the operation in the watch mode, and to control the drive power source.
Chapter 47 LCD Controller 4.Registers • bit1-0: Frame period Frame period When peripheral clock is selected: When subclock is selected: FP1 FP0 0 0 FCLKP/(213 × N) FCL-SUB/(23 × N) 0 1 FCLKP/(214 × N) FCL-SUB/(24 × N) 1 0 FCLKP/(215 × N) FCL-SUB/(25 × N) 1 1 FCLKP/(216 × N) FCL-SUB/(26 × N) FCLKP FCL-SUB N Peripheral clock (CLKP) frequency Subclock frequency Time division number (Selected with the display mode select bits, MS1 and MS0.
Chapter 47 LCD Controller 4.Registers 4.
Chapter 47 LCD Controller 4.
Chapter 47 LCD Controller 4.Registers 4.3 LCR1: LCDC Control Register 1 • LCR1H: Address 0EAH (Access: Byte, Half-word, Word) 15 - 14 - 13 - 12 - 11 - 10 - 9 SEGEN9 0 R/W 8 SEGEN8 0 R/W bit Initial value Attribute (For attributes, refer to “Meaning of Bit Attribute Symbols (Page No.10)”.) • bit15-10: Undefined (Read: Indeterminate, Write: “0” is always written.) • bit9-8: Segment driver enable. Always set to “11B” when LCD is used.
Chapter 47 LCD Controller 5.Operation 5. Operation This section describes operation. 5.1 LCD Controller/Driver (LCDC) Operation (1) Set values to the display data memory (VRAM) in advance. (2) Make necessary settings to each register. (3) When the frame period generation clock oscillates, LCD drive waveform is output through common/ segment output pins (COM0 - COM3, SEG0 - SEG39).
Chapter 47 LCD Controller 5.
Chapter 47 LCD Controller 5.Operation 5.3 1/3 Duty Cycle Output Waveform In the 1/3 duty cycle output mode, COM0, COM1 and COM2 outputs are used for LCD display. COM3 output is not used. • Example of 1/3 Bias Output Waveform LCD cells with the maximum voltage difference between common and segment outputs are lit.
Chapter 47 LCD Controller 5.
Chapter 47 LCD Controller 5.Operation 5.4 1/4 Duty Cycle Output Waveform In the 1/4 duty cycle output mode, COM0, COM1, COM2, and COM3 outputs are all used for LCD display. • Example of 1/3 Bias Output Waveform LCD cells with the maximum voltage difference between common and segment output are lit.
Chapter 47 LCD Controller 6.Setting 6. Setting Table 6-1 Required Setting to Use LCD Setting Setting register * Presetting Common pin switching register (LCDCMR) LCD control register 1 (LCR1) Set divided resistors. LCD control register 0 (LCR0) Set ports Set display data. Select the frame period generation clock. Set a frame period. Select a duty cycle. (Activation) Enable LCD display. Port function register (PFR) Display data memory (VRAM) Setting procedure – See 7.8 and 7.9 See 7.1 See 7.2 See 7.
Chapter 47 LCD Controller 7.Q&A 7. Q&A 7.1 How do I specify pins as COM or SEG output pins? Use COM and SEG output settings. Software can switch ports to COM or SEG output ports. To do so, write “1” to the output designation bit (COM[3:0], SEG[39:0]).
Chapter 47 LCD Controller 7.
Chapter 47 LCD Controller 7.Q&A 7.2 How do I set VRM? The following tables show the relationship between pins and the bit positions of VRAM(n).
Chapter 47 LCD Controller 7.Q&A 7.4 How do I set a duty cycle? Use the display mode select bit (LCR0.MS[1:0]). Controlled operation To deactivate LCD (Pin output: “L”) To set the 1/2 duty cycle output mode To set the 1/3 duty cycle output mode To set the 1/4 duty cycle output mode Display mode select bit (MS[1:0]) Set to “00”. Set to “01”. Set to “10”. Set to “11”. N (Time division number) N/A 2 3 4 The display mode select bit also serves as an operation start/stop control bit. 7.
Chapter 47 LCD Controller 7.Q&A 7.9 How do I select internal or external divided resistors? • When using internal divided resistors: V3 V3 V2 V1 V0 R V2 R V1 R V0 N-ch LCDC operation enabled • When using external divided resistors: The LCD driving voltage can be generated by connecting external divided resistors to the LCD drive power supply pins (V0 to V3).
Chapter 47 LCD Controller 8.Caution 8. Caution • To access VRAM, be sure to use byte-by-byte access. • Switching the frame period generation clocks: Frame period generation clocks (LCR0:CSS) can be switched even during LCD display. However, switching may cause some screen flicker. To avoid such flicker, be sure to set the blanking select bit (LCR0:BK) to “1” (blank display) before switching. • Depending on your LCD, different external divided resistors are used. Use appropriate resistor values.
Chapter 48 Clock Monitor 1.Overview Chapter 48 Clock Monitor 1. Overview The Clock Monitor is a macro that outputs internal clock signals to a terminal to externally monitor them. The Clock Monitor provides a function to divide the frequency of a clock signal before it outputs to the terminal, thus allowing the clock signal to be used as an event at which external circuits act in synchronization with a MCU function. MONCLK Terminal Internal clocks Selector Prescaler 2.
Chapter 48 Clock Monitor 3.Configuration 3.
Chapter 48 Clock Monitor 4.Register 4. Register 4.1 Clock Monitor Configuration Register A register for output settings of an internal clock signal • CMCFG: Address 04AFH (Access: Byte) 7 CMPRE3 0 R/W 6 CMPRE2 0 R/W 5 CMPRE1 0 R/W 4 CMPRE0 0 R/W 3 CMSEL3 0 R/W 2 CMSEL2 0 R/W 1 CMSEL1 0 R/W 0 CMSEL0 0 R/W bit Initial value Attributes (For attributes, refer to “Meaning of Bit Attribute Symbols (Page No.10)”.
Chapter 48 Clock Monitor 4.Register • CSCFG: Address 04AEh (Access: Byte) 7 6 EDSUEN PLLLOCK 5 RCSEL 4 MONCKI 3 CSC3 2 CSC2 1 CSC1 0 CSC0 0 X 0 0 0 0 0 0 X X X X X X X X R/W R R/W R/W R/W R/W R/W R/W bit Initial value (INIT pin input, watchdog reset) Initial value (software reset) Attribute (See “Meaning of Bit Attribute Symbols (Page No.10)” for details of the attributes.
Chapter 48 Clock Monitor 5.Operation 5. Operation The following diagram shows the output waveforms of the Clock Monitor. (1) The MONCLK pin is in high impedance state. (2) CMSEL is set from “0000” (no clock selected) to the selected (and prescaled) clock. (3) The MONCLK pin changes to output “L” status (output “H” if MONCKI is set to ‘1’) for one period of the internal (prescaled) clock.
Chapter 48 Clock Monitor 6.Settings 6. Settings Table 6-1 Settings for Using Clock Monitor Settings Set a prescaler value Set a source clock Change the mark level Enable clock monitor output.(MONCLK) Setting Procedure* Setting Registers Clock Monitor Prescaler (CMCFG.CMPRE[3:0]) Clock Monitor Selection (CMCFG.CMSEL[3:0]) Clock Monitor Inverter (CSCFG.MONCKI) See 7.1 See 7.1 See 7.1 See 7.2 See 7.3 Clock Monitor Selection (CMCFG.CMSEL[3:0]) *:For each setting procedure, refer to an appropriate section.
Chapter 48 Clock Monitor 8.Caution 8. Caution Due to the glitch free switching mechanism it is necessary to follow these rules when switching the clock source (CMCFG3:0) or the prescaler ratio (CMPRE3:0): - The CMPRE3:0 registers can only be written if the CMCFG3:0 registers are currently 0x0. - The CMPRE3:0 registers can only be written if the CMCFG3:0 registers are written to 0x0 within the same write access.
Chapter 48 Clock Monitor 8.
Chapter 49 Real-Time Clock 1.Overview Chapter 49 Real-Time Clock 1. Overview Real-time Clock (RTC) continues to count elapsed time even in the STOP mode to provide the current real time (HH/MM/SS) based on main oscillation (4MHz), sub oscillation (32kHz) or RC oscillation (~100kHz). This allows precise time counting without a return from an interrupt during stand by periods.
Chapter 49 Real-Time Clock 3.Configuration 3.
Chapter 49 Real-Time Clock 4.Registers 4. Registers 4.1 WTCR: RTC Control Register This register is used to control behavior of the Real-time Clock module.
Chapter 49 Real-Time Clock 4.Registers When the minute counter overflows, this flag is set to “1”. • bit10: 1-minute interrupt request flag Operation INT1 0 1 Read No interrupt requests Generate interrupt requests at 1-minute intervals. Write Clear the flag. Writing does not affect the operation. • bit9: Enable interrupt requests at 1-second intervals INTE0 0 1 Operation No interrupt requests Generate interrupt requests at 1-second intervals.
Chapter 49 Real-Time Clock 4.Registers recommended that the Sub-Second register is updated while the ST bit is "0". However, if this update is done immediately after an RTC second interrupt there should be enough time to securely modify the registers until the next reload operation (next second interrupt) even if ST is not set to "0" and the module is in operation.
Chapter 49 Real-Time Clock 4.Registers 4.2 WTBR: Sub-Second Registers These registers are used to hold values to be reloaded to the 21 bit down counter.
Chapter 49 Real-Time Clock 4.Registers 4.3 WTHR/WTMR/WTSR: Hour/Minute/Second Registers These registers hold time information (HH/MM/SS) for Real-time Clock.
Chapter 49 Real-Time Clock 5.Operation 5. Operation This section describes Real-time Clock operation.
Chapter 49 Real-Time Clock 5.Operation (10) (11) (12) (14) (17) (20) When the second counter counts up to “59”, the counter is cleared next time when the counter counts up, at which the minute counter counts up, generating a 1-minute interrupt request. When the minute counter counts up to “59”, the counter is cleared next time when the counter counts up, at which the hour counter counts up, generating a 1-hour interrupt request.
Chapter 49 Real-Time Clock 6.Setting 6. Setting Table 6-1 Required Settings to Run Real-time Clock Setting Set a reload value to the sub-second registers. Initialize Real-time Clock. Set time (hour/minute/second). Activate Real-time Clock. Setting Registers Sub-second registers (WTBR0,WTBR1 and WTBR2) RTC control register (WTCR) Hour/minute/second registers (WTHR/WTMR/WTSR) RTC control register (WTCR) Setting Procedure * See 7.1. See 7.2. See 7.3. See 7.4.
Chapter 49 Real-Time Clock 7.Q&A 7. Q&A 7.1 How do I set the count period of 1 second? Stop Real-time Clock and then set the sub-second register WTBR. The reload value corresponds to the time needed for half a second, i.e. • At 32 kHz RTC operation set WTBR to “001FFFH”. • At 100 kHz RTC operation set WTBR to “0061A7H”. • At 4 MHz RTC operation set WTBR to “0F423FH”. 7.2 How do I initialize Real-time Clock? Use the start bit (WTCR.ST).
Chapter 49 Real-Time Clock 7.Q&A 7.8 What are interrupt-related registers? RTC interrupt vector and level settings. The following table shows the relationship between interrupt levels and vectors. For details on interrupt levels and vectors, refer to “Chapter 24 Interrupt Control (Page No.311)”. Interrupt vectors (Default) #132 (0FFDECh) Interrupt level set bit (ICR[4.
Chapter 49 Real-Time Clock 8.Caution 8. Caution • Setting the interrupt request flags (WTCR.INT0, WTCR.INT1, WTCR.INT2, WTCR.INT4 and WTCER.INT4) to “1” due to overflow, and writing “0” to that bit have occurred at the same time, the flag is set to “1”. (Flag setting takes precedence.) • Writing “1” to the update bit (ETCR.UPDT) and update completion have occurred at the same time, the update bit (UPDT) is set to “0”.
Chapter 49 Real-Time Clock 8.Caution lower than that of the peripheral clock (CLKP). If not, correct values cannot be read from WTHR/WTMR/ WTSR. • Note that only byte-access is allowed to these register. So, when these registers are read at the very timing of changing over the hour or minute boundary as shown below, there is a possibility of misjudging the time. So, read several times to get a logically consistent value.
Chapter 50 Subclock Calibration Unit 1.Overview Chapter 50 Subclock Calibration Unit 1. Overview The Clock Calibration Module provides possibilities to calibrate the 32kHz oscillation clock or 100kHz RC oscillation clock with respect to the 4MHz oscillation clock. This chapter gives an overview of the calibration unit, describes the registers and provides some application notes. 1.
Chapter 50 Subclock Calibration Unit 2.Block Diagram 2.
Chapter 50 Subclock Calibration Unit 3.Timing 3.
Chapter 50 Subclock Calibration Unit 4.Clocks 4. Clocks The module operates with 3 different clocks: The 4 MHz clock OSC4, the 32 kHz clock OSC32 (ot the 100kHz clock OSC100) and the peripheral clock CLKP. Synchronization circuits adapt the different domains.
Chapter 50 Subclock Calibration Unit 5.Register Description 5. Register Description This section lists the registers of the calibration unit and describes the function of each register in detail. ■ Calibration Unit Control Register (CUCR) Control Register low byte Address : 0004B0H Read/write ⇒ Default value⇒ 7 6 5 4 3 2 - - - STRT - - (R) (0) (R) (0) (R) (0) (R/W) (0) 1 0 INT INTEN ⇐ Bit no.
Chapter 50 Subclock Calibration Unit 5.
Chapter 50 Subclock Calibration Unit 5.Register Description BIT[0]: INTEN - Interrupt enable 0 interrupt disabled (default) 1 interrupt enabled This is the interrupt enable bit corresponding to the INT bit. When this bit is set to 1 and the INT bit is set by the hardware, the calibration module signals an interrupt to the CPU. The INT-bit itself is not affected by the INTEN bit and is set by hardware even if interrupts are disabled (INTEN=0).
Chapter 50 Subclock Calibration Unit 5.Register Description 5.2 32 kHz / 100 kHz Timer Data Register (16 bit) (CUTD) The 32kHz/100kHz Timer Data Register (CUTD) holds the value which determines the duration of calibration (32kHz/100kHz reload value) 32/100kHz Timer Register high byte Address : 0004B2H 15 14 13 12 11 10 9 8 TDD15TDD14 TDD13 TDD12 TDD11TDD10 TDD9 TDD8 ⇐ Bit no.
Chapter 50 Subclock Calibration Unit 5.Register Description Table 5-1 32kHz : Ideal measurement results depending on measurement duration duration of calibration CUTD value CUTR value 2 sec 0x0000 0x7A1200 1.75 sec 0xE000 0x6ACFC0 1.5 sec 0xC000 0x5B8D80 1.25 sec 0xA000 0x4C4B40 1 sec 0x8000 0x3D0900 0.75 sec 0x6000 0x2DC6C0 0.5 sec 0x4000 0x1E8480 0.
Chapter 50 Subclock Calibration Unit 5.Register Description 5.3 4 MHz Timer Data Register (24 bits) (CUTR) The Timer Data Register (CUTR) holds the value of the calibration result (4MHz counter) Precaution: Reading this register during calibration, results in random values. The end of calibration is indicated by the INT-bit and the STRT-bit in the CUCR-register. After INT has changed from 0 to 1 / STRT has changed from 1 to 0, the value of CUTR is valid.
Chapter 50 Subclock Calibration Unit 6.Application Note 6. Application Note This section lists application notes concerning accuracy of the calibration, power dissipation and measurement duration. ● 32kHz The setting of the 32KHz Timer Data Register can be calculated in the following way. If the duration of 1 second is desired for the calibration, 8000Hex = 32768Dec should be set in the 32kHz Timer Data Register and it represents 32,768 pulses of the 32.768kHz oscillation clock.
Chapter 50 Subclock Calibration Unit 6.Application Note ■ Accuracy: The accuracy of the calibration is dependent on the clock frequency used by the 4MHz Timer and duration of the calibration. The maximum error of the 4MHz timer is +/- 1 digit. If the clock frequency is 4MHz and duration of the calibration is 1 second, the achieved accuracy is calculated in the following way: 0.25us (Clock cycle time) / 1 second (duration)=0.25 ppm.
Chapter 51 Low Voltage Reset/Interrupt 1.Overview Chapter 51 Low Voltage Reset/Interrupt 1. Overview • Module for generating a low voltage reset or interrupt depending on the supply state of either the internal or external supply voltage. 2.
Chapter 51 Low Voltage Reset/Interrupt 3.Registers 3. Registers 3.1 LV Detection Control Registers Controls the low voltage detection function. • LVDET: Address 04C5h (Access: Byte, Halfword, Word) 7 - 6 LVSEL 5 LVEPD 4 LVIPD 3 LVREN 2 - 1 LVIEN 0 LVIRQ - 0 0 0 0 - 0 0 - X X X X - 0 0 R0/W0 R/W R/W R/W R/W R0/W0 R/W R/W bit Initial value (INIT pin input, watchdog reset) Initial value (Software reset) Attribute (See “Meaning of Bit Attribute Symbols (Page No.
Chapter 51 Low Voltage Reset/Interrupt 3.Registers • LVSEL: Address 04C4h (Access: Byte, Halfword, Word) 7 LVESEL3 6 LVESEL2 5 LVESEL1 4 LVESEL0 3 LVISEL3 2 LVISEL2 1 LVISEL1 0 LVISEL0 0 0 0 0 0 1 1 1 X X X X X X X X R/W R/W R/W R/W R/W R/W R/W R/W bit Initial value (INIT pin input, watchdog reset) Initial value (Software reset) Attribute (See “Meaning of Bit Attribute Symbols (Page No.10)” for details of the attributes.
Chapter 51 Low Voltage Reset/Interrupt 3.
Chapter 52 Regulator Control 1.Overview Chapter 52 Regulator Control 1. Overview • Module for controlling the behaviour of the MAIN-Regulator and SUB-Regulator in the device modes. 2.
Chapter 52 Regulator Control 3.Registers 3. Registers 3.1 Regulator Control Registers Controls the regulator function. • REGCTR: Address 04CFh (Access: Byte, Halfword, Word) 7 - 6 - 5 - 4 MSTBO 3 - 2 - 1 0 MAINKPEN MAINDSBL X X X X X X 0 0 X X X X X X X X R0/WX R0/WX R0/WX R R0/WX R0/WX R/W R/W (See “Meaning of Bit Attribute Symbols (Page No.10)” for details of the attributes.) • Bit7-5: Reserved bit. The read value is always “0”. • Bit4: Main regulator Standby output flag.
Chapter 52 Regulator Control 3.Registers • REGSEL: Address 04CEh (Access: Byte, Halfword, Word) 7 - 6 - 5 4 FLASHSEL MAINSEL 3 2 1 0 SUBSEL3 SUBSEL2 SUBSEL1 SUBSEL0 0 0 0 0 0 1 1 0 X X X X X X X X R0/WX R0/WX R/W R/W R/W R/W R/W R/W bit Initial value (INIT pin input, watchdog reset) Initial value (Software reset) Attribute (See “Meaning of Bit Attribute Symbols (Page No.10)” for details of the attributes.) • Bit7-6: Reserved bit. The read value is always “0”.
Chapter 52 Regulator Control 3.
Chapter 53 Fixed Mode-Reset Vector / BOOT-ROM 1.Overview Chapter 53 Fixed Mode-Reset Vector / BOOT-ROM 1. Overview The Boot ROM is a fixed start-up routine, which is located at memory addresses 0xB000 to 0xBFFF. The entry point 0xBFF8 is determined by the Fixed Reset Vector if the device is configured with the mode pins set to MD[2:0]=”000” (internal ROM/vector mode).
Chapter 53 Fixed Mode-Reset Vector / BOOT-ROM 2.
Chapter 53 Fixed Mode-Reset Vector / BOOT-ROM 2.Check for Boot Conditions 2.2 Flash devices of MB91460 series (MB91F46x) After the chip initialization and saving the RSRR (Reset Cause Register) to CPU register R4, there is a check for boot conditions. All Flash devices have two Boot Security Vectors (BSV1: 0x14:8004, BSV2: 0x14:800C).
Chapter 53 Fixed Mode-Reset Vector / BOOT-ROM 2.Check for Boot Conditions the internal bootloader is entered. Otherwise Boot ROM is left and application is also started at default user program entry address 0x0F:4000.
Chapter 53 Fixed Mode-Reset Vector / BOOT-ROM 2.Check for Boot Conditions 2.3 Internal Bootloader Description If a valid boot condition for entering the internal bootloader was met, the ASCII-character “F” (0x46) will be transmitted via UART0 (MB91V460) or UART4 (MB91460 series flash derivatives) to indicate that the bootloader is ready to accept commands. There are five different commands supported by the internal bootloader. See the table below for serial protocol of these commands.
Chapter 53 Fixed Mode-Reset Vector / BOOT-ROM 3.Registers modified by Boot ROM 3. Registers modified by Boot ROM The Boot ROM initializes the chip and changes the settings of some registers (see table below). (Note) The RSRR register can only be read once. After reading the RSRR-register, the contents will be present in R4 (C-Compiler convention for parameters) after a branch to application start or the address specified by the BootSecurity-Vector. 3.
Chapter 53 Fixed Mode-Reset Vector / BOOT-ROM 4.Flash Access Mode Switching 4. Flash Access Mode Switching On MB91460 series flash devices it is possible to switch between different flash access modes. These modes are depending on device type.
Chapter 53 Fixed Mode-Reset Vector / BOOT-ROM 5.Bootloader Update Strategy 5. Bootloader Update Strategy Some applications require the possibility of software updates in the final product without great effort. To be able to program an updated application to the microcontroller, all connected busses (I2C, CAN, LIN, K-Line etc.) can be used, so that the microcontroller can remain ‘embedded’ in a bigger system.
Chapter 53 Fixed Mode-Reset Vector / BOOT-ROM 5.Bootloader Update Strategy By use of this bootloader the application as well as user bootloader 2 can be re-programmed. If you want to re-program user bootloader 1, then functions in user bootloader 2 have to be called to erase the sector where user bootloader 1 and the Magic Number are located. After erasing, program the new user bootloader to the section. As last step, the Magic Number should be set to 0x000A897A.
Chapter 53 Fixed Mode-Reset Vector / BOOT-ROM 5.
Chapter 54 Flash Memory 1.Overview Chapter 54 Flash Memory This chapter describes the use of the built-in flash memory. 1. Overview The MB91F46x devices have built-in Flash memory with a variety of capacities, capable of batch-erasing all sectors or erasing on the sector level via single +3.0V-5.5V power supply, and writing by the FR-CPU at the half-word (16-bit) and word (32-bit) level. 2. Features • • • • • Power: Single +3.0-5.
Chapter 54 Flash Memory 3.Configuration 3.
Chapter 54 Flash Memory 3.Configuration 3.
Chapter 54 Flash Memory 4.Registers 4. Registers For the description of the Flash related registers, refer to Chapter 11 Memory Controller (Page No.167). 5. Access Modes This section describes the Flash memory access modes. 5.1 Access from the FR-CPU The following three types of access mode are available: ■ 64-bit CPU mode (read/execute), not for all devices This mode does not allow data erase/write.
Chapter 54 Flash Memory 6.Flash Access Mode Switching 6. Flash Access Mode Switching On MB91460 series flash devices it is possible to switch between different flash access modes. These modes are depending on device type.
Chapter 54 Flash Memory 6.Flash Access Mode Switching 6.1 Flash Memory Mode Resetting after setting the MD2, MD1 and MD0 pins to “1”, “1” and “1” will halt the MCU functions. At this time, the Flash memory's interface circuit functions are emabled for direct control of the Flash memory unit from external pins, by directly linking some of the signals to the Flash memory unit's control signal. In this mode, the Flash memory appears to the external pins as a stand-alone unit.
Chapter 54 Flash Memory 7.Auto Algorithms 7. Auto Algorithms Writes and erases to Flash memory are performed by launching the Flash memory's own Auto Algorithms. 7.1 Command Operation Auto Algorithms are launched by writing one to six half words (16 bits) to the Flash memory in succession. This is called a “command.” Writing an illegal address or data, or writing them in the incorrect order, will reset the Flash memory to read mode.
Chapter 54 Flash Memory 7.Auto Algorithms 7.2 Auto Algorithm Commands ■ Read/reset command Issue a Read/reset command sequence to recover to read mode after a timing limit has been exceeded. Data is read from Flash memory via the read cycle. Flash memory stays in a read state until another command is input. When powered up, Flash memory is automatically set to read/reset. In this case, commands are not required for data reading.
Chapter 54 Flash Memory 7.Auto Algorithms ■ Chip erase Chip erase (erase all sectors at once) is performed via six accesses. First, there are two “unlock” cycles, after which a setup command is written. This is then followed by two more “unlock” commands before the chip erase command. The user does not have to write to Flash memory before a chip erase can be performed.
Chapter 54 Flash Memory 7.Auto Algorithms has halted, by entering the address of an erased sector, and monitoring the values read from bits 6 and 7. Additionally, writes of erase-suspend commands are ignored. When erasing is halted, the Flash memory goes into erase-suspend read mode. In this mode, data reads from sectors where erase has not been paused are enabled, but for other sectors, it is the same as standard reading.
Chapter 54 Flash Memory 7.Auto Algorithms 7.3 Hardware Sequence Flag This Flash memory performs the write/erase sequence via Auto Algorithms. It thus has hardware for informing the outside world when it has finished internal operations. Hardware sequence flag The hardware sequence flag can be obtained as data by reading any address (an odd address during byte access) from the Flash memory while an Auto Algorithm is executing.
Chapter 54 Flash Memory 7.Auto Algorithms 7.4 FLCR: Hardware Sequence Flag • FLCR: Address. Any address in Flash memory. (Access: Byte or half-word) 7 DPOLL R 6 TOGGLE R 5 TLOVER R 4 RX 3 SETIMR R 2 TOGGL2 R 1 RX 0 RX bit Initial value Attribute • bit 7: Data polling (DPOLL) • Auto write under way If data is read while the auto write algorithm is executing, the Flash memory outputs the data with the last value written to bit 7 inverted.
Chapter 54 Flash Memory 7.Auto Algorithms • bit 4: Undefined: The read value is indeterminate. • bit 3: Sector erase timer (SETIMR) • During sector erase After executing the first sector-erase command sequence, Flash memory goes into standby for sector erase. During this time, bit 3 is “0”. After the sector-erase wait period ends, it outputs “1”. The data-polling and toggle bits become enabled after the first sector-erase command sequence is executed.
Chapter 54 Flash Memory 7.Auto Algorithms 7.5 Sample Use of Hardware Sequence Flag It is possible to determine the state of the Flash memory’s internal Auto Algorithms using the hardware sequence flag mentioned above. As an example, the figures below show the write/erase determination sequence when the data-polling function is used, and when the toggle-bit function is used.
Chapter 54 Flash Memory 8.Caution 8. Caution • Please review the MBM29LV400TC data sheet in conjunction with this document. • CPU mode When in CPU mode, the address-allocation method is different than when writing via a parallel Flash programmer. Refer to “3.1 Address conversion from CPU Mode to Flash Programming Mode (Page No.995)”. • Flash memory mode (writing via parallel Flash programmer) This Flash memory allows writing via an external device, by means of the parallel Flash programmer.
Chapter 54 Flash Memory 8.
Chapter 55 Flash Security 1.Overview Chapter 55 Flash Security 1. Overview • Module for controlling the read and write access protection to the embedded Flash memory 2.
Chapter 55 Flash Security 3.Flash Security Vectors 3. Flash Security Vectors 3.1 Vector addresses Two Flash Security Vectors (FSV1, FSV2) are located parallel to the Boot Security Vectors (BSV1, BSV2) controlling the protection functions of the flash security module: FSV1: 0x14:8000 FSV2: 0x14:8008 BSV1: 0x14:8004 BSV2: 0x14:800C Remark: The addresses of both boot security vectors and flash security vectors depend on the size and the data width configuration of the embedded flash memory.
Chapter 55 Flash Security 3.Flash Security Vectors ■ FSV1 (bits 15 to 0) The setting of the Flash Security Vector FSV1 bits [15:0] is responsible for the individual write protection of the 8 kByte sectors. It is only evaluated if write protection bit FSV1[17] is set.
Chapter 55 Flash Security 3.Flash Security Vectors 3.3 Security Vector FSV2 The setting of the Flash Security Vector FSV2 bits [31:0] is responsible for the individual write protection of the 64 kByte sectors. It is only evaluated if write protection bit FSV1[17] is set.
Chapter 55 Flash Security 4.Register 4. Register 4.
Chapter 55 Flash Security 4.Register Remark: The Flash Security Vector Re-Fetch sequence is especially intented to be used after a chip erase command to update the security status without the need of applying an external INITX reset or after changing the status of the FSV1 security vector. Remark: For both Security Vector Re-Fetch and CRC32 it is not recommended to start these sequences from programs located in the Flash Memory itself.
Chapter 55 Flash Security 4.Register • Bit31-25: Reserved bit. The read value is always “0”. • Bit24: RDY: CRC32 Sequence Ready RDY 0 1 Function CRC32 sequence running or not yet started CRC32 sequence ready (data in the FSCR0 register is valid) • Bit23-20: Reserved bit. The read value is always “0”.
Chapter 55 Flash Security 4.
Chapter 56 Electrical Specification Chapter 56 Electrical Specification See the appropriate data sheet for the electrical specification of each device.
Chapter 56 Electrical Specification 1018
FR60 MB91460 Series Hardware Manual European Microcontroller Design Centre Author : MBo
CM71-xxxxx-1E FUJITSU SEMICONDUCTOR • CONTROLLER MANUAL FR60 32-BIT MICROCONTROLLER MB91460 Series User's Manual Jan 2005 the zero edition Published FUJITSU LIMITED Edited European Microcontroller Design Centre Electronic Devices
