FUJITSU SEMICONDUCTOR CM25-10146-1E CONTROLLER MANUAL F2MC-8L 8-BIT MICROCONTROLLER MB89950/950A Series HARDWARE MANUAL
F2MC-8L 8-BIT MICROCONTROLLER MB89950/950A Series HARDWARE MANUAL FUJITSU LIMITED
PREFACE ■ Objectives and Intended Reader The MB89950/950A series has been developed as a general-purpose version of the F2MC-8L family consisting of proprietary 8-bit, single-chip microcontrollers. The MB89950/950A series is applicable to a wide range of applications from consumer products to industrial equipment, including portable devices.
CHAPTER 12 "LCD CONTROLLER/DRIVER" This chapter describes the functions and operation of the LCD controller/driver. APPENDIX This appendix includes I/O maps, instruction lists, and other information. • • • • • The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering.
READING THIS MANUAL ■ Notations of the Register Name and Pin Name ● Example for description of register name and bit name ● Notations of a double-purpose pin P22/SCK pin Some pins can be used by switching their functions using, for example, settings by a program. Each double-purpose pin is represented by separating the name of each function using "/".
■ Documents and Development Tools Required for Development Items necessary for the development of this product are as follows. To obtain the necessary documents and development tools, contact a company sales representative.
❍ What is needed for evaluation on the one-time PROM microcomputer (if the programming operation is performed at your side) [Check field] MB89P955 EPROM programmer (Programmer available for the MBM27C1001) Package conversion adapter ROM-64QF2-28DP-8L3 ● Development tools [Check field] MB89PV950 (piggyback/evaluation device) Development tool Main unit Pod MB2141A + MB2144-505 Probe MB2144-203 To use a the other development environment, contact respective makers.
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CONTENTS CHAPTER 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 CHAPTER 2 2.1 OVERVIEW ................................................................................................... 1 MB89950/950A Series Features ........................................................................................................... 2 MB89950/950A Series Product Range ................................................................................................. 4 Differences among Products ....................................
CHAPTER 4 I/O PORTS .................................................................................................. 69 4.1 Overview of I/O Ports .......................................................................................................................... 4.2 Port 0 ................................................................................................................................................. 4.2.1 Port 0 Data Register (PDR0) ................................................
7.9 Program Example for 8-bit PWM Timer ............................................................................................ 138 CHAPTER 8 PULSE WIDTH COUNT TIMER (PWC) ................................................... 141 8.1 Overview of Pulse Width Count Timer .............................................................................................. 8.2 Block Diagram of Pulse Width Count Timer ..................................................................................... 8.
CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT (EDGE) ............................................ 223 11.1 Overview of the External Interrupt Circuit ........................................................................................ 11.2 Block Diagram of the External Interrupt Circuit ................................................................................. 11.3 Structure of the External Interrupt Circuit ......................................................................................... 11.3.
CHAPTER 1 OVERVIEW This chapter describes the main features and basic specifications of the MB89950/950A series. 1.1 "MB89950/950A Series Features" 1.2 "MB89950/950A Series Product Range" 1.3 "Differences among Products" 1.4 "Block Diagram of MB89950/950A Series" 1.5 "Pin Assignment" 1.6 "Package Dimensions" 1.
CHAPTER 1 OVERVIEW 1.1 MB89950/950A Series Features The MB89950/950A series is a line of the general-purpose, single-chip microcontrollers. In addition to a compact instruction set, the microcontrollers contain a variety of peripheral functions such as an LCD controller/driver, UART, a serial I/O, PWC timer, PWM timer and external interrupts. ■ MB89950/950A series features ● Various package options • QFP packages (0.
CHAPTER 1 OVERVIEW ● External interrupts (2 channels) • Two channels are independent and capable of wake-up from low-power consumption mode (with an edge detection function). ● Standby mode (low-power mode) • Stop mode (oscillation stops so as to minimize the current consumption). • Sleep mode (CPU stops so as to reduce the current consumption to approx. 1/3 of normal). ● I/O ports: max.
CHAPTER 1 OVERVIEW 1.2 MB89950/950A Series Product Range The MB89950/950A series contains 4 different models. Table 1.2-1 "MB89950/950A series product line-up" lists the product range and Table 1.2-2 "Common specifications for the MB89950/950A series" lists the common specifications. ■ MB89950/950A series product range Table 1.
CHAPTER 1 OVERVIEW Table 1.2-2 Common specifications for the MB89950/950A series Parameter Specification CPU functions Number of instructions: 136 Instruction bit length: 8 bits Instruction length: 1 to 3 bytes Data bit length: 1, 8, 16 bits Minimum execution time: 0.80 µs to 12.8 µs at 5 MHz Interrupt processing time: 7.26 µs to 115.
CHAPTER 1 OVERVIEW 1.3 Differences among Products This section describes the differences among the 4 products in the MB89950/950A series and lists points to note in product selection. ■ Differences among products and points to note for product selection Table 1.3-1 Package and corresponding products Package Part number MB89951A MB89953A MB89P955 FPT-64P-M09 (LQFP-64, 0.
CHAPTER 1 OVERVIEW 1.4 Block Diagram of MB89950/950A Series Figure 1.4-1 "MB89950/950A series overall block diagram" shows the block diagram of the MB89950/950A series. ■ MB89950/950A series block diagram Figure 1.
CHAPTER 1 OVERVIEW 1.5 Pin Assignment Figure 1.5-1 "FPT-64P-M09 pin assignment" and Figure 1.5-2 "MQP-64C-P01 pin assignment" show the pin assignment diagrams for the MB89950/950A series. ■ FPT-64P-M09 pin assignment 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 VCC SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 Figure 1.
CHAPTER 1 OVERVIEW ■ MQP-64C-P01 pin assignment 64 63 62 61 60 59 58 57 56 55 54 53 52 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 Vcc SEG13 SEG14 SEG15 SEG16 SEG17 Figure 1.
CHAPTER 1 OVERVIEW 1.6 Package Dimensions Two types of packages are available for MB89950/950A series. Figure 1.6-1 "FPT-64PM09 package dimensions" and Figure 1.6-2 "MQP-64C-P01 package dimensions" show the package dimensions. ■ FPT-64P-M09 package dimensions Figure 1.6-1 FPT-64P-M09 package dimensions 64-pin plastic LQFP Lead pitch 0.65 mm Package width package length 12 12 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 1.
CHAPTER 1 OVERVIEW ■ MQP-64C-P01 package dimensions Figure 1.6-2 MQP-64C-P01 package dimensions 64-pin ceramic MQFP Lead pitch 1.00 mm Lead shape Straight Motherboard material Ceramic Mounted package material Plastic (MQP-64C-P01) 64-pin ceramic MQFP (MQP-64C-P01) 18.70(.736)TYP INDEX AREA 16.30±0.33 (.642±.013) 15.58±0.20 (.613±.008) 12.00(.472)TYP 1.20 .047 +0.40 1.00±0.25 (.039±.010) +.016 1.00±0.25 (.039±.010) 1.27±0.13 (.050±.005) 22.30±0.33 (.878±.013) 24.70(.972) TYP 0.30(.
CHAPTER 1 OVERVIEW 1.7 I/O Pins and Pin Functions Table 1.7-1 "Pin description" and Table 1.7-2 "Pin description for external ROM (for MB89PV950 only)" list the MB89950/950A series I/O pins and their functions. Table 1.7-3 "I/O circuit type" lists the I/O circuit types. The letter in the "I/O circuit type" column in Table 1.7-1 "Pin description" refer to the letter in the "Type" column Table 1.7-3 "I/O circuit type". ■ I/O pins and pin functions Table 1.7-1 Pin description (1/2) Pin no.
CHAPTER 1 OVERVIEW Table 1.7-1 Pin description (2/2) Pin no. LQFP *1 16 17 MQFP Pin name I/O circuit type P41/PWM E General-purpose I/O port. Also serves as PWM timer toggle output (PWM). A pull-up resistor option is provided. E General-purpose I/O port. Also serves as pulse-width count timer input (PWC) and external interrupt input (INT1). The PWC and INT1 inputs are hysteresis type. A pull-up resistor option is provided.
CHAPTER 1 OVERVIEW Table 1.7-2 Pin description for external ROM (for MB89PV950 only) Pin no. Pin name I/O Function 66 VPP O For high-level output. 67 A12 68 A7 69 A6 70 A5 71 A4 O For address output. 72 A3 73 A2 74 A1 75 A0 77 O1 78 O2 I For data input. 79 O3 80 VSS O For power supply (GND). 82 O4 83 O5 84 O6 I For data input. 85 O7 86 O8 87 CE O For ROM chip enable. The High level is output in standby mode. 88 A10 O For address output.
CHAPTER 1 OVERVIEW Table 1.7-3 I/O circuit type (1/2) Type Circuit Remarks A • Crystal oscillator • Feedback resistor: About 1 MΩ (5 V) X1 N-ch P-ch X0 P-ch N-ch N-ch Standby control signal B • CMOS input • Pull-down resistor (N-ch): About 50 kΩ (5 V) R C • Output pull-up resistor (P-ch): About 50 kΩ (5 V) • Hysteresis input R P-ch N-ch D P-ch • N-ch open-drain output • CMOS input • The segment driver output is optional.
CHAPTER 1 OVERVIEW Table 1.
CHAPTER 2 HANDLING DEVICES This chapter describes points to note when using the general-purpose single-chip microcontroller. 2.
CHAPTER 2 HANDLING DEVICES 2.1 Notes on Handling Devices This section lists points to note regarding the power supply voltage, pins, and other device handling aspects. ■ Notes on handling devices ● Preventing latch-up Latch-up may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins other than medium to high-voltage pins or if higher than the voltage which shows on Absolute Maximum Ratings is applied between VCC and VSS.
CHAPTER 2 HANDLING DEVICES ● Recommended screening conditions The OTPROM product should be screened by high-temperature aging before mounting. Verify program High-temperature aging (150 C, 48Hrs) Read Mount The programming test cannot be performed for all bits of the preprogrammed OTPROM product due to its characteristics. Consequently, 100% programming yielding cannot be ensured. ● Treatment of N.C. pins Be sure to leave (internally connected) N.C. pins open.
CHAPTER 2 HANDLING DEVICES 20
CHAPTER 3 CPU This chapter describes the functions and operation of the CPU. 3.1 "Memory Space" 3.2 "Dedicated Registers" 3.3 "General-purpose Registers" 3.4 "Interrupts" 3.5 "Resets" 3.6 "Clocks" 3.7 "Standby Modes (Low-power Consumption)" 3.
CHAPTER 3 CPU 3.1 Memory Space The microcontrollers of the MB89950/950A series offer a memory space of 64 Kbytes. The memory space contains the I/O area, RAM area, ROM area, and external area. The memory space contains areas used for special purposes such as the general-purpose registers and vector table. ■ Memory space structure ● I/O area (addresses: 0000H to 007FH) • Control registers and data registers for the internal peripheral functions are located in this area.
CHAPTER 3 CPU ■ Memory map Figure 3.
CHAPTER 3 CPU 3.1.1 Special Areas In addition to the I/O area, the special purpose areas in the memory space include the general-purpose register area and the vector table area. ■ General-purpose register areas (addresses: 0100H to 01FFH) • Provides auxiliary registers for 8-bit arithmetic operation and transfer instructions. • Allocated to a region of the RAM area. Can also be used as normal RAM.
CHAPTER 3 CPU ■ Vector table area (addresses: FFC0H to FFFFH) • Used as the vector table for the vector call instruction, interrupts, and resets. • The vector table is allocated at the top of the ROM area. The start address of the corresponding processing routine is set as data at each vector table address. Table 3.1-2 "Vector table" lists the vector table addresses referenced by the vector call instruction, interrupts, and resets. See Section 3.4 "Interrupts", Section 3.
CHAPTER 3 CPU 3.1.2 Storing 16-bit Data in Memory For 16-bit data and the stack, store the upper data in the lower memory address value. ■ Storing 16-bit data in RAM When writing 16-bit data to memory, store the upper byte at the lower address and the lower byte at the next address. Handle reading of 16-bit data in the same way. Figure 3.1-2 "Storing 16-bit data in memory" shows how 16-bit data is stored in memory. Figure 3.
CHAPTER 3 CPU 3.2 Dedicated Registers The dedicated registers in the CPU consist of the program counter (PC), two arithmetic operation registers (A and T), three address pointers (IX, EP, and SP), and the program status (PS). All registers are 16 bits. ■ Dedicated register configuration The dedicated registers in the CPU consist of seven 16-bit registers. Some of these registers are also able to be used as 8-bit register, using the lower 8 bits only. Figure 3.
CHAPTER 3 CPU ● Temporary accumulator (T) The temporary accumulator is an auxiliary 16-bit arithmetic operation register used to perform arithmetic operations with the data in the accumulator (A). The content of the temporary accumulator is treated as word data (16-bit) for word-length arithmetic operations with the accumulator and as byte data (8-bit) for byte-length arithmetic operations.
CHAPTER 3 CPU 3.2.1 Condition Code Register (CCR) The condition code register (CCR) located in the lower 8 bits of the program status (PS) consists of the C, V, Z, N, and H bits indicating the results of arithmetic operations and the contents of transfer data, and the I, IL1, and IL0 bits for control whether or not the CPU accepts interrupt requests. ■ Structure of condition code register (CCR) Figure 3.
CHAPTER 3 CPU ● Carry flag (C) Set to "1" when a carry from bit 7 or borrow to bit 7 occurs as a result of an arithmetic operation. Clear to "0" otherwise. Set to the shift-out value in case of a shift instruction. Figure 3.2-3 "Change of carry flag by shift instruction" shows the change of the carry flag by a shift instruction. Figure 3.
CHAPTER 3 CPU Reference: The interrupt level bits (IL1, IL0) are normally "11B" when the CPU is not processing an interrupt (during main program execution). See Section 3.4 "Interrupts" for details on interrupts.
CHAPTER 3 CPU 3.2.2 Register Bank Pointer (RP) The register bank pointer (RP) located in the upper 8 bits of the program status (PS) indicates the address of the general-purpose register bank currently in use. The RP is converted to form the actual address in general-purpose register addressing. ■ Structure of register bank pointer (RP) Figure 3.2-4 "Structure of register bank pointer" shows the structure of the register bank pointer. Figure 3.
CHAPTER 3 CPU 3.3 General-purpose Registers The general-purpose registers are a memory block made up of banks, with 8 x 8-bit registers per bank. The register bank pointer (RP) is used to specify the register bank. The function permits the use of up to 32 banks, but the number of banks that can actually be used depends on how much RAM the device has. Register banks are valid for interrupt processing, vector call processing, and subroutine calls.
CHAPTER 3 CPU ■ Features of general-purpose registers General-purpose registers have the following features: • RAM can be accessed at high-speed using short instructions (general-purpose register addressing). • Registers are grouped in blocks in the form of register banks. This simplifies the process of saving register contents and dividing registers by function.
CHAPTER 3 CPU 3.4 Interrupts The MB89950/950A series has 12 interrupt request inputs corresponding to peripheral functions. The interrupt level can be set independently. If an interrupt request output is enabled in the peripheral function, an interrupt request from a peripheral function is compared with the interrupt level in the interrupt controller. The CPU performs interrupt operation according to how the interrupt is accepted.
CHAPTER 3 CPU 3.4.1 Interrupt Level Setting Registers (ILR1, ILR2, ILR3) The interrupt level setting registers (ILR1, ILR2, ILR3) together contain 12 blocks of 2-bit data, with each data corresponding to an interrupt request from a peripheral function. The interrupt level for each interrupt is set in that interrupt’s corresponding 2-bit data (interrupt level setting bits). ■ Structure of interrupt level setting registers (ILR1, ILR2, ILR3) Figure 3.
CHAPTER 3 CPU 3.4.2 Interrupt Processing The interrupt controller transmits the interrupt level to the CPU when an interrupt request is generated by a peripheral function. If the CPU is able to receive the interrupt, the CPU temporarily halts the currently executing program and executes the interrupt processing routine.
CHAPTER 3 CPU 1. After a reset, all interrupt requests are disabled. - Initialize the peripheral functions that are to generate interrupts in the peripheral function initialization program, set the interrupt levels in the appropriate interrupt level setting registers (ILR1, ILR2, ILR3), and start peripheral function. - The interrupt level can be set to 1, 2 or 3. Level 1 is the highest priority, followed by level 2. Setting level 3 disables the interrupt for that peripheral function. 2.
CHAPTER 3 CPU 3.4.3 Multiple Interrupts Multiple interrupts can be performed by setting different interrupt levels to the interrupt level setting register for two or more interrupt requests from peripheral functions. ■ Multiple interrupts If the interrupt request having the higher interrupt levels occurs during the interrupt processing routines, the CPU halts the current interrupt process and switches to accept the interrupt with the higher priority. Interrupt levels can be set in the range 1 to 3.
CHAPTER 3 CPU 3.4.4 Interrupt Processing Time The total time from the generation of an interrupt request until control passes to the interrupt processing routine is the sum of the time required to complete execution of the current instruction and the interrupt handling time (the time required to prepare for interrupt processing). The maximum time for this process is 30 instruction cycles.
CHAPTER 3 CPU 3.4.5 Stack Operation during Interrupt Processing This section describes the saving of the register contents to the stack and restore operation during interrupt processing. ■ Stack operation at start of interrupt processing The CPU automatically saves the current contents of the program counter (PC) and program status (PS) to the stack when an interrupt is accepted. Figure 3.
CHAPTER 3 CPU 3.4.6 Stack Area for Interrupt Processing Interrupt processing execution uses the stack area in RAM. The contents of the stack pointer (SP) specifies the top address of the stack area. ■ Stack area for interrupt processing The subroutine call instruction (CALL) and vector call instruction (CALLV) use the stack area to save and restore the program counter (PC). The stack area is also used by the PUSHW and POPW instructions to temporarily save and restore registers.
CHAPTER 3 CPU 3.5 Resets The MB89950/950A series supports the following four types of reset source: • External reset • Software reset • Watchdog reset • Power-on reset (optional) At reset, main clock oscillation stabilization delay time may or may not occur by the operating mode and option settings. ■ Reset source Table 3.5-1 Reset source Reset source Reset condition External reset Set the external reset pin to the "L" level.
CHAPTER 3 CPU ● Power-on reset Products can be set to with or without power-on reset (optional). On products with power-on reset, turning on the power generates a reset. The reset operation is performed after the oscillation stabilization delay time has passed. Moreover, external reset signal is outputted by the reset output option. On products without power-on reset, an external reset circuit is required to generate a reset when the power is turned on.
CHAPTER 3 CPU 3.5.1 External Reset Pin Inputting an "L" level to the external reset pin generates a reset. If products are set to with the reset output (optional), the pin outputs an "L" level depending on internal reset sources. ■ Block diagram of external reset pin The external reset pin (RST) on products with the reset output is a hysteresis input type and N-ch opendrain output type with a pull-up resistor. The external reset pin on products without a reset output option is only for the reset input.
CHAPTER 3 CPU 3.5.2 Reset Operation When the CPU wakes up from a reset, the CPU selects the read address of the mode data and reset vector according to the mode pin settings, then performs a mode fetch. The mode fetch is performed after the oscillation stabilization delay time has passed when power is turned on to a product with power-on reset, or on wake-up from stop mode by a reset. If reset occurs during a write to RAM, the contents of the RAM address cannot be assured.
CHAPTER 3 CPU ■ Mode pin The MB89950/950A series devices are single-chip mode devices. The mode pin (MODA) must be tied to VSS. The mode pin settings determine whether the mode data and reset vector are read from internal ROM. Do not change the mode pin settings, even after the reset has completed. ■ Mode fetch When the CPU wakes up from a reset, the CPU reads the mode data and reset vector from internal ROM. ● Mode data (address: FFFDH) Always set the mode to "00H" (single-chip mode).
CHAPTER 3 CPU 3.5.3 Pin States during Reset Reset initializes the pin states. ■ Pin states during reset When a reset source occurs, with a few exceptions, all I/O pins (peripheral pins) go to the high-impedance state and the mode data is read from internal ROM (pins with a pull-up resistor (optional) go to the "H" level).
CHAPTER 3 CPU 3.6 Clocks The clock generator provides an internal oscillation circuit. By connecting with external resonator, the circuits generate the high speed main clock sources. Alternatively, externally generated clock input can be used. Clock controller controls the speed and supply of the clock signal according to the standby mode. ■ Clock supply map Oscillation of a clock and its supply to the CPU and peripheral circuit (peripheral functions) are controlled by the clock controller.
CHAPTER 3 CPU Figure 3.
CHAPTER 3 CPU 3.6.1 Clock Generator Enable and stop of the main clock oscillation are controlled by clock and stop mode respectively. ■ Clock generator ● Crystal or ceramic resonator Connect as shown in Figure 3.6-2 "Connection example for a crystal or ceramic resonator". Figure 3.6-2 Connection example for a crystal or ceramic resonator MB89950/950A series Main clock oscillator X0 C X1 C Reference: A piezoelectric resonator (FAR series) that contains the external capacitors can also be used.
CHAPTER 3 CPU ● External clock Connect the external clock to the X0 pin and leave X1 pin open, as shown in Figure 3.6-3 "Connection example for external clock". Figure 3.
CHAPTER 3 CPU 3.6.2 Clock Controller The clock controller contains the following four blocks: • Main clock oscillator • Clock controller • Oscillation stabilization delay time selector • Standby control register (STBC) ■ Block diagram of clock controller Figure 3.6-4 "Block diagram of clock controller" shows the block diagram of the clock controller. Figure 3.
CHAPTER 3 CPU ● Clock controller This circuit controls the supply of operating clocks to the CPU and peripheral circuits, selecting the clock based on the active mode: normal (RUN), or standby (sleep/stop) mode. Supply of the clock to the CPU is stopped until the clock supply stop signal in the oscillation stabilization delay time selector is released.
CHAPTER 3 CPU 3.6.3 Oscillation Stabilization Delay Time When the system goes to run mode from a state in which the main clock is stopped (such as at power-on, and in stop mode and etc.), a delay time is required for oscillation to stabilize before starting any operation. ■ Oscillation stabilization delay time After starting, ceramic, crystal, and other resonators typically require the time between several milliseconds and several tens of milliseconds to stabilize at their fixed oscillation frequency.
CHAPTER 3 CPU ● Oscillation stabilization delay time at reset The oscillation stabilization delay time at reset (the initial values of WT1 and WT0) is selected as an option setting. Products with power-on reset require an oscillation stabilization delay time when exit from stop mode is triggered by resets in power-on reset, or external reset. Table 3.6-1 "Main clock startup conditions vs.
CHAPTER 3 CPU 3.7 Standby Mode (Low-power Consumption) The standby mode consists of sleep mode and stop mode. Main run mode is switched to sleep mode or stop mode by setting the standby control register (STBC). Standby mode reduces the power consumption by stopping the operation of the CPU and peripheral functions. This section describes the relationship between standby mode and clock mode, and the operation of various sections during standby.
CHAPTER 3 CPU 3.7.1 Operating States in Standby Mode This section describes the operating states of the CPU and peripheral functions in standby mode. ■ Operating states during standby mode Table 3.
CHAPTER 3 CPU 3.7.2 Sleep Mode This section describes the operations of sleep mode. ■ Operation of sleep mode ● Entering sleep mode Sleep mode stops the CPU operating clock. The CPU stops while maintaining all register contents, RAM contents, and pin states at their values immediately prior to entering sleep mode. However, peripheral functions except the watchdog timer continue to operate. Writing "1" to the sleep bit in the standby control register (STBC: SLP) puts the CPU to sleep mode.
CHAPTER 3 CPU 3.7.3 Stop Mode This section describes the operations of stop mode. ■ Operation of stop mode ● Entering stop mode Stop mode stops the oscillation source. Almost all functions stop while maintaining all register and RAM contents at their value immediately before entering stop mode. Writing "1" to the stop bit in the standby control register (STBC: STP) puts the CPU to stop mode. At this time, external pin states are held if the pin state specification bit (STBC: SPL) is "0".
CHAPTER 3 CPU 3.7.4 Standby Control Register (STBC) The standby control register (STBC) controls the CPU to enter to sleep mode, stop mode, sets the pin states in stop mode, and initiates software reset. ■ Standby control register (STBC) Figure 3.7-1 Standby control register (STBC) Address 0008H Bit 7 STP W Bit 6 SLP W Bit 5 SPL R/W Bit 4 RST W Bit 3 — Bit 2 — RST 0 1 Bit 1 — Bit 0 — Software reset bi t Read Wri te Generates a reset signal for four instruction cycles.
CHAPTER 3 CPU Table 3.7-2 Standby control register (STBC) bits Bit 62 Function Bit 7 STP: Stop bit • • • • Sets the CPU entering stop mode. Writing "1" to this bit sets the CPU entering stop mode. Writing "0" to this bit has no effect on operation. Reading this bit always returns "0". Bit 6 SLP: Sleep bit • • • • Sets the CPU entering sleep mode. Writing "1" to this bit sets the CPU entering sleep mode. Writing "0" to this bit has no effect on operation. Reading this bit always returns "0".
CHAPTER 3 CPU 3.7.5 State Transition Diagram This section shows two state transition diagrams: one diagram for "with power-on reset" option products and the other for "without power-on reset" products. ■ State transition diagrams Figure 3.
CHAPTER 3 CPU ● Go to normal state (RUN) and reset Table 3.7-3 Go to main clock mode run state and reset Conditions/events required for transition State transition Products with power-on reset (Figure 3.7-2 ) Products without power-on reset (Figure 3.7-3 ) Go to normal state (RUN) after power-on [1] Main clock oscillation stabilization delay time completes (timebase timer output). [2] Wake-up from Reset input.
CHAPTER 3 CPU 3.7.6 Notes on Using Standby Mode The CPU does not go to standby mode if an interrupt request occurs from a peripheral function when a standby mode bit is set in the standby control register (STBC). Also, if an interrupt is used to wake up from a standby mode to the normal operating state, the operation after wake-up differs depending on whether or not the interrupt request is accepted.
CHAPTER 3 CPU ■ Oscillation stabilization delay time As the oscillator that provides the oscillation source is stopped during stop mode, a delay time is required for oscillation to stabilize after the oscillator restarts operation. In main clock mode, the main clock oscillation stabilization delay time is selected from one of two possible delay times defined by the timebase timer.
CHAPTER 3 CPU 3.8 Memory Access Mode In the MB89950/950A series, the only memory access mode is the single-chip mode. ■ Single-chip mode In single-chip mode, the device uses internal RAM and ROM only. Therefore, the CPU can access no areas other than the internal I/O area, RAM area, and ROM area (internal access). ■ Mode pin (MODA) Always set the mode pin, MODA, to VSS. At reset, reads the mode data and reset vector from internal ROM.
CHAPTER 3 CPU ■ Memory access mode selection operation Only the single-chip mode can be selected. Table 3.8-2 "Mode pin and mode data" lists the mode pin and mode data options. Table 3.8-2 Mode pins and mode data Memory access mode Mode pin (MODA) Mode data VSS 00H Prohibited settings Prohibited settings Single-chip mode Other modes Figure 3.8-2 "Memory access selection operation" shows the operation for memory access mode selection. Figure 3.
CHAPTER 4 I/O PORTS This chapter describes the functions and operation of the I/O ports. 4.1 "Overview of I/O Ports" 4.2 "Port 0" 4.3 "Port 1" 4.4 "Port 2" 4.5 "Port 3" 4.6 "Port 4" 4.
CHAPTER 4 I/O PORTS 4.1 Overview of I/O Ports The I/O ports consist of five ports (33 pins) including N-ch open-drain and CMOS general-purpose I/O ports (parallel I/O ports). The ports also serve as peripherals (I/O pins of peripheral functions). ■ I/O port functions The functions of the I/O ports are to output data from the CPU via the I/O pins and to fetch signals input to the I/O pins into the CPU. Input and output are performed via the port data registers (PDR).
CHAPTER 4 I/O PORTS Table 4.
CHAPTER 4 I/O PORTS 4.2 Port 0 Port 0 is N-ch open-drain I/O port that also serves as LCD segment driver outputs. Port 0 pins can be switched between LCD segment driver output and port operation by mask option. This section principally describes the port functions when operating as N-ch open-drain I/O port. The section describes the port structure and pins, the pin block diagram, and the port register for port 0.
CHAPTER 4 I/O PORTS ■ Block diagram of port 0 pins Figure 4.2-1 Block diagram of port 0 pins Mask option LCD segment driver output Segment driver output select register PDR (Port data register) Internal data bus Stop mode (SPL = 1) PDR read PDR read (for bit manipulation instructions) Output latch PDR write Pin N-ch Stop mode (SPL = 1) SPL: Pin state specification bit in the standby control register (STBC) ■ Port 0 register The port 0 register consists of PDR0.
CHAPTER 4 I/O PORTS 4.2.1 Port 0 Data Register (PDR0) This section describes the port 0 data register. ■ Port 0 data register functions ● Port 0 data register (PDR0) The PDR0 register holds the pin states. Therefore, a bit corresponding to a pin set as an output port can be read as the same state ("0" or "1") as the output latch, but when it is an input port, it cannot be read as the output latch state.
CHAPTER 4 I/O PORTS 4.2.2 Operation of Port 0 This section describes the operations of the port 0. ■ Operation of port 0 ● Operation as an output port • When the output latch value is "0", the output transistor turns "ON" and an "L" level is output from the pin. When the output latch value is "1", the transistor turns "OFF" and high impedance (Hi-Z) is output to the pin. • Writing data to the PDR0 register stores the data in the output latch and it will be output to the pin.
CHAPTER 4 I/O PORTS ● Operation in stop mode • The output transistors are forcibly turned "OFF" regardless of the PRD0 register value and the pins go to the high-impedance state if the pin state specification bit in the standby control register (STBC: SPL) is "1" when the device goes to stop mode. Moreover, to avoid leakage (from floating input pin), input must be driven by either "1" or "0" when SPL = "1". Table 4.2-4 "Port 0 pin state" lists the port 0 pin states Table 4.
CHAPTER 4 I/O PORTS 4.3 Port 1 Port 1 is N-ch open-drain I/O port that also serves as LCD segment driver outputs. Port 1 pins can be switched between LCD segment driver output and port operation by mask option. This section principally describes the port functions when operating as N-ch open-drain I/O port. The section describes the port structure and pins, the pin block diagram, and the port register for port 1.
CHAPTER 4 I/O PORTS ■ Block diagram of port 1 pins Figure 4.3-1 Block diagram of port 1 pins Mask option LCD segment driver output Segment driver output select register PDR (Port data register) Internal data bus Stop mode (SPL = 1) PDR read PDR read (for bit manipulation instructions) Output latch PDR write Pin N-ch Stop mode (SPL = 1) SPL: Pin state specification bit in the standby control register (STBC) ■ Port 1 register The port 1 register consists of PDR1.
CHAPTER 4 I/O PORTS 4.3.1 Port 1 Data Register (PDR1) This section describes the port 1 data register. ■ Port 1 data register functions ● Port 1 data register (PDR1) The PDR1 register holds the pin states. Therefore, a bit corresponding to a pin set as an output port can be read as the same state ("0" or "1") as the output latch, but when it is an input port, it cannot be read the output latch state.
CHAPTER 4 I/O PORTS 4.3.2 Operation of Port 1 This section describes the operations of the port 1. ■ Operation of port 1 ● Operation as an output port • When the output latch value is "0", the output transistor turns "ON" and an "L" level is output from the pin. When the output latch value is "1", the transistor turns "OFF" and high impedance (Hi-Z) is output from the pin. • Writing data to the PDR1 register stores the data in the output latch and it will be output to the pin.
CHAPTER 4 I/O PORTS ● Operation in stop mode • The output transistors are forcibly turned "OFF" regardless of the PRD0 register value and the pins go to the high-impedance state if the pin state specification bit in the standby control register (STBC: SPL) is "1" when the device goes to stop mode. Moreover, to avoid leakage (from floating input pin), input must be driven by either "1" or "0" when SPL = "1". Table 4.3-4 "Port 1 pin state" lists the port 1 pin states. Table 4.
CHAPTER 4 I/O PORTS 4.4 Port 2 Port 2 is N-ch open-drain I/O port that also serves as LCD segment driver outputs. Port 2 pins can be switched between LCD segment driver output and port operation by mask option. This section principally describes the port functions when operating as N-ch open-drain I/O port. The section describes the port structure and pins, the pin block diagram, and the port register for port 2.
CHAPTER 4 I/O PORTS ■ Block diagram of port 2 pins Figure 4.4-1 Block diagram of port 2 pins Mask option LCD segment driver output Segment driver output select register PDR (Port data register) Internal data bus Stop mode (SPL = 1) PDR read PDR read (for bit manipulation instructions) Output latch PDR write Pin N-ch Stop mode (SPL = 1) SPL: Pin state specification bit in the standby control register (STBC) ■ Port 2 register The port 2 register consists of PDR2.
CHAPTER 4 I/O PORTS 4.4.1 Port 2 Data Register (PDR2) This section describes the port 2 data register. ■ Port 2 data register functions ● Port 2 data register (PDR2) The PDR2 register holds the pin states. Therefore, a bit corresponding to a pin set as an output port can be read as the same state ("0" or "1") as the output latch, but when it is an input port, it cannot be read as the output latch state.
CHAPTER 4 I/O PORTS 4.4.2 Operation of Port 2 This section describes the operations of the port 2. ■ Operation of port 2 ● Operation as an output port • Writing data to the PDR2 register stores the data in the output latch. When the output latch value is "0", the output transistor turns "ON" and an "L" level is output from the pin. When the output latch value is "1", the transistor turns "OFF" and high impedance (Hi-Z) is output from the pin. • Reading the PDR2 register returns the output latch value.
CHAPTER 4 I/O PORTS 4.5 Port 3 Port 3 is N-ch open-drain I/O port. Two of them also serve as LCD bias input. Port 3 pins can be switched between LCD bias input and port operation. This section principally describes the port functions when operating as N-ch open-drain I/O port. The section describes the port structure and pins, the pin block diagram, and the port register for port 3.
CHAPTER 4 I/O PORTS ■ Block diagram of port 3 pins Figure 4.5-1 Block diagram of port 3 pins (P30 and P31) PDR (Port data register) Stop mode (SPL = 1) Internal data bus PDR read PDR read (for bit manipulation instructions) Output latch PDR write Pin N-ch Stop mode (SPL = 1) SPL: Pin state specification bit in the standby control register (STBC) Figure 4.
CHAPTER 4 I/O PORTS ■ Port 3 register The port 3 register consists of PDR3. Each bit in the register has a one-to-one relationship with a port 3 pin. Table 4.5-2 "Correspondence between pin and register for port 3" shows the correspondence between the pins and register for port 3. Table 4.
CHAPTER 4 I/O PORTS 4.5.1 Port 3 Data Register (PDR3) This section describes the port 3 data register. ■ Port 3 data register functions ● Port 3 data register (PDR3) The PDR3 register holds the pin states. Therefore, a bit corresponding to a pin set as an output port can be read as the same state ("0" or "1") as the output latch, but when it is an input port, it cannot be read as the output latch state.
CHAPTER 4 I/O PORTS 4.5.2 Operation of Port 3 This section describes the operations of the port 3. ■ Operation of port 3 ● Operation as an output port • Writing data to the PDR3 register stores the data in the output latch. When the output latch value is "0", the output transistor turns "ON" and an "L" level is output from the pin. When the output latch value is "1", the transistor turns "OFF" and high impedance (Hi-Z) is output from the pin. • Reading the PDR3 register returns the output latch value.
CHAPTER 4 I/O PORTS Table 4.
CHAPTER 4 I/O PORTS 4.6 Port 4 Port 4 is a general-purpose I/O port that also serves as the peripheral signal I/O pins. Individual pin can be switched between the port and resource function. This section principally describes the port functions when operating as a general-purpose I/O port. The section describes the port structure and pins, the pin block diagram, and the port registers for port 4.
CHAPTER 4 I/O PORTS ■ Block diagram of port 4 pins Figure 4.6-1 Block diagram of port 4 pins External interrupt enable To external interrupt To peripheral input PDR (Port data register) Stop mode (SPL = 1) Pull-up resistor Approx.
CHAPTER 4 I/O PORTS 4.6.1 Port 4 Registers (PDR4, DDR4) This section describes the port 4 registers. ■ Port 4 register functions ● Port 4 data register (PDR4) The PDR4 register holds the pin states. Therefore, when used as an output port that is not a peripheral output, it reads out as the same state ("0" or "1") as that of the output data latch; and when it is an input port, the output latch state cannot be read out.
CHAPTER 4 I/O PORTS Table 4.6-3 Port 4 PDR and DDR register function Register Data Read Write Pin state is the "L" level. Outputs an "L" level to the pin if the pin functions as an output port. (Sets "0" to the output latch and turns the output transistor "ON".) 1 Pin state is the "H" level. Sets the pin to the highimpedance state if the pin functions as an output port. (*) (Sets "1" to the output latch and turns the output transistor "OFF".
CHAPTER 4 I/O PORTS 4.6.2 Operation of Port 4 This section describes the operations of the port 4. ■ Operation of port 4 ● Operation as an output port • Setting the corresponding DDR4 register bit to "1" sets a pin as an output port. • When a pin is as an output port, the output transistor is enabled and the pin outputs the data stored in the output latch. • Writing data to the PDR4 register stores the data in the output latch and outputs the data to the pin.
CHAPTER 4 I/O PORTS ● Operation in stop mode • The pins go to the high-impedance state, if the pin state specification bit in the standby control register (STBC: SPL) is "1" when the device goes to stop mode. This is achieved by forcibly setting the output transistor "OFF" regardless of the DDR4 register value. Table 4.6-4 "Port 4 pin state" lists the port 4 pin states. Table 4.
CHAPTER 4 I/O PORTS 4.7 Program Example for I/O Ports This section gives an example program for using the I/O ports. ■ Program example for I/O ports ● Processing description • Port 0 and port 1 are used to illuminate all elements of seven segment LED (eight segments if the decimal point is included). • The P00 pin is used for the anode common pin of the LED and the P10 to P17 pins operate as the segment pins. Figure 4.
CHAPTER 5 TIMEBASE TIMER This chapter describes the functions and operation of the timebase timer. 5.1 "Overview of Timebase Timer" 5.2 "Block Diagram of Timebase Timer" 5.3 "Timebase Timer Control Register (TBTC)" 5.4 "Timebase Timer Interrupt" 5.5 "Operation of Timebase Timer" 5.6 "Notes on Using Timebase Timer" 5.
CHAPTER 5 TIMEBASE TIMER 5.1 Overview of Timebase Timer The timebase timer provides interval timer functions. Four different interval times can be selected. The timebase timer uses a 20-bit free-run counter which counts up in synchronous with the internal count clock (divide-by-two the main clock oscillation frequency).
CHAPTER 5 TIMEBASE TIMER ■ Clock supply function The clock supply function provides the timer output used for the main clock oscillation stabilization delay time (two values), and operation clock for some peripheral functions. Table 5.1-2 "Clocks supplied by timebase timer" lists the cycles of the clocks that the timebase timer supplies to various peripherals. Table 5.
CHAPTER 5 TIMEBASE TIMER 5.2 Block Diagram of Timebase Timer The timebase timer consists of the following four blocks: • Timebase timer counter • Counter clear circuit • Interval timer selector • Timebase timer control register (TBTC) ■ Block diagram of timebase timer Figure 5.
CHAPTER 5 TIMEBASE TIMER ● TBTC register The TBTC register is used to select the interval timer bit, clear the counter, control interrupts, and check the state of the timebase timer.
CHAPTER 5 TIMEBASE TIMER 5.3 Timebase Timer Control Register (TBTC) The timebase timer control register (TBTC) is used to select the interval times bit, clear the counter, control interrupts, and check the state of the timebase timer. ■ Timebase timer control register (TBTC) Figure 5.
CHAPTER 5 TIMEBASE TIMER Table 5.3-1 Timebase timer control register (TBTC) bits Bit Function Bit 7 Bit 6 Bit 5 Unused bits • The read value is indeterminate. • Writing to these bits has no effect on the operation. Bit 4 TBIF: Overflow interrupt request flag bit • This bit is set to "1" when counter overflow occurs on the specified bit of the timebase timer counter. • An interrupt request is generated when both this bit and the interrupt request enable bit (TBIE) are "1".
CHAPTER 5 TIMEBASE TIMER 5.4 Timebase Timer Interrupt The timebase timer can generate an interrupt request when an overflow occurs on the specified bit of the timebase counter (for the interval timer function). ■ Interrupts for interval timer function The counter counts up on the internal count clock. When an overflow occurs on the selected interval timer bit, the overflow interrupt request flag bit (TBTC: TBIF) is set to "1".
CHAPTER 5 TIMEBASE TIMER 5.5 Operation of Timebase Timer The timebase timer has the interval timer function and the clock supply function for some peripherals. ■ Operation of interval timer function (timebase timer) Figure 5.5-1 "Interval timer function settings" shows the settings required to operate the interval timer function. Figure 5.
CHAPTER 5 TIMEBASE TIMER ■ Operation of timebase timer The state of following operations are shown in Figure 5.5-2 "Operation of timebase timer". • A power-on reset occurs. • Goes to sleep mode during operation of the interval timer function in the main clock mode. • Goes to stop mode. • A counter clear request occurs. The timebase timer is cleared by going to stop mode, and its operation is stopped. The timebase timer counts the oscillation stabilization delay time after wake-up from stop mode. Figure 5.
CHAPTER 5 TIMEBASE TIMER 5.6 Notes on Using Timebase Timer This section lists points to note when using the timebase timer. ■ Notes on using timebase timer ● Notes on setting bits by program The system cannot recover from interrupt processing if the overflow interrupt request flag bit (TBTC: TBIF) is "1" and the interrupt request enable bit is enabled (TBTC: TBIE = "1"). Always clear the TBIF bit.
CHAPTER 5 TIMEBASE TIMER 5.7 Program Example for Timebase Timer This section gives a program example for the timebase timer. ■ Program example for timebase timer ● Processing description • Generates repeated interval timer interrupts at 219/FCH (FCH: Main clock oscillation frequency) intervals. At this time, the interval time is approximately 104.86 ms (at 5 MHz operation).
CHAPTER 6 WATCHDOG TIMER This chapter describes the functions and operation of the watchdog timer. 6.1 "Overview of Watchdog Timer" 6.2 "Block Diagram of Watchdog Timer" 6.3 "Watchdog Timer Control Register (WDTC)" 6.4 "Operation of Watchdog Timer" 6.5 "Notes on Using Watchdog Timer" 6.
CHAPTER 6 WATCHDOG TIMER 6.1 Overview of Watchdog Timer The watchdog timer is a 2-bit counter that uses, as its count clock source, the timebase timer derived from the main clock. The watchdog timer resets the CPU if not cleared within a fixed time after activation. ■ Watchdog timer function The watchdog timer is a counter provided to guard against program runaway. Once activated, the counter must be repeatedly cleared within a fixed time interval.
CHAPTER 6 WATCHDOG TIMER 6.2 Block Diagram of Watchdog Timer The watchdog timer consists of the following four blocks: • Watchdog timer counter • Reset controller • Counter clear controller • Watchdog timer control register (WDTC) ■ Block diagram of watchdog timer Figure 6.
CHAPTER 6 WATCHDOG TIMER ● WDTC register The WDTC register is used to select the count clock, and to activate or clear the watchdog timer counter. As the register is write-only, the bit manipulation instructions cannot be used.
CHAPTER 6 WATCHDOG TIMER 6.3 Watchdog Timer Control Register (WDTC) The watchdog timer control register (WDTC) is used to activate or clear the watchdog timer. ■ Watchdog timer control register (WDTC) Figure 6.
CHAPTER 6 WATCHDOG TIMER 6.4 Operation of Watchdog Timer The watchdog timer generates a watchdog reset when the watchdog timer counter overflows. ■ Operation of watchdog timer ● Activating watchdog timer The watchdog timer is activated by writing "0101B" to the watchdog control bits in the watchdog control register (WDTC: WTE3 to WTE0) for the first time after a reset. Once activated, the watchdog timer cannot be stopped other than by a reset.
CHAPTER 6 WATCHDOG TIMER Figure 6.4-1 Watchdog timer clear and interval time Minimum time 419.43 ms Count clock output of the timebase timer Watchdog clear Overflow 1-bit watchdog counter Watchdog reset Maximum time 838.
CHAPTER 6 WATCHDOG TIMER 6.5 Notes on Using Watchdog Timer This section lists points to note when using the watchdog timer. ■ Notes on using watchdog timer ● Stopping watchdog timer Once activated, the watchdog timer cannot stop until a reset generates. ● Clearing watchdog timer Clearing the counter being used as a count clock of the watchdog timer (timebase timer or watch prescaler) also simultaneously clears the watchdog timer counter.
CHAPTER 6 WATCHDOG TIMER 6.6 Program Example for Watchdog Timer This section gives a program example for the watchdog timer. ■ Program example for watchdog timer ● Processing description Activates the watchdog timer immediately after the program. Clears the watchdog timer in each loop of the main program. The processing time for the main loop, including interrupt processing, must be less than the minimum interval time of the watchdog timer (approximately 419.43 ms at 5 MHz operation).
CHAPTER 6 WATCHDOG TIMER 120
CHAPTER 7 8-BIT PWM TIMER This chapter describes the functions and operation of the 8-bit PWM timer. 7.1 "Overview of 8-bit PWM Timer" 7.2 "Block Diagram of 8-bit PWM Timer" 7.3 "Structure of 8-bit PWM Timer" 7.4 "8-bit PWM Timer Interrupts" 7.5 "Operation of Interval Timer Function" 7.6 "Operation of PWM Timer Function" 7.7 "States in Each Mode during 8-bit PWM Timer Operation" 7.8 "Notes on Using 8-bit PWM Timer" 7.
CHAPTER 7 8-BIT PWM TIMER 7.1 Overview of 8-bit PWM Timer The 8-bit PWM timer can be selected to function as either an interval timer or PWM timer with 8-bit resolution. The interval timer function counts up in synchronous with PWC output clock or one of three internal count clocks. Therefore, an 8-bit interval timer time can be set and the output can be used to generate variable frequency square waves.
CHAPTER 7 8-BIT PWM TIMER ■ PWM timer function The PWM timer function has 8-bit resolution and can control the "H" and "L" width of one cycle. • As the resolution is 1/256, pulses can be output with duty ratio of between 0 and 99.6%. • The cycle of the PWM wave can be selected from four types. • The PWM timer can be used as a D/A converter by connecting the output to a low-pass filter. Table 7.
CHAPTER 7 8-BIT PWM TIMER 7.2 Block Diagram of 8-bit PWM Timer The 8-bit PWM timer consists of the following six blocks: • Count clock selector • 8-bit counter • Comparator circuit • PWM generator and output controller • PWM compare register (COMR) • PWM control register (CNTR) ■ Block diagram of 8-bit PWM timer Figure 7.
CHAPTER 7 8-BIT PWM TIMER ● Count clock selector Selects a count-up clock for the 8-bit counter from the three internal count clocks and the PWC timer output cycle. ● 8-bit counter The 8-bit counter counts up on the count clock selected by the count clock selector. ● Comparator circuit The comparator circuit has a latch to hold the COMR register value. The circuit latches the COMR register value when the 8-bit counter value is "00H".
CHAPTER 7 8-BIT PWM TIMER 7.3 Structure of 8-bit PWM Timer This section describes the pin, pin block diagram, register source, and interrupts of the 8-bit PWM timer. ■ 8-bit PWM timer pin The 8-bit PWM timer uses the P41/PWM pin. This pin can function as a CMOS general-purpose I/O port (P41), or as the interval timer or PWM timer output (PWM). PWM: When the interval timer function is selected, the square waves are output to this pin. When the PWM timer function is selected, the pin outputs the PWM wave.
CHAPTER 7 8-BIT PWM TIMER ■ 8-bit PWM timer registers Figure 7.
CHAPTER 7 8-BIT PWM TIMER 7.3.1 PWM Control Register (CNTR) The PWM control register (CNTR) is used to select the operating mode of the 8-bit PWM timer (interval timer operation or PWM timer operation), enable or disable operation, select the count clock, control interrupts, and check the state of the 8-bit PWM timer. ■ PWM control register (CNTR) Figure 7.
CHAPTER 7 8-BIT PWM TIMER Table 7.3-1 PWM control register (CNTR) bits Bit Function Bit 7 P/T: Operating mode selection bit • This bit switches between the interval timer function (P/T = "0") and PWM timer function (P/T = "1"). Note: Write to this bit when the counter operation is stopped (TPE = "0"), interrupts are disabled (TIE = "0"), and the interrupt request flag bit is cleared (TIR = "0"). Bit 6 Unused bit • The read value is indeterminate. • Writing to this bit has no effect on the operation.
CHAPTER 7 8-BIT PWM TIMER 7.3.2 PWM Compare Register (COMR) The PWM compare register (COMR) sets the interval time for the interval timer function. The register value sets the "H" width of the pulse for the PWM timer function. ■ PWM compare register (COMR) Figure 7.3-4 "PWM compare register (COMR)" shows the bit structure of the PWM compare register. As the register is write-only, bit manipulation instructions cannot be used. Figure 7.
CHAPTER 7 8-BIT PWM TIMER 7.4 8-bit PWM Timer Interrupts The 8-bit PWM timer can generate an interrupt request when a match is detected between the counter value and PWM compare register value for the interval timer function. Interrupt requests are not generated for the PWM timer function. 8-bit PWM timer generates the IRQ2 as an interrupt request. ■ Interrupts for interval timer function The counter starts to count up from "00H" on the selected count clock.
CHAPTER 7 8-BIT PWM TIMER 7.5 Operation of Interval Timer Function This section describes the operation of the interval timer function of the 8-bit PWM timer. ■ Operation of interval timer function Figure 7.5-1 "Interval timer function settings" shows the settings required to operate as an interval timer function. Figure 7.5-1 Interval timer function settings Bit 7 CNTR Bit 6 P/T Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P1 P0 TPE TIR OE TIE 0 1 COMR Sets interval time (compare value).
CHAPTER 7 8-BIT PWM TIMER Note: Do not change the count clock cycle (CNTR: P1, P0) during operation of the interval timer function (CNTR: TPE = "1"). References: • Setting the COMR register value to "00H" causes the PWM pin output to be inverted with the cycle of the selected count clock. • When the counter is stopped (CNTR: TPE = "0") while the interval timer function is selected, the PWM pin outputs an "L" level.
CHAPTER 7 8-BIT PWM TIMER 7.6 Operation of PWM Timer Function This section describes the operation of the PWM timer function of the 8-bit PWM timer. ■ Operation of PWM timer function Figure 7.6-1 "PWM timer function settings" shows the settings required to operate as the PWM timer function. Figure 7.6-1 PWM timer function settings CNTR Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P/TX — P1 P0 TPE TIR OE TIE 1 X 1 X 1 COMR Sets "H" width of pulse (compare value).
CHAPTER 7 8-BIT PWM TIMER 7.7 States in Each Mode during 8-bit PWM Timer Operation This section describes the operation of the 8-bit PWM timer when the device goes to sleep or stop mode, or an operation halt request occurs during operation. ■ Operation during standby mode or operation halt Figure 7.7-1 "Counter operation during standby mode or operation halt (for interval timer function)" and Figure 7.
CHAPTER 7 8-BIT PWM TIMER ● For PWM timer function Figure 7.7-2 Operation during standby mode or operation halt (for PWM timer function) 00H 00H 00H 00H 00H PWM pin (PWM waveform) * Maintains the level prior to halting. TPE bit Operation halts Operation restarts Sleep mode SLP bit (STBC register) Wake-up from sleep mode by an interrupt other than IRQ2 (IRQ2 is not generated). Stop mode STP bit (STBC register) Oscillation stabilization delay time Wake-up from stop mode by an external interrupt.
CHAPTER 7 8-BIT PWM TIMER 7.8 Notes on Using 8-bit PWM Timer This section lists points to note when using the 8-bit PWM timer. ■ Notes on using 8-bit PWM timer ● Error Activating the counter by program is not synchronized with the start of counting-up using the selected count clock. Therefore, the time from activating the counter until a match with the PWM compare register (COMR) is detected may be shorter than the theoretical time by a maximum of one cycle count clock. Figure 7.
CHAPTER 7 8-BIT PWM TIMER 7.9 Program Example for 8-bit PWM Timer This section gives program examples for the 8-bit PWM timer. ■ Program example for interval timer function ● Processing description • Generates repeated interval timer interrupts at 2.5 ms intervals. • Outputs a square wave to the PWM pin that inverts after each interval time.
CHAPTER 7 8-BIT PWM TIMER ● Coding example CNTR COMR EQU EQU 0012H 0013H ; Address of the PWM control register ; Address of the PWM compare register TPE TIR EQU EQU CNTR:3 CNTR:2 ; Define the counter operation enable bit. ; Define the interrupt request flag bit. ILR1 EQU 007CH ; Address of the interrupt level setting register 3 INT_V DSEG ABS ; [DATA SEGMENT] ORG 0FFF6H IRQ2 DW WARI ; Set interrupt vector.
CHAPTER 7 8-BIT PWM TIMER ■ Program example for PWM timer function ● Processing description • Generates a PWM wave with a duty ratio of 50%. Then, changes the duty ratio to 25%. • Does not generate interrupts. • For a 5 MHz main clock oscillation frequency (FCH), selecting the interval 16 tinst count clock gives a PWM wave cycle of 16 x 4/5 MHz x 256 = 3.277 ms.
CHAPTER 8 PULSE WIDTH COUNT TIMER (PWC) This chapter describes the functions and operation of the pulse width count timer (PWC). 8.1 "Overview of Pulse Width Count Timer" 8.2 "Block Diagram of Pulse Width Count Timer" 8.3 "Structure of Pulse Width Count Timer 8.4 "Pulse Width Count Timer Interrupts" 8.5 "Operation of Interval Timer Function" 8.6 "Operation of Pulse Width Measurement Function" 8.7 "Operation of Noise Filter Circuit" 8.8 "States in Each Mode during Pulse Width Count Timer Operation" 8.
CHAPTER 8 PULSE WIDTH COUNT TIMER (PWC) 8.1 Overview of Pulse Width Count Timer The pulse width count timer (PWC) can be selected to function as either an interval timer or the pulse width measurement. The interval timer function counts down in synchronous with one of three internal count clocks. The pulse width measurement function measures the width of pulses input to an external pin. Therefore, the PWC can be used as an input capture by continuously measuring the pulse width of an external input.
CHAPTER 8 PULSE WIDTH COUNT TIMER (PWC) ■ Pulse width measurement function The pulse width measurement function can measure the "H" width, "L" width, and one-cycle width of pulses input from an external pin (PWC pin). • The PWC can perform continuous pulse width measurement. • The measurement speed (internal count clock) can be selected from three different speeds. • The width of long input pulses can be measured using an interrupt processing routine. Table 8.
CHAPTER 8 PULSE WIDTH COUNT TIMER (PWC) 8.2 Block Diagram of Pulse Width Count Timer The pulse width count timer consists of the following nine blocks: • Count clock selector • 8-bit down counter • Input pulse edge detector • Noise filter circuit • Noise filter clock selector • PWC reload buffer register (RLBR) • PWC pulse width control register 1 (PCR1) • PWC pulse width control register 2 (PCR2) • Noise filter control register (NCCR) ■ Block diagram of pulse width count timer Figure 8.
CHAPTER 8 PULSE WIDTH COUNT TIMER (PWC) ● Count clock selector Selects a count clock for the 8-bit down counter from the three available internal count clocks. ● 8-bit down counter The 8-bit down counter starts to count from the value set in the PWC reload buffer register (RLBR) when operating as an interval timer, and from FFH when performing pulse width measurement. When an underflow (01H --> 00H) occurs, the counter inverts the timer output bit (PCR2: TO).
CHAPTER 8 PULSE WIDTH COUNT TIMER (PWC) 8.3 Structure of Pulse Width Count Timer This section describes the pins, pin block diagram, registers, and interrupt source of the pulse width count timer. ■ Pulse width count timer pin The pulse width count timer uses the P42/PWC/INT1 pin. This pin can function either as CMOS generalpurpose I/O port (P42) or external interrupt (INT1), or as the measured pulse input (PWC). PWC: The pulse width measurement function measures the pulse widths input to this pin.
CHAPTER 8 PULSE WIDTH COUNT TIMER (PWC) ■ Pulse width count timer registers Figure 8.
CHAPTER 8 PULSE WIDTH COUNT TIMER (PWC) 8.3.1 PWC Pulse Width Control Register 1 (PCR1) The PWC pulse width control register 1 (PCR1) is used to enable or disable functions, control interrupts and check the state of the pulse width count timer. ■ PWC pulse width control register 1 (PCR1) Figure 8.
CHAPTER 8 PULSE WIDTH COUNT TIMER (PWC) Table 8.3-1 PWC pulse width control register 1 (PCR1) bits Bit Function Bit 7 EN: Counter operation enable bit • For the interval timer function: Writing "1" to this bit starts the counter to count down from the PWC reload buffer register (RLBR) value. Writing "0" to this bit stops the counter operation. • For the pulse width measurement function: Writing "1" to this bit enables measurement.
CHAPTER 8 PULSE WIDTH COUNT TIMER (PWC) 8.3.2 PWC Pulse Width Control Register 2 (PCR2) The PWC pulse width control register 2 (PCR2) is used to select the operating mode (pulse width measurement or interval timer operation, etc.), select the count clock, set the measured pulse (measurement edges), and check the timer output state of the pulse width count timer. ■ PWC pulse width control register 2 (PCR2) Figure 8.
CHAPTER 8 PULSE WIDTH COUNT TIMER (PWC) Table 8.3-2 PWC pulse width control register 2 (PCR2) bits Bit Function Bit 7 FC: Operating mode selection bit • This bit switches between the interval timer function (FC = "0") and pulse width measurement function (FC = "1"). Note: When using the pulse width measurement function (FC = "1"), set the P42/PWC/INT1 pin as an input port.
CHAPTER 8 PULSE WIDTH COUNT TIMER (PWC) 8.3.3 PWC Reload Buffer Register (RLBR) The PWC reload buffer register (RLBR) functions as a reload register for the interval timer function and as a measurement value storage register for the pulse width measurement function. ■ PWC reload buffer register (RLBR) Figure 8.3-5 "PWC reload buffer register (RLBR)" shows the bit structure of the PWC reload buffer register. Figure 8.
CHAPTER 8 PULSE WIDTH COUNT TIMER (PWC) ● For pulse width measurement function The register is used to store the pulse width measurement value. The counter value is transferred to this register when pulse width measurement completes on detection of the edge specified for measurement completion. At this time, the buffer full flag bit (PCR1: BF) and the measurement completion interrupt request flag bit (PCR1: IR) are set to "1". Reading this register clears the BF bit to "0".
CHAPTER 8 PULSE WIDTH COUNT TIMER (PWC) 8.3.4 PWC Noise Filter Control Register (NCCR) The PWC noise filter control register is used to select the sampling clock for the noise filter circuit. There are three type of selectable sampling clock from the timebase timer. ■ PWC noise filter control register (NCCR) Figure 8.
CHAPTER 8 PULSE WIDTH COUNT TIMER (PWC) 8.4 Pulse Width Count Timer Interrupts The pulse width count timer has the following two interrupts: • Counter value underflow (01H --> 00H) for the interval timer function • Measurement completion and buffer full for the pulse width measurement function ■ Interrupt for the interval timer function The counter counts down from the set value on the selected internal count clock.
CHAPTER 8 PULSE WIDTH COUNT TIMER (PWC) 8.5 Operation of Interval Timer Function This section describes the operation of the interval timer function of the pulse width count timer. ■ Operation of interval timer function The interval timer function can operate as a continuous timer (reload timer mode), or as a timer that operates for one timer-cycle and then stops (one-shot mode). ● Reload timer mode Figure 8.
CHAPTER 8 PULSE WIDTH COUNT TIMER (PWC) Figure 8.5-2 Operation in reload timer mode Counter value FFH Reload 80H 00H Time Timer cycle RLBR value (FFH) RLBR value is modified* (FFH 80H) Cleared by the program UF bit EN bit TOE bit For an initial value of “0” (TO bit) *: If the PWC reload buffer register (RLBR) value is modified during operation, the new value will be effective in next cycle.
CHAPTER 8 PULSE WIDTH COUNT TIMER (PWC) Figure 8.
CHAPTER 8 PULSE WIDTH COUNT TIMER (PWC) 8.6 Operation of Pulse Width Measurement Function This section describes the operations of the pulse width measurement function of the pulse width count timer. ■ Operation of pulse width measurement function Figure 8.6-1 "Pulse width measurement function settings" shows the settings required to operate as the pulse width measurement function. Figure 8.
CHAPTER 8 PULSE WIDTH COUNT TIMER (PWC) Figure 8.
CHAPTER 8 PULSE WIDTH COUNT TIMER (PWC) Figure 8.6-3 Measuring long pulse width (falling edge to falling edge) One cycle Input pulse (Input waveform to the PWC pin) EN bit Counter value FFH Software counter value 0 1 2 3 Set "0" UF bit Cleared by the program Cleared by the program IR bit BF bit Data transferred from down counter to RLBR RLBR read Figure 8.
CHAPTER 8 PULSE WIDTH COUNT TIMER (PWC) 8.7 Operation of Noise Filter Circuit This section describes the operations of noise filter circuit function when the pulse width measurement function is selected. ■ Operation of noise filter circuit function Figure 8.7-1 "Noise filter circuit function settings" shows the settings required to operate as the noise filter circuit function. Figure 8.
CHAPTER 8 PULSE WIDTH COUNT TIMER (PWC) 8.8 States in Each Mode during Pulse Width Count Timer Operation This section describes the operation of the pulse width count timer when the device goes to sleep or stop mode, or an operation halt request occurs during operation. ■ Operation during standby mode or operation halt Figure 8.
CHAPTER 8 PULSE WIDTH COUNT TIMER (PWC) 8.9 Notes on Using Pulse Width Count Timer This section lists points to note when using the pulse width count timer. ■ Notes on using pulse width count timer ● Error When using the interval timer function, activating the counter by program is not synchronized with the start of counting-down using the selected internal count clock.
CHAPTER 8 PULSE WIDTH COUNT TIMER (PWC) 8.10 Program Example for Timer Function of Pulse Width Count Timer This section gives two program examples for the timer function of the pulse width count timer. ■ Program example 1 for interval timer function (reload timer mode) ● Processing description • Generates repeated interval timer interrupts at 3 ms intervals (reload timer mode). • The TO bit will be inverted after each interval time cycle. The initial value of TO bit is "0" level.
CHAPTER 8 PULSE WIDTH COUNT TIMER (PWC) ● Coding example PCR1 PCR2 RLBR EQU EQU EQU 0014H 0015H 0016H ; Address of the PWC pulse width control register 1 ; Address of the PWC pulse width control register 2 ; Address of the PWC reload buffer register EN IE UF EQU EQU EQU PCR1:7 PCR1:5 PCR1:2 BF EQU PCR1:0 ; Define the counter operation enable bit. ; Define the interrupt request enable bit. ; Define the underflow (01H 00H) interrupt request flag bit. ; Define the buffer full flag.
CHAPTER 8 PULSE WIDTH COUNT TIMER (PWC) ■ Program example 2 for interval timer function (one-shot timer mode) ● Processing description • Generates a single 1.5 ms interval timer interrupt (one-shot timer mode). • The TO bit is initialized to "1" and inverted after the interval time. • The following shows the RLBR register value that results in an interval time of approximately 3 ms for a 5 MHz main clock oscillation frequency. The count clock is 32 tinst (tinst: Instruction cycle).
CHAPTER 8 PULSE WIDTH COUNT TIMER (PWC) ● Coding example PCR1 PCR2 RLBR EQU EQU EQU 0014H 0015H 0016H ; Address of the PWC pulse width control register 1 ; Address of the PWC pulse width control register 2 ; Address of the PWC reload buffer register EN IE UF EQU EQU EQU PCR1:7 PCR1:5 PCR1:2 BF EQU PCR1:0 ; Define the counter operation enable bit. ; Define the interrupt request enable bit. ; Define the underflow (01H 00H) interrupt request flag bit.
CHAPTER 9 8-BIT SERIAL I/O This chapter describes the functions and operation of the 8-bit serial I/O. 9.1 "Overview of 8-bit Serial I/O" 9.2 "Block Diagram of 8-bit Serial I/O" 9.3 "Structure of 8-bit Serial I/O" 9.4 "8-bit Serial I/O Interrupts" 9.5 "Operation of Serial Output" 9.6 "Operation of Serial Input" 9.7 "States in Each Mode during 8-bit Serial I/O Operation" 9.8 "Notes on Using 8-bit Serial I/O" 9.9 "Connection Example for 8-bit Serial I/O" 9.
CHAPTER 9 8-BIT SERIAL I/O 9.1 Overview of 8-bit Serial I/O The 8-bit serial I/O function is the serial transfer of 8-bit data, synchronized with the shift clock. The shift clock can be selected from one external and three internal clocks. The data shift direction can be selected as either LSB first or MSB first. ■ Serial I/O function The 8-bit serial I/O function is the serial input and output of 8-bit data, synchronized with the shift clock.
CHAPTER 9 8-BIT SERIAL I/O 9.2 Block Diagram of 8-bit Serial I/O Each channel of the 8-bit serial I/O consists of the following four blocks: • Shift clock controller • Shift clock counter • Serial data register (SDR) • Serial mode register (SMR) ■ Block diagram of 8-bit serial I/O Figure 9.
CHAPTER 9 8-BIT SERIAL I/O ● Shift clock control circuit Selects the shift clock from one external and three internal clocks. If an internal shift clock is selected, the shift clock can be output to the SCK pin. If external shift clock is selected, the clock input from the SCK pin is used as the shift clock. The SDR register shifts in synchronous with the shift clock and the shifted-out value is output to the SO pin. Similarly, the serial input is obtained by shifting the SI pin input to the SDR register.
CHAPTER 9 8-BIT SERIAL I/O 9.3 Structure of 8-bit Serial I/O This section describes the pins, pin block diagram, registers, and interrupt source of 8bit serial I/O. ■ 8-bit serial I/O pins 8-bit serial I/O uses the P43/SI, P44/SO, and P45/SCK. The pins are also used as UART I/O pins. To use the pins as serial I/O pins, set the UART/SIO selection bit RSEL of UART serial mode control register 2 (SMC2: RSEL = "1").
CHAPTER 9 8-BIT SERIAL I/O ■ Block diagram of 8-bit serial I/O pins Figure 9.3-1 Block diagram of 8-bit serial I/O pin For P43/SI and P45/SCK To SIO input PDR (Port data register) Stop mode (SPL = 1) Pull-up resistor Approx.
CHAPTER 9 8-BIT SERIAL I/O ■ 8-bit serial I/O interrupt source IRQ5: 8-bit serial I/O generates an interrupt request (IRQ5) if interrupt request output is enabled (SMR: SIOE = "1") when the I/O function completes input or output of 8-bit serial data.
CHAPTER 9 8-BIT SERIAL I/O 9.3.1 Serial Mode Register (SMR) The serial mode register (SMR) is used to enable or disable operation, select the shift clock, set the transfer direction, control interrupts, and check the state of 8-bit serial I/O. ■ Serial mode register (SMR) Figure 9.
CHAPTER 9 8-BIT SERIAL I/O Table 9.3-1 Serial mode register (SMR) bits Bit Bit 7 SIOF: Interrupt request flag bit Function • • This bit is set to "1" when the serial output operation has transmitted 8 serial data bits or the serial input operation has received 8 serial data bits. An interrupt request is generated when both this bit and the interrupt request enable bit (SIOE) are "1". Writing "0" clears this bit. Writing "1" has no effect and does not change the bit value.
CHAPTER 9 8-BIT SERIAL I/O Table 9.3-1 Serial mode register (SMR) bits Bit Bit 0 SST: Serial I/O transfer start bit Function • • • • • 178 This bit controls serial I/O transfer start and transfer enable. This bit can also be used to determine whether transfer has completed. Writing "1" to this bit when an internal shift clock is selected (CKS1, CKS0 = other than "11B") clears the shift clock counter and starts data transfer.
CHAPTER 9 8-BIT SERIAL I/O 9.3.2 Serial Data Register (SDR) The serial data register (SDR) stores the transfer data for 8-bit serial I/O. The register can function as the transmit data register for serial output operation or as the receive data register for serial input operation. ■ Serial data register (SDR) Figure 9.3-4 "Serial data register (SDR)" shows the bit structure of the serial data register. Figure 9.
CHAPTER 9 8-BIT SERIAL I/O 9.4 8-bit Serial I/O Interrupts The 8-bit serial I/O can generate interrupt requests after completion of the serial input and output of the 8-bit data. ■ Interrupt for serial output operation The 8-bit serial I/O performs the serial input operation and serial output operation at the same time. When the serial transfer starts, the data in the serial data register (SDR) is input and output one bit at a time, synchronized with the cycle of the selected shift clock.
CHAPTER 9 8-BIT SERIAL I/O 9.5 Operation of Serial Output The 8-bit serial I/O can perform serial output of 8-bit data synchronized with a shift clock. ■ Serial output operation Serial output can operate using an internal or external shift clock. When serial output operation is enabled, the contents of the SDR register are output to the serial data output pin (SO). Serial input is performed at the same time. ● Internal shift clock Figure 9.
CHAPTER 9 8-BIT SERIAL I/O When the device being communicated with has completed the serial input operation (on the rising edge), hold the external shift clock at the "H" level while waiting for next output data (idle state). Figure 9.5-3 "8-bit serial output operation" shows the 8-bit serial output operation. Figure 9.
CHAPTER 9 8-BIT SERIAL I/O 9.6 Operation of Serial Input The 8-bit serial I/O can perform serial input of 8-bit data synchronized with a shift clock. ■ Serial input operation Serial input can operate using an internal or external shift clock. When serial in operation is enabled, input from the serial data input pin (SI) is stored in SDR register. Serial output is performed at the same time. ● Internal shift clock Figure 9.
CHAPTER 9 8-BIT SERIAL I/O During this time, hold the external shift clock at the "H" level while waiting for the next data (idle state). Figure 9.6-3 "8-bit serial input operation" shows the 8-bit serial input operation. Figure 9.6-3 8-bit serial input operation For MSB first SDR Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 #7 #6 #5 #4 #3 #2 Serial input data Bit 1 Bit 0 #1 SI pin #0 #7 #6 #5 #4 #3 #2 #1 #0 0 1 2 3 4 5 6 7 Shift clock Cleared by the program.
CHAPTER 9 8-BIT SERIAL I/O 9.7 States in Each Mode during 8-bit Serial I/O Operation This section describes the operation of the 8-bit serial I/O when the device goes to sleep or stop mode, or an operation halt request occurs during transfer. ■ Using internal shift clock ● Operation in sleep mode In sleep mode, serial I/O operation does not halt and transfer continues, as shown in Figure 9.7-1 "Operation in sleep mode (internal shift clock)". Figure 9.
CHAPTER 9 8-BIT SERIAL I/O Figure 9.7-3 Operation during halt (internal shift clock) SCK output SST bit Operation halts. Operation reactivates. Reset SDR register SIOF bit SO pin output #0 #1 #2 #3 #4 #5 #0 #1 ■ Using external shift clock ● Operation in sleep mode In sleep mode, serial I/O operation does not halt and transfer continues, as shown in Figure 9.7-4 "Operation in sleep mode (external shift clock)". Figure 9.
CHAPTER 9 8-BIT SERIAL I/O Figure 9.7-5 Operation in stop mode (external shift clock) Clock for next data SCK input #6 Stop request SST bit #7 SIOF bit Oscillation stabilization delay time Cleared by the program. Interrupt request #0 SO pin output #1 #2 #3 #4 #5 #6 #7 Stop modeTransfer error occurs STP bit (STBC register) Wake-up from stop mode by an external interrupt.
CHAPTER 9 8-BIT SERIAL I/O 9.8 Notes on Using 8-bit Serial I/O This section lists points to note using when the 8-bit serial I/O. ■ Notes on using 8-bit serial I/O ● Error on starting serial transfer Activating the serial transfer by software (SMR: SST = "1") is not synchronized with the falling edge (output) or rising edge (input) of the shift clock, there is a delay of up to one cycle of the selected shift clock before the first serial data I/O occurs.
CHAPTER 9 8-BIT SERIAL I/O 9.9 Connection Example for 8-bit Serial I/O This section shows an example of connecting together two MB89950/950A series 8-bit serial I/O and performing bi-directional serial I/O. ■ Bi-directional serial I/O performing Figure 9.9-1 Connection example for 8-bit serial I/O (interface between two MB89950/950A) SO SIO-A SI SCK SIO-B SO SI Output Input Internal shift clock SCK External shift clock Figure 9.
CHAPTER 9 8-BIT SERIAL I/O 9.10 Program Example for 8-bit Serial I/O This section gives program example for 8-bit serial I/O. ■ Program example for serial output ● Processing description • Outputs 8-bit serial data (55H) from the SO pin of serial I/O, then generates an interrupt when transfer is completed. • The interrupt processing routine resets the transfer data and continues output. • Operates as an internal shift clock and outputs the shift clock from the SCK pin.
CHAPTER 9 8-BIT SERIAL I/O ● Coding example SMR SDR EQU EQU 001CH 001DH ; Serial mode register ; Serial data register SIOF SST EQU EQU SMR:7 SMR:0 ; Define the interrupt request flag bit. ; Define the serial I/O transfer start bit. ILR2 EQU 007DH ; Address of the interrupt level setting register 2 INT_V DSEG ABS ; [DATA SEGMENT] ORG 0FFF0H IRQ5 DW WARI ; Set interrupt vector.
CHAPTER 9 8-BIT SERIAL I/O ■ Program example for serial input ● Processing description • Inputs 8-bit serial data from the SI pin of serial I/O, then generates an interrupt when transfer is completed. • The interrupt processing routine reads the transferred data and continues transfer. • Serial I/O uses the external shift clock. The shift clock is input from the SCK pin.
CHAPTER 10 UART This chapter describes the functions and operation of the UART. 10.1 "Overview of UART" 10.2 "Structure of UART" 10.3 "UART Pins" 10.4 "UART Registers" 10.5 "UART Interrupts" 10.6 "Operation of UART" 10.7 "Operation of Mode 0, 1, 3" 10.
CHAPTER 10 UART 10.1 Overview of UART The UART is a general-purpose data communication interface. The UART supports both synchronous clock and asynchronous clock mode and transmits variable-length serial data. The transmission format is the "NRZ" system and the transmission data rate is configurable by setting the proprietary baud rate generator, external clocks, internal timers.
CHAPTER 10 UART ■ Selection of transfer clocks The transfer clock can selected from the external clock (SCK pin), PWM timer or dedicated baud rate generator by setting CS0 and CS1 bits of serial rate control register (SRC). In addition, the CR bit of SRC and SMDE bit of serial mode control register 1 (SMC1) can determine which divider for the selected transfer clock. Please refer to Table 10.1-2 "Clock ratio". Table 10.
CHAPTER 10 UART Table 10.1-4 "Transfer cycle and transfer rate by baud rate generator" is shown the example of baud rate when using the dedicated baud rate generator. Table 10.1-4 Transfer cycle and transfer rate by baud rate generator Baud rate (bps) 4.
CHAPTER 10 UART Table 10.1-5 Transfer cycle and transfer rate by external clocks Asynchronous transfer mode Selected baud rate division value CR = 0 CR = 1 Synchronous transfer mode Transfer cycle Transfer rate (baud) (*1) 16 128/FCH or more 39062 or less 64 512/FCH or more Selected baud rate division value Transfer cycle Transfer rate (baud) (*1) 1 8/FCH or more 625k or less 9765 or less FCH: Main clock oscillation frequency *1: Min. external clock cycle of (8/FCH = 0.
CHAPTER 10 UART Table 10.1-6 Transfer cycle and transfer rate by 8-bit PWM timers Asynchronous transfer mode PWM timer count clock cycle 1 tinst 16 tinst 64 tinst 1 tinst From PWC timer 4 tinst 32 tinst Synchronous transfer mode Clock division value Transfer rate (baud) (*1) CR = 0 16 39062 to 152.6 CR = 1 64 9765.6 to 38.1 CR = 0 16 2441.4 to 9.5 CR = 1 64 610.4 to 2.4 CR = 0 16 610.4 to 2.4 CR = 1 64 152.6 to 0.6 CR = 0 16 19531.3 to 76.3 CR = 1 64 4882.8 to 19.
CHAPTER 10 UART 10.2 Structure of UART The UART consists of the following blocks: • Baud rate generator and serial clock generator • Data transmitter and data receiver • Registers (SMC1, SMC2, SRC, SSD, SIDR, SODR) ■ Block diagram of UART Figure 10.
CHAPTER 10 UART ● Baud rate generator and serial clock generator This block generates transmit/receive clocks from the outputs of baud rate generator, 8-bit PWM timer or external clock. ● Date receive control circuit The receive control circuit consists of the receive byte counter, the start bit detection circuit and the receive parity circuit. The receive byte counter counts number of data bit received and generates an interrupt after having received data of the specified length.
CHAPTER 10 UART ● Serial output data register (SODR) This register stores data to be transmitted. The data written in this register is converted to serial data and sent to serial output pin. When the data length is set to be 7 bits, bit 7 does not have meaning.
CHAPTER 10 UART 10.3 UART Pins This section describes the pins and pin block diagram of UART. ■ UART pins The pins for the UART function are shift clock input/output pin (P45/SCK), serial data output pin (P44/SO) and serial data input pin (P43/SI). P45/SCK: This pin function either as a general-purpose input/output port (P45) or a clock input output pin (hysteresis input) for the UART(SCK).
CHAPTER 10 UART ■ Block diagram of UART pins Figure 10.3-1 Block diagram of UART pins For P45/SCK and P43/SI To peripheral input PDR (Port data register) Stop mode (SPL = 1) Pull-up resistor Approx.
CHAPTER 10 UART 10.4 UART Registers This section describes the registers of the UART. ■ UART registers Figure 10.
CHAPTER 10 UART 10.4.1 Serial Mode Control Register 1 (SMC1) Serial mode control register 1 (SMC1) sets synchronous mode, stop bit length, data length, parity/non-parity and select the port function of SCK and SO. ■ Serial mode control register 1 (SMC1) Figure 10.
CHAPTER 10 UART Table 10.4-1 Serial mode control register 1 (SMC1) bits Bit Function Bit 7 PEN: Parity control bit • In the clock asynchronous mode, sets whether there is parity data or not. Bit 6 SBL: Stop bit length control bit • This bit determines the stop bit length. • In serial transmission, a stop bit of the bit length specified is appended. • In serial reception, a stop bit is recognized as in a 1-bit length regardless of the value set here.
CHAPTER 10 UART 10.4.2 Serial Rate Control Register (SRC) The serial rate control register (SRC) is to set the UART transmission speed (baud rate). ■ Serial rate control register (SRC) Figure 10.
CHAPTER 10 UART Table 10.4-2 Serial rate control register (SRC) bits Bit Function Bit 7 Bit 6 Unused bits • The read value is indeterminate. • Writing to these bits has no effect on the operation. Bit 5 CR: Clock rate selection bit • Used to select the asynchronous transfer clock rate. However, when the CS1 and CS0 bit are "11B", the 1/8 clock rate is selected in spite of the value of the CR bit. Bit 4 Bit 3 CS1, CS0: Transfer clock selection bits • Used to select the clock input of the UART.
CHAPTER 10 UART 10.4.3 Serial Status and Data Register (SSD) The serial status and data register (SSD) is used to set and monitor transmit/receive operation and error status. ■ Serial status and rate register (SSD) Figure 10.
CHAPTER 10 UART Table 10.4-3 Serial status and data register (SSD) bits Bit Function Bit 7 RDRF: Receive data register full bit • This flag represents the status of the serial input data register (SIDR). • This flag is set when receiving data is loaded into the SIDR register. It is cleared when the SIDR register is read. If the RDRF bit is set when the RIE bit is "1", a receive interrupt request is generated.
CHAPTER 10 UART 10.4.4 Serial Input Data Register (SIDR) The serial input data register (SIDR) is used to input (receive) serial data. ■ Serial input data register (SIDR) Figure 10.4-5 "Serial input data register (SIDR)" shows the bit allocations of the serial input data register. Figure 10.
CHAPTER 10 UART 10.4.5 Serial Output Data Register (SODR) The serial output data register (SODR) is used to output (transmit) serial data. ■ Serial output data register (SODR) Figure 10.4-6 shows the bit allocations of the serial output data register. Figure 10.
CHAPTER 10 UART 10.4.6 Serial Mode Control Register 2 (SMC2) Serial mode control register 2 (SMC2) selects the division ratio of the baud rate generator, selects to function as UART or SIO, and enables the baud rate generator. ■ Serial mode control register 2 (SMC2) Figure 10.
CHAPTER 10 UART Table 10.4-4 Serial mode control register 2 (SMC2) bits Bit Function Bit 7 Bit 6 Unused bits • The read value is indeterminate. • Writing to these bits has no effect on the operation. Bit 5 PSEN: Operation enable bit • This bit enables baud rate generator. Baud rate generator is stopped by writing "0" to this bit after transmitting/receiving the current serial data, then disabled thereafter. Bit 4 Reserved bit • Always write "0".
CHAPTER 10 UART 10.
CHAPTER 10 UART 10.6 Operation of UART This section describes the operation of the UART. The UART has a serial communication function (operation mode 0,1,3). ■ Operation of UART ● Operation mode The UART has 3 operation modes. The mode 0, 1, 3 are standard serial transmission modes in which a data type from 4-bit data length/parity to 9-bit data length/non-parity is selected (See Table 10.1-1 "UART operating mode").
CHAPTER 10 UART 10.7 Operation of Mode 0, 1, 3 The operation mode 0, 1 and 3 provide a serial communication function. ■ Operation of operation mode 0, 1, 3 Settings shown in Figure 10.7-1 "Operation of operation mode 0, 1, 3" are necessary for the UART operation. Figure 10.
CHAPTER 10 UART Figure 10.7-2 Transmit operation in mode 0, 1, 3 SSD read Write to the SODR (Interrupt processing routine) Transmit buffer full TDRE Transmit interrupt Transfer the data to the transmit shift register. Transfer the data to the transmit shift register. Transmit data START 0 1 2 3 4 5 6 7 STOP START ■ Receive operation If receive data is received from the serial data input pin, a serial-parallel conversion process is initiated in the internal receive shift register.
CHAPTER 10 UART Figure 10.7-3 Receive operation in mode 0, 1, 3 Data START 0 1 2 3 4 5 6 7 8 STOP RDRF Receive interrupt Figure 10.7-4 Operation at overrun error in mode 0, 1, 3 Data START 0 1 2 3 4 5 6 7 8 STOP RDRF=1 (Receive buffer full) ORFE Receive interrupt Figure 10.
CHAPTER 10 UART 10.8 Program Example for UART This section gives program example for UART. ■ Program example for UART ● Processing description • Perform serial transmit/receive operation using communication functions of the UART. • P45/SCK, P44/SO and P43/SI pins are used for communication. • Set a transmission speed of 150 baud by the internal baud rate generator. • A character "13H" is transmitted from the SO pin and triggers the operation by interrupt.
CHAPTER 10 UART ● Coding example PDR4 DDR4 SMC1 SRC SSD SIDR SODR SMC2 PSEN ILR2 INT_V EQU EQU EQU EQU EQU EQU EQU EQU EQU 000EH 000FH 0020H 0021H 0022H 0023H 0023H 0024H SMC2:5 ; ; ; ; ; ; ; ; ; ; ; ; Address of the port data register Address of the port direction register Address of the serial mode control register 1 Address of the serial rate control register Address of the serial status and data register Address of the serial input data register Address of the serial output data register Address of
CHAPTER 10 UART 222
CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT (EDGE) This chapter describes the functions and operation of the external interrupt circuit. 11.1 "Overview of the External Interrupt Circuit" 11.2 "Block Diagram of the External Interrupt Circuit" 11.3 "Structure of the External Interrupt Circuit" 11.4 "External Interrupt Circuit Interrupts" 11.5 "Operation of the External Interrupt Circuit" 11.
CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT (EDGE) 11.1 Overview of the External Interrupt Circuit The external interrupt circuit detects edges on the signals input to the two external interrupt pins and generates the corresponding interrupt requests to the CPU. ■ Functions of the external interrupt circuit The function of the external interrupt circuit is to detect specified edges on signals input to the external interrupt pins and to generate interrupt requests to the CPU.
CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT (EDGE) 11.2 Block Diagram of the External Interrupt Circuit The external interrupt circuit consists of the following two elements: • Edge detect circuit 0, 1 • External interrupt control register (EIC) ■ Block diagram of the external interrupt circuit Figure 11.
CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT (EDGE) 11.3 Structure of the External Interrupt Circuit This section describes the pins, pin block diagram, register, and interrupt sources of the external interrupt circuit. ■ External interrupt circuit pins The external interrupt circuit has two external interrupt pins. The external interrupt pins can function either as external interrupt inputs (hysteresis inputs) or general I/O ports.
CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT (EDGE) Reference: Pins with a pull-up resistor go to the "H" level (pull-up state) rather than to the high-impedance state when the output transistor is turned "OFF". ■ External interrupt circuit register Figure 11.
CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT (EDGE) 11.3.1 External Interrupt Control Register (EIC) External interrupt control register (EIC) is used to select the edge polarity and to control interrupts for external interrupt pins (INT0, INT1). ■ External interrupt control register (EIC) Figure 11.
CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT (EDGE) Table 11.3-2 External interrupt control register (EIC) bits Bit Function Bit 7 EIR1: INT1 external interrupt request flag bit • This bit is set to "1" when the edge selected by INT1 edge polarity selection bits (SL11, SL10) is input to external interrupt pin INT1. • An interrupt request is output when both this bit and INT1 interrupt request enable bit (EIE1) are "1". • Writing "0" clears the bit. Writing "1" has no effect and does not change the bit value.
CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT (EDGE) 11.4 External Interrupt Circuit Interrupts The external interrupt circuit can generate interrupt requests when it detects a specified edge on the signal input to an external interrupt pin. ■ Interrupts when the external interrupt circuit is operating On detecting a specified edge on an external interrupt input, the external interrupt circuit sets the corresponding external interrupt request flag bit (EIC: EIR0 - EIR1) to "1".
CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT (EDGE) 11.5 Operation of the External Interrupt Circuit The external interrupt circuit can detect a specified edge on a signal input to an external interrupt pin. ■ Operation of the external interrupt circuit Figure 11.5-1 "External interrupt circuit settings" shows the settings required to operate the external interrupt circuit. Figure 11.
CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT (EDGE) 11.6 Program Example for the External Interrupt Circuit This section gives a program example for the external interrupt circuit. ■ Program example for the external interrupt circuit ● Processing description • Generates interrupts on detecting a rising edge on pulses input to the INT1 pin.
CHAPTER 12 LCD CONTROLLER/DRIVER This chapter describes the functions and operation of the LCD controller/driver. 12.1 "Overview of LCD Controller/Driver" 12.2 "Block Diagram of LCD Controller/Driver" 12.3 "Structure of LCD Controller/Driver" 12.4 "Operation of LCD Controller/Driver" 12.
CHAPTER 12 LCD CONTROLLER/DRIVER 12.1 Overview of LCD Controller/Driver The LCD controller/driver includes 21 bytes of on-chip display data in memory, the contents of which control an LCD via 42 segment and 4 common outputs. The function can drive an LCD panel directly, using one of three selectable duty ratios.
CHAPTER 12 LCD CONTROLLER/DRIVER 12.2 Block Diagram of LCD Controller/Driver The LCD controller/driver is made up of seven blocks listed below. Functionally, the circuit can be broken into two major sections: the controller section, which generates LCD segment and common signals based on the current contents of display RAM, and the driver section, which develops sufficient drive to operate the display.
CHAPTER 12 LCD CONTROLLER/DRIVER ● Display RAM This 42 x 4-bit block of RAM controls the segment output signals. Its contents are automatically read out to the segment outputs in synchronous with the timing of the selected common signal. ● Prescaler The prescaler generates one of the 4 frame frequencies according to the LCD control register setting. ● Timing controller This block controls the segment and common signals based on the frame frequency and LCD control register settings.
CHAPTER 12 LCD CONTROLLER/DRIVER 12.2.1 LCD Controller/Driver Internal Voltage Divider LCD driver supply voltage can be taken from an internal voltage divider (external voltage divider may also be used). ■ Internal voltage divider In these devices, external voltage divider may also be connected at pins V1 through V3. The selection of internal or external voltage divider is made by the drive supply voltage control bit of LCD control register (LCDR: VSEL). VSEL = "1" connects the internal voltage divider.
CHAPTER 12 LCD CONTROLLER/DRIVER ■ Use of internal voltage divider Figure 12.2-3 "Use of internal voltage divider" shows the voltage divider circuits for 1/2 and 1/3 bias. As shown in this figure, in the 1/2 bias mode (with LCD enabled) V2 and V1 will be 1/2 of V3 (V3 is the LCD operating voltage, which is VCC in this configuration). In the 1/3 bias mode, V1 is 1/3 of V3, and V2 is 2/3 of V3. Figure 12.
CHAPTER 12 LCD CONTROLLER/DRIVER 12.2.2 LCD Controller/Driver External Voltage Divider External voltage divider can also be used with devices that have internal voltage divider. Display brightness can be adjusted by a variable resistor(VR) connected between the VCC and V3 pins. ■ External voltage divider When you do not wish to use the internal voltage divider, external voltage divider resistors can be connected at the LCD drive voltage supply pins (V1 to V3). Figure 12.
CHAPTER 12 LCD CONTROLLER/DRIVER ■ Use of external voltage divider Figure 12.2-6 "External voltage divider connection" shows an external voltage divider connection. Figure 12.2-6 External voltage divider connection Vcc V3 V3 VR RX V2 V1 R V2 R V1 R LCD enable RX RX N-ch MB89950/950A series V1 to V3: Voltages at V1 to V3 pins.
CHAPTER 12 LCD CONTROLLER/DRIVER 12.3 Structure of LCD Controller/Driver This section describes the pins, pin block diagrams, registers, and display RAM of the LCD controller/driver. ■ LCD controller/driver pins The LCD controller/driver uses 4 common output pins (COM0 to COM3), 42 segment output pin (SEG0 to SEG41), and 3 LCD driving power supply pins (V1 to V3). ● COM0, COM1, COM2, and COM3 pins COM0 to COM3 can function LCD common output pins (COM0 to COM3).
CHAPTER 12 LCD CONTROLLER/DRIVER ■ Block diagrams of LCD controller/driver pins Figure 12.3-1 Block diagram of LCD controller/driver pins (dedicated common/segment output pins COM0 to COM3 and SEG0 to SEG19) Dedicated common/segment output pins Common/segment control signal P-ch LCD drive voltage (V3 or V2) N-ch Pin COM0 to COM3 SEG0 to SEG19 P-ch LCD drive voltage (V1 or Vss) N-ch Common/segment control signal V1 to V3: V1 to V3 pin voltages Figure 12.
CHAPTER 12 LCD CONTROLLER/DRIVER Figure 12.3-3 Block diagram of LCD controller/driver pin (P32/V1 and P33/V2) PSEL bit of LCDR register V1 or V2 PDR (Port data register) N-ch P-ch Stop mode (SPL = 1) Internal data bus PDR read PDR read (for bit manipulation instructions) Output latch PDR write Pin N-ch Stop mode (SPL = 1) P32/V1 P33/V2 SPL: Pin state specification bit in the standby control register (STBC) ■ LCD controller/driver registers Figure 12.
CHAPTER 12 LCD CONTROLLER/DRIVER 12.3.1 LCD Control Register (LCDR) LCD control register (LCDR) is used to select the frame cycle, control the LCD drive supply voltage, select display blanking/non-blanking, and select the display mode. ■ LCD control register (LCDR) Figure 12.
CHAPTER 12 LCD CONTROLLER/DRIVER Table 12.3-1 LCD control register (LCDR) bit functions Bit Function Bit 7 Reserved bit • Always write "0" to this bit. Bit 6 PSEL: LCD power supply selection bit • Selects P32/V1 and P33/V2 to function either as N-ch open-drain I/O ports (P32, P33) or as LCD power supply pins (V1 and V2). Bit 5 VSEL: LCD drive supply voltage control bit • This bit controls the use of the internal voltage divider. Writing a "1" to it enables the use of the internal voltage divider.
CHAPTER 12 LCD CONTROLLER/DRIVER 12.3.2 Segment Output Select Register (SEGR) Segment output select register (SEGR) is used to select N-ch open-drain I/O port function or segment output function for P00/SEG20 to P07/SEG27, P10/SEG28 to P17/ SEG35 and P20/SEG36 to P25/SEG41, in order to be consistent with mask option. ■ Segment output select register (SEGR) Figure 12.
CHAPTER 12 LCD CONTROLLER/DRIVER Table 12.3-2 Segment output select register bit functions Bit Function Bit 7 Unused bit • The read value is indeterminate. • Writing to this bit has no effect on the operation. Bit 6 SEG15: Segment output selection bit • Selects P24/SEG40 to P25/SEG41 to function either as N-ch open-drain I/O ports (P24 to P25) or as LCD segment outputs (SEG40 to SEG41). Note: The setting of this bit MUST be consistent with mask option. This bit cannot override the mask option.
CHAPTER 12 LCD CONTROLLER/DRIVER 12.3.3 Display RAM Display RAM consists of 42 x 4-bit (21 bytes) of display data memory used to generate the segment output signals. ■ Display RAM and output pins The contents of display RAM are automatically read out and output via the segment outputs in synchronous with the selected common signal timing. A "1" bit is converted to a "select" (display on) voltage and a "0" to a "deselect" (display off) voltage.
CHAPTER 12 LCD CONTROLLER/DRIVER Table 12.
CHAPTER 12 LCD CONTROLLER/DRIVER 12.4 Operation of LCD Controller/Driver The LCD controller/driver provides the necessary control and drive for an LCD. ■ Operation of LCD controller/driver Figure 12.4-1 "LCD controller/driver settings" shows the settings required to operate the LCD. Figure 12.
CHAPTER 12 LCD CONTROLLER/DRIVER 12.4.1 Output Waveforms during LCD Controller/Driver Operation (1/2 Duty Ratio) The display drive output is a multiplex drive-type two-frame a.c. waveform. In the 1/2 duty ratio mode, the only common outputs are COM0 and COM1. (COM2 and COM3 are not used.) ■ 1/2 bias, 1/2 duty output waveform The maximum potential difference exists between a segment output and the corresponding common output when the segment (LCD cell) is turned on. Figure 12.
CHAPTER 12 LCD CONTROLLER/DRIVER Figure 12.
CHAPTER 12 LCD CONTROLLER/DRIVER ● LCD panel connections and display data example (1/2 duty ratio drive mode) Figure 12.4-3 Segment/common connections, data states and corresponding display Example) Using segments to represent "5". *0 SEGn COM1 *6 SEGn+3 *1 *5 SEGn+1 *2 *3 COM3 bit3 bit7 n+1H bit3 bit7 *4 SEGn+2 COM0 Address nH *7 COM2 COM1 COM0 bit2 bit1*1 bit0*0 SEGn *3 bit6 bit5 bit4*2 SEGn+1 *5 bit2 bit1 bit0*4 SEGn+2 bit6 bit5*7 bit4*6 Segment No.
CHAPTER 12 LCD CONTROLLER/DRIVER 12.4.2 Output Waveforms during LCD Controller/Driver Operation (1/3 Duty Ratio) In the 1/3 duty ratio mode, the COM0, COM1 and COM2 outputs are used by the display. COM3 is not used. ■ 1/3 bias, 1/3 duty output waveform The maximum potential difference exists between a segment output and the corresponding common output when the segment (LCD cell) is turned on. Figure 12.
CHAPTER 12 LCD CONTROLLER/DRIVER Figure 12.
CHAPTER 12 LCD CONTROLLER/DRIVER ● LCD panel connections and display data example (1/3 duty ratio drive mode) Figure 12.4-5 Segment/common connections, data states and corresponding display Example) Using segments to represent "5". COM0 *6 *3 *0 SEGn+3 *4 *7 SEGn COM1 *1 COM2 Address nH n+1H *5 *8 SEGn+2 SEGn+1 COM3 bit3 bit2*2 COM2 COM1 COM0 bit1*1 bit0*0 SEGn bit7 bit6*5 bit5*4 bit4*3 SEGn+1 bit3 bit2*8 bit1*7 bit0*6 SEGn+2 *0 to *8: Indicate corresponding display RAM bits.
CHAPTER 12 LCD CONTROLLER/DRIVER 12.4.3 Output Waveforms during LCD Controller/Driver Operation (1/4 Duty Ratio) In the 1/4 duty ratio mode, all four common outputs, COM0, COM1, COM2, and COM3 are used. ■ 1/3 bias, 1/4 duty output waveforms The maximum potential difference exists between a segment output and the corresponding common output when the segment (LCD cell) is turned on. Figure 12.
CHAPTER 12 LCD CONTROLLER/DRIVER Figure 12.
CHAPTER 12 LCD CONTROLLER/DRIVER ● 8-segment LCD panel connections and display data (1/4 duty ratio drive mode) Figure 12.4-7 Segment/common connections, data states and corresponding display Example) Using segments to represent "5". COM0 COM3 *4 *0 SEGn COM1 *5 *1 *2 COM3 COM2 COM1 COM0 bit3*3 bit2*2 bit1*1 bit0*0 SEGn bit7*7 bit6*6 bit5*5 bit4*4 SEGn+1 *0 to *7: Indicate corresponding display RAM bits.
CHAPTER 12 LCD CONTROLLER/DRIVER 12.5 Program Example for LCD Controller/Driver This section gives a program example for LCD controller/driver. ■ Program example for LCD controller/driver ● Processing description The process writes LCD data to display RAM. The data is that required to display the numbers "0" through "9" in an LCD panel connected as shown in Figure 12.4-7 "Segment/common connections, data states and corresponding display".
CHAPTER 12 LCD CONTROLLER/DRIVER ● Coding example LCRAM LCDR SEGR LCD LCDDATA EQU 0064H ;Starting address of LCD display RAM EQU 0079H ;Address of LCD control register (LCDR) EQU 007AH ;Address of segment output select register (SEGR) SEG CSEG ;8-segment LCD data DB 11011111B ;"0" DB 11001000B ;"1" DB 11110110B ;"2" DB 11111100B ;"3" DB 11101001B ;"4" DB 01111101B ;"5" DB 01111111B ;"6" DB 11011001B ;"7" DB 11111111B ;"8" DB 11111101B ;"9" DB 00000000B ;END LCD SEG ENDS ;-----Main program-----------------
CHAPTER 12 LCD CONTROLLER/DRIVER 262
APPENDIX This appendix includes I/O maps, instruction lists, and other information.
APPENDIX APPENDIX A I/O Map Table A-1 "I/O map" lists the addresses of the registers of used by the internal peripheral functions of the MB89950/950A series.
APPENDIX A I/O Map Table A-1 I/O map (2/2) Address 1DH Register name SDR Register description Serial data register Read/Write Initial value R/W XXXXXXXXB 1EH (Vacancy) 1FH 20H SMC1 UART serial mode control register 1 R/W 00000-00B 21H SRC UART serial rate control register R/W --011000B 22H SSD UART serial status/data register R/W 00100-1XB 23H SIDR/SODR UART serial data register R/W XXXXXXXXB 24H SMC2 UART serial mode control register 2 R/W --1-0-00B R/W 00000000B 25H to 2
APPENDIX APPENDIX B Overview of Instructions Appendix B describes the instructions used by the F2MC-8L. B.1 "Overview of F2MC-8L Instructions" B.2 "Addressing" B.3 "Special Instructions" B.4 "Bit Manipulation Instructions (SETB, CLRB)" B.5 "F2MC-8L Instructions" B.
APPENDIX B Overview of Instructions B.1 Overview of F2MC-8L Instructions The F2MC-8L supports 140 types of instructions. ■ Overview of F2MC-8L instructions The F2MC-8L has 140 1-byte machine instructions (256-byte instruction map). An instruction code consists of an instruction and zero or more operands that follow. Figure B.1-1 "Relationship between the instruction codes and the instruction map" shows the relationship between the instruction codes and the instruction map. Figure B.
APPENDIX ■ Symbols used with Instructions Table B.1-1 "Symbols in the instruction list" lists the symbols used in the instruction code descriptions in Appendix B. Table B.
APPENDIX B Overview of Instructions B.2 Addressing The F2MC-8L has the following ten addressing modes: • Direct addressing • Extended addressing • Bit direct addressing • Index addressing • Pointer addressing • General-purpose register addressing • Immediate addressing • Vector addressing • Relative addressing • Inherent addressing ■ Explanation of addressing ● Direct addressing Direct addressing is indicated by dir in the instruction list.
APPENDIX ● Bit direct addressing Bit direct addressing is indicated by dir:b in the instruction list. This addressing is used to access a particular bit in the area between 0000H and 00FFH. In this addressing mode, the higher byte of the address is 00H and the lower byte is specified by the operand. The bit position at the address is specified by the lower three bits of the operation code. Figure B.2-3 "Example of bit direct addressing" shows an example. Figure B.
APPENDIX B Overview of Instructions ● General-purpose register addressing General-purpose register addressing is indicated by Ri in the instruction list. This addressing is used to access a register bank in the general-purpose register area. In this addressing mode, the higher byte of the address is always 01 and the lower byte is specified based on the contents of RP (register bank pointer) and the lower three bits of the operation code. Figure B.
APPENDIX ● Vector addressing Vector addressing is indicated by vct in the instruction list. This addressing is used to branch to a subroutine address stored in the vector table. In this addressing mode, vct information is contained in the operation codes, and the corresponding table addresses are created as shown in Table B.2-1 "Vector table addresses corresponding to vct". Table B.
APPENDIX B Overview of Instructions ● Relative addressing Relative addressing is indicated by rel in the instruction list. This addressing is used to branch to within the area between the address 128 bytes higher and that 128 bytes lower relative to the address contained in the PC (program counter). In this addressing mode, the result of a signed addition of the contents of the operand to the PC is stored in the PC. Figure B.2-9 "Example of relative addressing" shows an example. Figure B.
APPENDIX B.3 Special Instructions This section describes the special instructions used for other than addressing. ■ Special instructions ● JMP @A This instruction sets the contents of A (accumulator) to PC (program counter) as the address, and causes a branch to that address. One of the N branch destination addresses is selected from a table, and then transferred to A. The instruction can be executed to perform N-branch processing. Figure B.3-1 "JMP @A" shows a summary of the instruction. Figure B.
APPENDIX B Overview of Instructions ● MULU A This instruction performs an unsigned multiplication of AL (lower eight bits of the accumulator) and TL (lower eight bits of the temporary accumulator), and stores the 16-bit result in A. The contents of T (temporary accumulator) do not change. The contents of AH (higher eight bits of the accumulator) and TH (higher eight bits of the temporary accumulator) before execution of the instruction are not used for the operation.
APPENDIX ● XCHW A, PC This instruction swaps the contents of A and PC, resulting in a branch to the address contained in A before execution of the instruction. After the instruction is executed, A contains the address that follows the address of the operation code of MOVW A, PC. This instruction is effective especially when it is used in the main routine to specify a table for use in a subroutine. Figure B.3-5 "XCHW A, PC" shows a summary of the instruction. Figure B.
APPENDIX B Overview of Instructions ● CALLV #vct This instruction is used to branch to a subroutine address stored in the vector table. The instruction saves the return address (contents of PC) in the location at the address contained in SP (stack pointer), and uses vector addressing to cause a branch to the address stored in the vector table. Because CALLV #vct is a 1byte instruction, the use of this instruction for frequently used subroutines can reduce the entire program size. Figure B.
APPENDIX B.4 Bit Manipulation Instructions (SETB, CLRB) Some bits of peripheral function registers include bits that are read by a bit manipulation instruction differently than usual. ■ Read-modify-write operation By using these bit manipulation instructions, only the specified bit in a register or RAM location can be set to 1 (SETB) or cleared to 0 (CLRB).
APPENDIX B Overview of Instructions B.5 F2MC-8L Instructions Table B.5-1 "Transfer instructions" to Table B.5-4 "Other instructions" list the instructions used with the F2MC-8L. ■ Transfer instructions Table B.5-1 Transfer instructions No.
APPENDIX Table B.5-1 Transfer instructions (Continued) No.
APPENDIX B Overview of Instructions ■ Arithmetic instructions Table B.5-2 Arithmetic operation instructions No.
APPENDIX Table B.5-2 Arithmetic operation instructions (Continued) No.
APPENDIX B Overview of Instructions Table B.5-2 Arithmetic operation instructions (Continued) No.
APPENDIX ■ Branch instructions Table B.5-3 Branch instructions No.
APPENDIX B Overview of Instructions ■ Other instructions Table B.5-4 Other instructions No.
L 286 F E D C B A 9 8 7 6 5 4 3 2 A A A A A A dir, A A, T A, T XOR XOR XOR A A IX A, dir A, #d8 XORW XOR A AND AND AND A, dir A, #d8 A A ext, A A, ext ANDW AND MOV MOV MOV MOV MOV MOV MOV MOV MOV A, R7 A, R6 A, R5 A, R4 A, R3 A, R2 A, R1 A, R0 A, @EP MOV CMP CMP CMP CMP CMP CMP CMP A, R7 A, R6 A, R5 A, R4 A, R3 A, R2 A, R1 A, R0 A, @EP CMP A, R7 ADDC A, R6 ADDC A, R5 ADDC A, R4 ADDC A, R3 ADDC A, R2 ADDC A, R1 ADD
APPENDIX C Mask Options APPENDIX C Mask Options This appendix lists the mask options for the MB89950/950A series. ■ Mask options Table C-1 Mask options Part number MB89951A MB89953A MB89P955 MB89PV950 Specifying procedure Specify when ordering mask Set with EPROM programmer Setting not possible No.
APPENDIX Table C-2 Recommended port/segment mask option combinations Mask Options Number of segments Number of P00/SEG20 P10/SEG28 P14/SEG32 P20/SEG36 P24/SEG40 I/O ports (*1) to to to P16/SEG34 P17/SEG35 to to P07/SEG27 P13/SEG31 P15/SEG33 P23/SEG39 P25/SEG41 42 11 X X X X X X X 41 12 X X X X O X X 40 13 X X X O O X X 38 15 X X O O O X X 34 19 X O O O O X X 26 27 O O O O O X X 40 13 X X X X X X O 22 31 O O O O O O X 20 33 O O O
APPENDIX D Programming Specifications for One-Time PROM And EPROM Microcontroller APPENDIX D Programming Specifications for One-Time PROM And EPROM Microcontroller This appendix describes the programming specifications for one-time PROM and EPROM microcontroller. D.1 "Programming Specifications for One-time PROM and EPROM Microcontrollers" D.2 "Programming Yield and Erasure" D.
APPENDIX D.1 Programming Specifications for One-time PROM and EPROM Microcontrollers In EPROM mode, the MB89P955 function is equivalent to the MBM27C256A. This allows the PROM to be programmed with a general-purpose EPROM programmer by using the dedicated adaptor. Note that the electronic signature mode cannot be used. ■ EPROM programmer socket adaptor Depending on the EPROM programmer, inserting a capacitor of about 0.1 µF between VPP and VSS or VCC and VSS can stabilize programming operations. Table D.
APPENDIX D Programming Specifications for One-Time PROM And EPROM Microcontroller ■ Recommended screening conditions High-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked OTPROM microcomputer program. Table D.1-2 "Screening procedure" shows the screening procedure. Figure D.1-2 Screening procedure ■ Programming to the EPROM In EPROM mode, the MB89P955 function is equivalent to the MBM27C256A ● Programming procedure: 1.
APPENDIX ■ Bit map for PROM option Table D.1-2 "Bit map for PROM option" shows the bit map for PROM option. Table D.
APPENDIX D Programming Specifications for One-Time PROM And EPROM Microcontroller D.2 Programming Yield and Erasure This section describes the programming yield and the data erasure on EPROM microcomputer. ■ Programming yield All bits cannot be programmed at Fujitsu shipping test to a blanked OTPROM microcomputer, due to its nature. For this reason, a programming yield of 100% cannot be assured at all times.
APPENDIX D.3 Programming to the EPROM with Piggyback/Evaluation Device This section describes the programming to the EPROM with piggyback/evaluation device. ■ EPROM for use MBM27C256A-20TV ■ Programming socket adaptor To program to the PROM using an EPROM programmer, use the socket adaptor (manufacturer: Sun Hayato Co., Ltd.) listed below. Table D.3-1 Programming socket adaptor Package Adaptor socket part number LCC-32 (Rectangle) ROM-32LC-28DP-YG Inquiries: Sun Hayato Co., Ltd.
APPENDIX E MB89950/950A Series Pin States APPENDIX E MB89950/950A Series Pin States This section describes the pin states of the MB89950/950A series in various modes. ■ MB89950/950A series pin states The state of each pin of the MB89950/950A series of microcontrollers at sleep, stop and reset is as follows: 1. Sleep: The pin state immediately before entering sleep mode is held. 2.
APPENDIX 296
INDEX INDEX The index follows on the next page. This is listed in alphabetic order.
INDEX Index Numerics 1/2 bias, 1/2 duty output waveform ...................... 251 1/3 bias, 1/3 duty output waveform ...................... 254 1/3 bias, 1/4 duty output waveform ...................... 257 8-bit PWM timer interrupt source.......................... 127 8-bit PWM timer interrupt, register and vector table for ................................................................... 131 8-bit PWM timer pin.............................................. 126 8-bit PWM timer pin, block diagram of ...
INDEX I/O port function ..................................................... 70 I/O port, program example for................................ 98 instruction cycle ..................................................... 54 instruction map..................................................... 286 instruction, symbol used with ............................... 268 internal shift clock, using...................................... 185 internal voltage divider .........................................
INDEX port 3 pins .............................................................. 86 port 3 register ......................................................... 88 port 3, operation of ................................................. 90 port 3, structure of .................................................. 86 port 4 pin, block diagram of.................................... 93 port 4 pins .............................................................. 92 port 4 register function ...............................
INDEX UART pin, block diagram of ................................. 203 UART registers .................................................... 204 UART, block diagram of....................................... 199 UART, operation of .............................................. 216 UART, program example for ................................ 220 V W watchdog timer control register (WDTC) ..............115 watchdog timer function........................................112 watchdog timer, block diagram of.........
INDEX 302
CM25-10146-1E FUJITSU SEMICONDUCTOR • CONTROLLER MANUAL F2MC-8L 8-BIT MICROCONTROLLER MB89950/950A Series HARDWARE MANUAL July 2002 the first edition Published FUJITSU LIMITED Edited Technical Information Dept.
