FUJITSU SEMICONDUCTOR DATA SHEET DS04-21374-1E ASSP Dual Serial Input PLL Frequency Synthesizer MB15F74UL ■ DESCRIPTION The Fujitsu MB15F74UL is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 4000 MHz and a 2000 MHz prescalers. A 64/65 or a 128/129 for the 4000 MHz prescaler, and a 32/33 or a 64/65 for the 2000 MHz prescaler can be selected for the prescaler that enables pulse swallow operation. The BiCMOS process is used, as a result a supply current is typically 9.0 mA at 3.0 V.
MB15F74UL (Continued) • Direct power saving function : Power supply current in power saving mode Typ 0.1 µA (VCC = Vp = 3.0 V, Ta = +25 °C) Max 10 µA (VCC = Vp = 3.0 V) • Software selectable charge pump current : 1.5 mA/6.
MB15F74UL ■ PIN DESCRIPTION Pin no. Pin name I/O 1 finIF I Prescaler input pin for the IF-PLL. Connection to an external VCO should be AC coupling. 2 XfinIF I Prescaler complimentary input for the IF-PLL section. This pin should be grounded via a capacitor. 3 GNDIF Ground pin for the IF-PLL section. 4 VCCIF Power supply voltage input pin for the IF-PLL section (except for the charge pump circuit) , the shift register and the oscillator input buffer.
MB15F74UL ■ BLOCK DIAGRAM VpIF (6) VCCIF GNDIF (3) (4) Intermittent mode control (IF-PLL) FCIF SWIF 3 bit latch LDS PSIF (5) 7 bit latch 11 bit latch Phase comp. (IF-PLL) Binary 7-bit Binary 11-bit swallow counter programmable (IF-PLL) counter (IF-PLL) Charge pump Current (IF-PLL) Switch (7) DoIF fpIF finIF (1) XfinIF (2) Prescaler (IF-PLL) (32/33, 64/65) Lock Det. (IF-PLL) 2 bit latch T1 T2 14 bit latch 1 bit latch Binary 14-bit programmable ref.
MB15F74UL ■ ABSOLUTE MAXIMUM RATINGS Parameter Symbol Unit Min Max VCC −0.5 4.0 V Vp VCC 4.0 V VI −0.5 VCC + 0.5 V LD/fout VO GND VCC V DoIF, DoRF VDO GND Vp V Tstg −55 +125 °C Power supply voltage Input voltage Output voltage Rating Storage temperature WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
MB15F74UL ■ ELECTRICAL CHARACTERISTICS * (VCC = 2.7 V to 3.6 V, Ta = −40 °C to +85 °C) Parameter Symbol Input sensitivity “L” level input voltage “H” level input voltage “L” level input voltage “H” level input current “L” level input current “H” level input current “L” level input current Typ Max Unit finIF = 2000 MHz VCCIF = VpIF = 3.0 V 2.1 2.5 3.2 mA ICCRF *1 finRF = 2500 MHz VCCRF = VpRF = 3.0 V 5.7 6.5 8.4 mA IPSIF PSIF = PSRF = “L” 0.
MB15F74UL (Continued) (VCC = 2.7 V to 3.6 V, Ta = −40 °C to +85 °C) Parameter Symbol “H” level output current DoIF *8 DoRF IDOH *4 “L” level output current DoIF *8 DoRF IDOL IDOL/IDOH IDOMT *5 Charge pump current rate DOVD *6 vs VDO I vs Ta IDOTA *7 Value Condition Unit Min Typ Max CS bit = “H” −8.2 −6.0 −4.1 mA CS bit = “L” −2.2 −1.5 −0.8 mA CS bit = “H” 4.1 6.0 8.2 mA CS bit = “L” 0.8 1.5 2.2 mA VDO = Vp / 2 3 10 % 0.5 V ≤ VDO ≤ Vp − 0.
MB15F74UL ■ FUNCTIONAL DESCRIPTION 1.
MB15F74UL • Programmable Counter (LSB) 1 2 Data Flow 3 CN1 CN2 LDS 4 5 SWIF/ FCIF/ RF RF A1 to A7 N1 to N11 LDS SWIF/RF FCIF/RF CN1, 2 6 7 8 (MSB) 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 A1 A2 A3 A4 A5 A6 A7 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 : Divide ratio setting bits for the swallow counter (0 to 127) : Divide ratio setting bits for the programmable counter (3 to 2,047) : LD/fout signal select bit : Divide ratio setting bit for the prescaler (IF : SWIF, RF : SWRF) : Phase control
MB15F74UL • Prescaler Data Setting SW = “H” SW = “L” Prescaler divide ratio IF-PLL 32/33 64/65 Prescaler divide ratio RF-PLL 64/65 128/129 Divide ratio • Charge Pump Current Setting Current value CS ±6.0 mA 1 ±1.
MB15F74UL 3. Power Saving Mode (Intermittent Mode Control Circuit) Status PS pin Normal mode H Power saving mode L The intermittent mode control circuit reduces the PLL power consumption. By setting the PS pin low, the device enters into the power saving mode, reducing the current consumption. See the Electrical Characteristics chart for the specific value. The phase detector output, Do, becomes high impedance. For the dual PLL, the lock detector, LD, is as shown in the LD Output Logic table.
MB15F74UL 4. Serial Data Data Input Timing Divide ratio is performed through a serial interface using the Data pin, Clock pin, and LE pin. Setting data is read into the shift register at the rise of the Clock signal, and transferred to a latch at the rise of the LE signal. The following diagram shows the data input timing.
MB15F74UL ■ PHASE COMPARATOR OUTPUT WAVEFORM fr IF/RF fp IF/RF t WU t WL LD (FC bit = High) D o IF/RF H Z L (FC bit = Low) H D o IF/RF Z L • LD Output Logic IF-PLL section RF-PLL section LD output Locking state/Power saving state Locking state/Power saving state H Locking state/Power saving state Unlocking state L Unlocking state Locking state/Power saving state L Unlocking state Unlocking state L Notes : • Phase error detection range = −2π to +2π • Pulses on DoIF/RF signals during
MB15F74UL ■ TEST CIRCUIT (for Measuring Input Sensitivity fin/OSCIN) S.G. S.G. Controller (Divide ratio setting) 1000 pF 50 Ω 1000 pF S.G. 1000 pF 50 Ω GND OSCIN Clock Data 1000 pF 16 LE 15 finRF 14 XfinRF 4 13 GNDRF PSIF 5 12 VCCRF VpIF 6 11 PSRF finIF 1 XfinIF 2 GNDIF 3 VCCIF 20 19 18 17 MB15F74UL 7 8 9 10 50 Ω 1000 pF VCCRF VpIF VCCIF DoIF LD/fout DoRF VpRF 0.1 µF 0.1 µF VpRF 0.1 µF Oscilloscope 14 0.
MB15F74UL ■ TYPICAL CHARACTERISTICS 1. fin input sensitivity RF-PLL input sensitivity vs. Input frequency 10 0 SPEC VCC = 2.7 V PfinRF [dBm] −10 VCC = 3.0 V VCC = 3.6 V −20 SPEC −30 −40 −50 1000 1500 2000 2500 3000 3500 4000 finRF [MHz] 4500 5000 5500 6000 IF-PLL input sensitivity vs. Input frequency 10 0 SPEC PfinIF [dBm] −10 VCC = 2.7 V VCC = 3.0 V −20 VCC = 3.
MB15F74UL 2. OSCIN input sensitivity Input sensitivity vs. Input frequency 10 Input sensitivity VOSC (dBm) SPEC 0 −10 VCC = 2.7 V VCC = 3.0 V VCC = 3.
MB15F74UL 3. RF-PLL Do output current • 1.5 mA mode IDO − VDO Charge pump output current IDO (mA) 10.0 VCC = Vp = 3.0 V 0 −10.0 0.0 1.0 2.0 3.0 Charge pump output voltage VDO (V) • 6.0 mA mode IDO − VDO Charge pump output current IDO (mA) 10.0 VCC = Vp = 3.0 V 0 −10.0 0.0 1.0 2.0 3.
MB15F74UL 4. IF-PLL Do output current • 1.5 mA mode IDO − VDO Charge pump output current IDO (mA) 10.0 VCC = Vp = 3.0 V 0 −10.0 0.0 1.0 2.0 3.0 Charge pump output voltage VDO (V) • 6.0 mA mode IDO − VDO Charge pump output current IDO (mA) 10.0 VCC = Vp = 3.0 V 0 −10.0 0.0 1.0 2.0 3.
MB15F74UL 5. fin input impedance finIF input impedance 4 : 16.453 Ω −46.539 Ω 2 000.000 000 MHz 1 : 866.25 Ω −916.31 Ω 100 MHz 2: 76.5 Ω −319.2 Ω 500 MHz 3 : 31.078 Ω −152.46 Ω 1 GHz 1 2 3 4 START 100.000 000 MHz STOP 2 000.000 000 MHz finRF input impedance 4 : 25.791 Ω 34.824 Ω 4 000.000 000 MHz 1 : 35 336 Ω −151.85 Ω 1 GHz 4 2: 17.436 Ω −52.191 Ω 2 GHz 3 : 20.211 Ω −743.16 mΩ 3 GHz 3 1 2 START 1 000.000 000 MHz STOP 4 000.
MB15F74UL 6. OSCIN input impedance OSCIN input impedance 4 : 049.5 Ω −1.0414 kΩ 100.000 000 MHz 1 : 15.882 kΩ −11.652 kΩ 3 MHz 2 : 3.924 kΩ −8.942 kΩ 10 MHz 3: 286 Ω −2.5913 kΩ 4 40 MHz 231 START 3.000 000 MHz 20 STOP 100.
MB15F74UL ■ REFERENCE INFORMATION (for Lock-up Time, Phase Noise and Reference Leakage) Test Circuit S.G. OSCIN Do LPF fVCO = 2500 MHz VCC = 3.0 V KV = 50 MHz/V Ta = + 25 °C fr = 200 kHz CP : 6 mA mode fOSC = 13 MHz LPF fin 7.5 kΩ Spectrum Analyzer VCO To VCO 1500 pF 2.7 kΩ 330 pF 15000 pF • PLL Reference Leakage ATTEN 10 dB RL 0 dBm 10 dB/ ∆MKR −70.00 dB 200 kHz ∆MKR 200 kHz D −70.00 dB S CENTER 2.500000 GHz ∗ RBW 3.0 kHz VBW 3.0 kHz SPAN 1.
MB15F74UL (Continued) PLL Lock Up time PLL Lock Up time 2500 MHz→2550 MHz within ± 1 kHz L ch→H ch 440 µs 2550 MHz→2500 MHz within ± 1 kHz H ch→L ch 400 µs A Mkr x: 439.99764 µs y: 50.0009 MHz A Mkr x: 400.00146 µs y: −50.0013 MHz 100.0050 MHz 100.0050 MHz 2.00 kHz/div 2.00 kHz/div 99.99500 MHz 99.99500 MHz 0s 22 2.0000000 ms 0s 2.
MB15F74UL ■ APPLICATION EXAMPLE 1000 pF TCXO From controller GND OSCIN Clock Data 1000 pF finIF 1 20 19 18 17 16 LE 15 finRF 14 XfinRF 1000 pF 1000 pF 3.0 V XfinIF 2 GNDIF 3 VCCIF 4 13 GNDRF PSIF 5 12 VCCRF VpIF 6 11 PSRF MB15F74UL 7 8 9 10 3.0 V 0.1 µF 3.0 V 0.1 µF DoIF LD/fout DoRF VpRF 0.1 µF 1000 pF 3.0 V 0.1 µF LPF VCO Output VCO Output Lock Det.
MB15F74UL ■ USAGE PRECAUTIONS (1) VCCRF, VpRF, VCCIF and VpIF must be equal voltage. Even if either RF-PLL or IF-PLL is not used, power must be supplied to VCCRF, VpRF, VCCIF and VpIF to keep them equal. It is recommended that the non-use PLL is controlled by power saving function. (2) To protect against damage by electrostatic discharge, note the following handling precautions : • Store and transport devices in conductive containers. • Use properly grounded workstations, tools, and equipment.
MB15F74UL ■ PACKAGE DIMENSION 20-pad plastic BCC (LCC-20P-M05) 3.00(.118)TYP 3.60±0.10(.142±.004) 16 0.55±0.05 (.022±.002) (Mounting height) 11 11 0.25±0.10 (.010±.004) 16 0.50(.020) TYP 0.25±0.10 (.010±.004) INDEX AREA 3.40±0.10 (.134±.004) 2.70(.106) TYP "D" "A" 1 6 "C" 6 Details of "A" part 0.50±0.10 (.020±.004) 1 0.50(.020) TYP 2.80(.110)REF 0.075±0.025 (.003±.001) (Stand off) 0.05(.002) "B" Details of "B" part 0.50±0.10 (.020±.004) Details of "C" part 0.50±0.10 (.020±.
MB15F74UL FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use.