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April 2013

FAN3226 / FAN3227 / FAN3228 / FAN3229 • Rev. 1.1.0

FAN3226 / FAN3227 / FAN3228 / FAN3229 — Dual 2-A High-Speed, Low-Side Gate Drivers

FAN3226 / FAN3227 / FAN3228 / FAN3229

Dual 2-A High-Speed, Low-Side Gate Drivers

Features

 Industry-Standard Pinouts

 4.5-V to 18-V Operating Range

 3-A Peak Sink/Source at V

= 12 V

 2.4 A-Sink / 1.6-A Source at V

OUT

= 6 V

 Choice of TTL or CMOS Input Thresholds

 Four Versions of Dual Independent Drivers:

- Dual Inverting + Enable (FAN3226)

- Dual Non-Inverting + Enable (FAN3227)

- Dual Inputs in Two Pin-Out Configurations:

o Compatible with FAN3225x (FAN3228)

o Compatible with TPS2814D (FAN3229)

 Internal Resistors Turn Driver Off If No Inputs

 MillerDrive™ Technology

 12-ns / 9-ns Typical Rise/Fall Times (1-nF Load)

 Under 20-ns Typical Propagation Delay Matched

within 1 ns to the Other Channel

 Double Current Capability by Paralleling Channels

 8-Lead 3x3 mm MLP or 8-Lead SOIC Package

 Rated from –40°C to +125°C Ambient

 Automotive Qualified to AEC-Q100 (F085 Version)

Applications



Switch-Mode Power Supplies

 High-Efficiency MOSFET Switching

 Synchronous Rectifier Circuits

 DC-to-DC Converters

 Motor Control

 Servers

 Automotive-Qualified Systems (F085 version)

Description

The FAN3226-29 family of dual 2 A gate drivers is

designed to drive N-channel enhancement-mode

MOSFETs in low-side switching applications by

providing high peak current pulses during the short

switching intervals. The driver is available with either

TTL or CMOS input thresholds. Internal circuitry

provides an under-voltage lockout function by holding

the output low until the supply voltage is within the

operating range. In addition, the drivers feature matched

internal propagation delays between A and B channels

for applications requiring dual gate drives with critical

timing, such as synchronous rectifiers. This enables

connecting two drivers in parallel to effectively double

the current capability driving a single MOSFET.

The FAN322X drivers incorporate MillerDrive™

architecture for the final output stage. This bipolar-

MOSFET combination provides high current during the

Miller plateau stage of the MOSFET turn-on / turn-off

process to minimize switching loss, while providing rail-

to-rail voltage swing and reverse current capability.

The FAN3226 offers two inverting drivers and the

FAN3227 offers two non-inverting drivers. Each device

has dual independent enable pins that default to ON if

not connected. In the FAN3228 and FAN3229, each

channel has dual inputs of opposite polarity, which

allows configuration as non-inverting or inverting with an

optional enable function using the second input. If one

or both inputs are left unconnected, internal resistors

bias the inputs such that the output is pulled low to hold

the power MOSFET off.

Related Resources



AN-6069: Application Review and Comparative

Evaluation of Low-Side Gate Drivers

FAN3226 FAN3227 FAN3228 FAN3229

Figure 1. Pin Configurations

Summary of content (26 pages)

PAGE 1
FAN3226 / FAN3227 / FAN3228 / FAN3229 Dual 2-A High-Speed, Low-Side Gate Drivers Features       Description Industry-Standard Pinouts 4.5-V to 18-V Operating Range 3-A Peak Sink/Source at VDD = 12 V 2.4 A-Sink / 1.
PAGE 2
Part Number Logic Input Threshold FAN3226CMPX FAN3226CMX CMOS FAN3226CMX_F085 (1) FAN3226TMPX Dual Inverting Channels + Dual Enable FAN3226TMX FAN3226TMX_F085 TTL (1) FAN3227CMPX FAN3227CMX CMOS FAN3227CMX_F085 (1) FAN3227TMPX FAN3228TMX_F085 (1) Dual Channels of Two-Input / One-Output Drivers, Pin Configuration 1 FAN3229CMX_F085 (1) FAN3229TMPX 3,000 SOIC-8 Tape & Reel 2,500 SOIC-8 Tape & Reel 2,500 3x3 mm MLP-8 Tape & Reel 3,000 SOIC-8 Tape & Reel 2,500 SOIC-8 Tape & Re
PAGE 3
Figure 2. 3x3 mm MLP-8 (Top View) Figure 3. SOIC-8 (Top View) Thermal Characteristics(2) ΘJL(3) ΘJT(4) ΘJA(5) ΨJB(6) ΨJT(7) Unit 8-Lead 3x3 mm Molded Leadless Package (MLP) 1.6 68 43 3.5 0.8 °C/W 8-Pin Small Outline Integrated Circuit (SOIC) 40 31 89 43 3.0 °C/W Package Notes: 2. Estimates derived from thermal simulation; actual values depend on the application. 3.
PAGE 4
FAN3227 FAN3228 FAN3229 Figure 4. Pin Configurations (Repeated) Pin Definitions Name Pin Description ENA Enable Input for Channel A. Pull pin LOW to inhibit driver A. ENA has TTL thresholds for both TTL and CMOS INx threshold. ENB Enable Input for Channel B. Pull pin LOW to inhibit driver B. ENB has TTL thresholds for both TTL and CMOS INx threshold. GND Ground. Common ground reference for input and output circuits. INA Input to Channel A. INA+ Non-Inverting Input to Channel A.
PAGE 5
FAN3226 / FAN3227 / FAN3228 / FAN3229 — Dual 2-A High-Speed, Low-Side Gate Drivers Block Diagrams VDD VDD 100k 100k ENA 1 8 ENB VDD 100k INA 2 7 OUTA 100k GND 3 UVLO 6 VDD VDD_OK VDD 100k INB 5 4 OUTB 100k Figure 5. FAN3226 Block Diagram Figure 6. FAN3227 Block Diagram © 2007 Fairchild Semiconductor Corporation FAN3226 / FAN3227 / FAN3228 / FAN3229 • Rev. 1.1.0 www.fairchildsemi.
PAGE 6
FAN3226 / FAN3227 / FAN3228 / FAN3229 — Dual 2-A High-Speed, Low-Side Gate Drivers Block Diagrams Figure 7. FAN3228 Block Diagram Figure 8. FAN3229 Block Diagram © 2007 Fairchild Semiconductor Corporation FAN3226 / FAN3227 / FAN3228 / FAN3229 • Rev. 1.1.0 www.fairchildsemi.
PAGE 7
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Unit -0.3 20.0 V VDD VDD to PGND VEN ENA and ENB to GND GND - 0.3 VDD + 0.
PAGE 8
Unless otherwise noted, VDD=12 V, TJ=-40°C to +125°C. Currents are defined as positive into the device and negative out of the device. Symbol Parameter Conditions Min. Typ. Max. Unit Supply VDD Operating Range 4.5 18.0 V 0.75 1.20 mA CMOS(9) 0.65 1.05 mA IDD Supply Current Inputs / EN Not Connected TTL VON Turn-On Voltage INA=ENA=VDD, INB=ENB=0 V 3.5 3.9 4.3 V VOFF Turn-Off Voltage INA=ENA=VDD, INB=ENB=0 V 3.3 3.7 4.
PAGE 9
Unless otherwise noted, VDD=12 V, TJ=-40°C to +125°C. Currents are defined as positive into the device and negative out of the device. Symbol Parameter Conditions Min. Typ. Max.
PAGE 10
90% 90% Output Output 10% Input 10% VINH Input VINL tD1 tD2 t RISE VINH VINL tD1 t FALL tD2 tRISE tFALL Figure 9. Non-Inverting (EN HIGH or Floating) Figure 10. Inverting (EN HIGH or Floating) Figure 11. Non-Inverting (IN HIGH) Figure 12. Inverting (IN LOW) © 2007 Fairchild Semiconductor Corporation FAN3226 / FAN3227 / FAN3228 / FAN3229 • Rev. 1.1.0 www.fairchildsemi.
PAGE 11
Typical characteristics are provided at 25°C and VDD=12 V unless otherwise noted. 1.6 1.6 1.4 FAN3226C, 27C 1.2 1.2 1.0 1.0 IDD (mA) IDD (mA) 1.4 0.8 0.6 0.4 0.8 0.6 0.4 Inputs and Enables Floating, Outputs 0.2 TTL Input Inputs and Enables Floating, Outputs Low 0.2 0.0 0.0 4 6 8 10 12 14 16 4 18 6 Supply Voltage (V) 8 10 12 14 16 18 Supply Voltage (V) Figure 13. IDD (Static) vs. Supply Voltage(15) Figure 14. IDD (Static) vs. Supply Voltage(15) 1.6 1.
PAGE 12
Typical characteristics are provided at 25°C and VDD=12 V unless otherwise noted. Figure 18. IDD (1 nF Load) vs. Frequency Figure 19. IDD (1 nF Load) vs. Frequency 1.6 1.6 FAN3226C, 27C 1.4 1.2 1.2 1.0 1.0 IDD (mA) IDD (mA) 1.4 0.8 0.6 0.2 0.0 -50 -25 0 25 50 75 Tem perature (°C) 100 0.8 0.6 Inputs and Enables Floating, Outputs 0.4 Inputs and Enables Floating, Outputs 0.4 TTL Input 0.2 0.0 -50 125 Figure 20. IDD (Static) vs.
PAGE 13
Typical characteristics are provided at 25°C and VDD=12 V unless otherwise noted. Figure 23. Input Thresholds vs. Supply Voltage Figure 24. Input Thresholds vs. Supply Voltage Figure 25. Input Threshold % vs. Supply Voltage Figure 26. Input Thresholds vs. Temperature © 2007 Fairchild Semiconductor Corporation FAN3226 / FAN3227 / FAN3228 / FAN3229 • Rev. 1.1.0 Figure 27. Input Thresholds vs. Temperature www.fairchildsemi.
PAGE 14
Typical characteristics are provided at 25°C and VDD=12 V unless otherwise noted. Figure 28. UVLO Thresholds vs. Temperature Figure 29. UVLO Threshold vs. Temperature Figure 30. Propagation Delays vs. Supply Voltage Figure 31. Propagation Delays vs. Supply Voltage Figure 32. Propagation Delays vs. Supply Voltage Figure 33. Propagation Delays vs. Supply Voltage © 2007 Fairchild Semiconductor Corporation FAN3226 / FAN3227 / FAN3228 / FAN3229 • Rev. 1.1.0 www.fairchildsemi.
PAGE 15
Typical characteristics are provided at 25°C and VDD=12 V unless otherwise noted. Figure 34. Propagation Delays vs. Temperature Figure 35. Propagation Delays vs. Temperature Figure 36. Propagation Delays vs. Temperature Figure 37. Propagation Delays vs. Temperature Figure 38. Fall Time vs. Supply Voltage Figure 39. Rise Time vs. Supply Voltage © 2007 Fairchild Semiconductor Corporation FAN3226 / FAN3227 / FAN3228 / FAN3229 • Rev. 1.1.0 www.fairchildsemi.
PAGE 16
Typical characteristics are provided at 25°C and VDD=12 V unless otherwise noted. Figure 40. Rise and Fall Times vs. Temperature Figure 41. Rise/Fall Waveforms with 1 nF Load Figure 42. Rise/Fall Waveforms with 10 nF Load Figure 43. Quasi-Static Source Current with VDD=12 V Figure 44. Quasi-Static Sink Current with VDD=12 V © 2007 Fairchild Semiconductor Corporation FAN3226 / FAN3227 / FAN3228 / FAN3229 • Rev. 1.1.0 www.fairchildsemi.
PAGE 17
Typical characteristics are provided at 25°C and VDD=12 V unless otherwise noted. Figure 45. Quasi-Static Source Current with VDD=8 V Figure 46. Quasi-Static Sink Current with VDD=8 V Note: 15. For any inverting inputs pulled low, non-inverting inputs pulled high, or outputs driven high, static IDD increases by the current flowing through the corresponding pull-up/down resistor shown in the block diagram. Test Circuit Figure 47.
PAGE 18
Input Thresholds MillerDrive™ Gate Drive Technology Each member of the FAN322x driver family consists of two identical channels that may be used independently at rated current or connected in parallel to double the individual current capacity. In the FAN3226 and FAN3227, channels A and B can be enabled or disabled independently using ENA or ENB, respectively. The EN pin has TTL thresholds for parts with either CMOS or TTL input thresholds.
PAGE 19
best results, make connections to all pins as short and direct as possible. To enable this IC to turn a device on quickly, a local highfrequency bypass capacitor CBYP with low ESR and ESL should be connected between the VDD and GND pins with minimal trace length. This capacitor is in addition to bulk electrolytic capacitance of 10 µF to 47 µF commonly found on driver and controller bias circuits.  A typical criterion for choosing the value of CBYP is to keep the ripple voltage on the VDD supply to ≤5%.
PAGE 20
Operational Waveforms The FAN3228/FAN3229 truth table indicates the operational states using the dual-input configuration. In a non-inverting driver configuration, the IN- pin should be a logic low signal. If the IN- pin is connected to logic high, a disable function is realized, and the driver output remains low regardless of the state of the IN+ pin. At power-up, the driver output remains low until the VDD voltage reaches the turn-on threshold.
PAGE 21
In the forward converter with synchronous rectifier shown in the typical application diagrams, the FDMS8660S is a reasonable MOSFET selection. The gate charge for each SR MOSFET would be 60 nC with VGS = VDD = 7V. At a switching frequency of 500 kHz, the total power dissipation is: Gate drivers used to switch MOSFETs and IGBTs at high frequencies can dissipate significant amounts of power.
PAGE 22
Figure 55. Forward Converter with Synchronous Rectification Figure 56. Primary-Side Dual Driver in a Push-Pull Converter Figure 57. Phase-Shifted Full-Bridge with Two Gate Drive Transformers (Simplified) © 2007 Fairchild Semiconductor Corporation FAN3226 / FAN3227 / FAN3228 / FAN3229 • Rev. 1.1.0 www.fairchildsemi.
PAGE 23
Type Part Number Gate Drive(16) Input (Sink/Src) Threshold Logic Single Channel of Dual-Input/Single-Output Package Single 1 A FAN3111C +1.1 A / -0.9 A CMOS Single 1 A FAN3111E +1.1 A / -0.9 A External Single 2 A FAN3100C +2.5 A / -1.8 A CMOS Single Channel of Two-Input/One-Output SOT23-5, MLP6 Single 2 A FAN3100T +2.5 A / -1.8 A TTL Single Channel of Two-Input/One-Output SOT23-5, MLP6 Single 2 A FAN3180 +2.4 A / -1.6 A TTL Single Non-Inverting Channel + 3.
PAGE 24
2X 2X 0.8 MAX RECOMMENDED LAND PATTERN 0.05 0.00 SEATING PLANE A. CONFORMS TO JEDEC REGISTRATION MO-229, VARIATION VEEC, DATED 11/2001 B. DIMENSIONS ARE IN MILLIMETERS. C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994 D. FILENAME: MKT-MLP08Drev2 Figure 58. 3x3 mm, 8-Lead Molded Leadless Package (MLP) Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice.
PAGE 25
5.00 4.80 A 0.65 3.81 5 8 B 6.20 5.80 PIN ONE INDICATOR 1.75 4.00 3.80 1 5.60 4 1.27 (0.33) 0.25 M 1.27 C B A LAND PATTERN RECOMMENDATION 0.25 0.10 SEE DETAIL A 1.75 MAX R0.10 0.10 0.51 0.33 0.50 x 45° 0.25 C OPTION A - BEVEL EDGE GAGE PLANE R0.10 8° 0° 0.90 0.406 0.25 0.19 C OPTION B - NO BEVEL EDGE 0.36 NOTES: UNLESS OTHERWISE SPECIFIED A) THIS PACKAGE CONFORMS TO JEDEC MS-012, VARIATION AA, ISSUE C, B) ALL DIMENSIONS ARE IN MILLIMETERS.
PAGE 26
FAN3226 / FAN3227 / FAN3228 / FAN3229 — Dual 2-A High-Speed, Low-Side Gate Drivers © 2007 Fairchild Semiconductor Corporation FAN3226 / FAN3227 / FAN3228 / FAN3229 • Rev. 1.1.0 www.fairchildsemi.