MF423-11 S1D12000 Series Technical Manual IEEE1394 LCD DRIVER Controller IC S1R72801F00A S1D12000 Series Technical Manual S1D12000 Series Technical Manual ELECTRONIC DEVICES MARKETING DIVISION EPSON Electronic Devices Website http://www.epson.co.jp/device/ This manual was made with recycle paper, and printed using soy-based inks. First issue November,1990 U Printed May,2001 in Japan H B 4.
NOTICE No parts of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice.
The information of the product number change Starting April 1, 2001 the product number will be changed as listed below. To order from April 1, 2001 please use the new product number. For further information, please contact Epson sales representative.
Previous number New number Previous number New number SED1231DJB SED1231DMB SED1231T01 SED1231T02 SED1231T0B SED1232 SED1232D** SED1232DAB SED1232DBB SED1232DGB SED1232DMB SED1233 SED1233D** SED1233D2E SED1233D3E SED1233DAE SED1233DBB SED1233DBE SED1233DGB SED1233DGE SED1233DMB SED1233DRA SED1233T0A SED1233T0B SED123*D*A SED123*D*B SED123*D*C SED123*D*F SED123*D..
CONTENTS 1. S1D12000 Series Selection Guide 2. S1D12200 Series 3. S1D12205 Series 4. S1D12300 Series 5. S1D12304/12305 Series 6.
S1D12000 series Selection Guide
■ LCD controller-drivers for Built-in character generators together with segment and common drivers simplify the task of displaying microprocessor messages on small LCDs. small-sized displays S1D12000 (SED1200) Series Part number Supply LCD voltage voltage range (V) Duty Segment Common Display RAM MPU Extension S1D12200D (SED1220D) S1D12200T 2.4 to 3.6 4.0 to 7.0 1/26 64 26 36 serial — Au bump 2.4 to 3.6 4.0 to 7.
S1D12200 Series Rev. 1.
Contents 1. DESCRIPTION ............................................................................................................................................. 2–1 2. FEATURES .................................................................................................................................................. 2–1 3. BLOCK DIAGRAM ...................................................................................................................................... 2–2 4. CHIP SPECIFICATION .
1. DESCRIPTION S1D12200 Series is a dot matrix LCD controller/driver for character display. Using 4bits data, 8bits data or serial data being provided from the micro computer, it displays up to 36 characters, 4 user defined characters and up to 120 symbols. Up to 256 types of built-in character generator ROMs are prepared. Each character font is consisted of 5 × 8 dots. It also contains the RAM for displaying 4 user defined characters each font consisting of 5 × 8 dots.
2–2 EPSON A0 SEG driving circuit COMSA SEG1~60 SEGSA, B, C, D, E SEGS1, 2, 4, 5 (S1D12200/12201/12202) SEGSA, B, C, D, E, F, G, H, I, J (S1D12210) Static icon drive circuit Timing generatinon circuit V1 COM1~24 (S1D12200/12201) COM1~16 (S1D12202/12210) COMS1, 2 COM driving circuit Refresh address counter P/S Input buffer WR (E) Cursor control CG ROM CG RAM CS Command decoder Address counter RES V2 Oscillator IF DD RAM symbol register D7 (SI) D6 (SCL) D5 D4 D3 D2 D1 D0 LCD powe
S1D12200 Series 4. CHIP SPECIFICATION S1D12200D****/S1D12201D****/S1D12210D**** 74 73 147 y x 63 62 Top View 56 55 165 54 1 :DUMY PAD :PAD S1D122 **D**** ↑ Digits prepared for CGROM pattern changes Chip size: 7.70 × 2.
S1D12200 Series S1D12202D**** 108 52 ......... 51 ... 109 ... y 41 ... x Top View 40 34 125 ... 1 ......... 11 12 33 ... 27 28 32 : PAD S1D12202D **** ↑ Digits prepared for CGROM pattern changes Chip size: 7.70 × 2.77 mm Pad pitch: 124 µm (Minimum) Chip thickness (for reference): 625 ± 50 µm (S1D12202D 1) A1 pad specifications Pad size on Y side: Pad size on X side: 1) Al pad. pad size 2–4 **A*) 90 µm × 96 µm 96 µm × 90 µm (PAD. No.
S1D12200 Series No.
S1D12200 Series PAD No.
S1D12200 Series No.
S1D12200 Series PAD No. 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 2–8 Name SEG58 SEG59 SEG60 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COMS2 SEGSA SEGSB SEGSC SEGSD SEGSE COORDINATES X Y –3694 1191 1067 943 819 695 571 447 323 119 75 –49 –173 –335 –459 –583 –707 –3694 –831 EPSON Rev. 1.
S1D12200 Series No.
S1D12200 Series PAD No.
S1D12200 Series 5. PIN DESCRIPTION Pin name VDD VSS V0, V1 V2, V3 V4, V5 VS1 I/O Description No. of Pins Power supply Connected to logic supply. Common with MPU power terminal VCC. 1 Power supply 0V power terminal connected to system ground. 1 Power supply Multi-level power supply for liquid crystal drive. 6 The voltage determined in the liquid crystal cell is resistancedivided or impedance-converted by operational amplifier, and the resultant voltage is applied.
S1D12200 Series Pins for System Bus Connection Pin name D7 (SI) D6 (SCL) D5 ~ D0 I/O I Description No. of Pins 8-bit input data bus. These pins are connected to a 8-bit or 16-bit 8 standard MPU data bus. When P/S = LOW, the D7 and D6 pins are operated as a serial data input and a serial clock input respectively.
S1D12200 Series Liquid Crystal Drive Circuit Signals Pin name COM1 to COM24 COMS1, CMOS2 SEG1 to SEG60 SEGS1, 2 4, 5 I/O Description No.
S1D12200 Series 6. FUNCTIONAL DESCRIPTION MPU Interface Selection of interface type In the S1D12200 Series, data transfer is performed through a 8-bit or 4-bit data bus or a serial data input (SI). By selecting HIGH or LOW as P/S pin polarity, a parallel data input or a serial data input can be selected as shown in Table 1.
S1D12200 Series CS SCL D7 1 D6 2 D5 3 D4 4 D3 5 D2 6 D1 7 D0 8 D7 S1D12200 Series SI 9 A0 Fig. 1 Identification of data bus signals The S1D12200 series identifies data bus signals, as shown in Table 3, by combinations of A0 and WR (E). Table 3 Common A0 1 0 68 series E 1 1 80 series WR 0 0 Function Writing to RAM and symbol register Writing to internal register (command) Chip select The S1D12200 series has a chip select pin (CS). Only when CS = LOW, MPU interfacing is enabled.
S1D12200 Series Voltage Tripler Circuit If capacitors are connected between CAP+1 – CAP–1 and CAP2+,CAP2– and VSS VOUT, VDD– VSS potential is negatively tripled and generated at VOUT terminal. When the voltage is boosted double, open CAP2+ and connect CAP2– to VOUT terminal. At this time, the oscillating circuit must be operating since the amplifying circuit utilize the signal from the oscillation output.
S1D12200 Series When using the electronic volume function, you need to turn the voltage regulation circuit on using the supply control command. The electronic volume function allows to control the liquid crystal drive voltage V5 with the commands and thus to adjust density of the liquid crystal display. Liquid crystal drive voltage V5 can have one of 32 voltage values if 5-bit data is set to the electronic volume register.
S1D12200 Series Liquid crystal voltage generating circuit V5 potential is resistive divided within IC to produce V1, V2, V3 and V4 potentials required for driving the liquid crystal. V1, V2, V3 and V4 potentials are then subject to impedance conversion and provided to the liquid crystal drive circuit. The liquid crystal drive voltage is fixed to 1/5 (1/4) bias. The liquid crystal power terminals V1 – V5 must be externally connected with the voltage regulating capacitor C2.
S1D12200 Series Example 3: When using the built-in power source (VC, VF, P) = (0, 1, 0) S1D12200D VSS S1D12200D **** VSS CAP1+ CAP1CAP2+ CAP2- CAP1+ CAP1CAP2+ CAP2VOUT VOUT External power source R3 V5 VR External power R2 source **** S1D12200 Series Example 2: When using the built-in power source (VC, VF, P) = (1, 1, 0) V5 VR R1 VDD, V0 C2 C2 C2 C2 C2 C2 VDD, V0 C2 C2 C2 C2 C2 C2 V1 V2 V3 V4 V5 VS1 V1 V2 V3 V4 V5 VS1 Reference setting values: C1: 0.47 - 4.
S1D12200 Series Low Power Consumption Mode S1D12200 Series is provided with standby mode and sleep mode for saving power consumption during standby period. Reset Circuit ● Standby Mode Switching between on and off of the standby mode is done using the power save command. In the standby mode, only static icon is displayed. 1.
S1D12200 Series Table 4 lists the commands. S1D12200 Series identifies the data bus signal using different combinations of A0 and WR (E). High speed command interpretation and execution are possible since only the internal timing is used.
S1D12200 Series (5) VF =0 1 : Voltage follower off : Voltage follower on VC =0 1 : Voltage regulation circuit off : Voltage regulation circuit on (6) RAM Address Set This command sets addresses to write data into the DD RAM, CG RAM and symbol register in the address counter. When the cursor is displayed, the cursor is displayed at the display position corresponding to the DD RAM address set by this command.
S1D12200 Series (7) Data Write RAM Address Set A0 WR D7 D6 D5 D4 D3 D2 D1 D0 1 0 DATA 2 This command writes data the DD RAM, CG RAM or symbol register. This command automatically increases the address counter by +1, thus enabling continuous writing of data. Following figures illustrates an example of continuous writing of one line data to DD RAM. Rev. 1.
S1D12200 Series Table 4 S1D12200 Series Command List Command (1) Cursor Home Code Function A0 WR D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 1 * * * * Moves the cursor to the home position. (2) Display ON/OFF 0 Control 0 0 0 1 1 C B * D Sets cursor ON/OFF (C), cursor blink ON//OFF (B), and display ON/OFF (D).
S1D12200 Series S1D12200D10** Lower 4 Bit of Code 0 1 2 3 4 5 6 7 8 9 A B C D E F S1D12200 Series 0 1 2 3 4 5 Higher 4 Bit of Cord 6 7 8 9 A B C D E F Rev. 1.
S1D12200 Series S1D12200D11** Lower 4 Bit of Code 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 Higher 4 Bit of Cord 6 7 8 9 A B C D E F 2–26 EPSON Rev. 1.
S1D12200 Series S1D12200D16** Lower 4 Bit of Code 0 1 2 3 4 5 6 7 8 9 A B C D E F S1D12200 Series 0 1 2 3 4 5 Higher 4 Bit of Cord 6 7 8 9 A B C D E F Rev. 1.
S1D12200 Series Character Generator RAM (CG ROM) CGRAM contained in S1D12200 Series enables user programming of character patterns for display signals with higher degrees of freedom. When using CGRAM, select it using the system command. Capacity of CGRAM is 160 bits and accepts registration of any 4 5 × 8 dots patterns. Following shows relationship between the CGRAM characters, CGRAM addresses and character code.
S1D12200 Series Symbol Register S1D12200 Series contains the symbol register which enable individual symbol setting for displaying on the screen. Capacity of the symbol register is 120 bits and is capable of displaying up to 120 symbols. 13 1 12 1 2 3 4 5 56 · · · 60 61 · · · 65 116 · · · 120 S1D12200 Series Following shows relationship between the symbol register display patterns, RAM addresses and written data.
S1D12200 Series 12201/12202) or 20 bit (S1D12210) and is capable of displaying up to 5 icons (S1D12200/12201/12202) or 10 icons (S1D12210). Following shows relationship between the static icons functions, static icon RAM addresses and written data. Static Icon Ram S1D12200 Series contains the static icon RAM for displaying the static icons in addition to the dynamic icons.
S1D12200 Series Item Symbol Standard value Unit Power supply voltage (1) VSS –6.0 to +0.3 V Power supply voltage (2) V5, Vout –7.0 to +0.3 V Power supply voltage (3) V1, V2, V3, V4 V5 to +0.3 V Input voltage VIN VSS–0.3 to +0.3 V Output voltage VO VSS–0.3 to +0.3 V Operating temperature Topr –30 to +85 °C –55 to +100 °C Storage temperature TCP Bare chip Tstr (VCC) VDD –65 to +125 S1D12200 Series 9. ABSOLUTE MAXIMUM RATINGS VDD (GND) VSS V5 Notes: 1.
S1D12200 Series 10. DC CHARACTERISTICS VDD = 0 V, VSS = –3.6 V to –2.4 V, Ta = –30 to 85°C unless otherwise specified.
S1D12200 Series *6: Current consumption when data is always written by fcyc. The current consumption in the access state is almost proportional to the access frequency (fcyc). When no access is made, only IDD (I) occurs. *7: tR (reset time) indicates the internal circuit reset completion time from the edge of the RES signal. Accordingly, the S1D12200 usually enters the operating state after tR. *8: Specifies the minimum pulse width of the RES signal.
S1D12200 Series 11.
S1D12200 Series (2) MPU Bus Write Timing (68 series) A0 S1D12200 Series tAH6 tAC6 CS tCYC6 tEWL tEWH E tDS6 tDH6 tAW6 D0 to D7 Item Signal Address setup time A0, CS Address hold time CS setup time System cycle time WR Enable LOW pulse width (Write) Enable HIGH pulse width (Write) Data setup time D0 ~ D7 Data hold time Item Signal Address setup time A0, CS Address hold time CS setup time System cycle time WR Enable LOW pulse width (Write) Enable HIGH pulse width (Write) Data setup time D0 to D7
S1D12200 Series (3) Serial Interface tCSS tCSH CS tSAS tSAH A0 tSCYC tSLW SCL tSHW tSDS tSDH SI Item System clock cycle SCL HIGH pulse width SCL LOW pulse width Address setup time Address hold time Data setup time Data hold time CS-SCL time Signal Symbol SCL tSCYC tSHW tSLW tSAS tSAH tSDS tSDH tCSS tCSH A0 SI CS [Ta = –30 to 85°C, VSS = –3.6 V to –2.4 V] Measuring Min. Max. Unit condition Every timing is specified 1000 ns on the basis of 20% and 300 ns 80% of VSS.
S1D12200 Series 12. MPU INTERFACE (REFERENCE EXAMPLES) The S1D12200 Series can be connected to the 80 series MPU and 68 series MPU. When an serial interface is used, the S1D12200 Series can be operated by less signal lines.
S1D12200 Series 13. LCD CELL INTERFACE (REFERENCE) 12 columns by 3 lines, 5 × 8-dot matrix segments and symbols S1D12200 LCD panel 1 . . . . . . . . . . . . . . . . . 12 static icon COMSA .. SEGSA SEGSE symbol COMS1 signal signal COMS2 COM1 2 3 4 5 6 7 8 COM9 10 11 12 13 14 15 16 COM17 18 19 20 21 22 23 24 character SEGS1 SEGS2 .. SEG1 2 3 4 5 SEG60 SEGS4 SEGS5 2–38 EPSON Rev. 1.
S1D12200 Series 12 columns by 2 lines, 5 × 8-dot matrix segments and symbols LCD panel 1 ............... 12 S1D12200 Series S1D12201 static icon COMSA .. SEGSA SEGSE symbol COMS1 signal signal COMS2 COM1 2 3 4 5 6 7 8 COM9 10 11 12 13 14 15 16 character SEGS1 SEGS2 .. SEG1 2 3 4 5 SEG60 SEGS4 SEGS5 Rev. 1.
S1D12200 Series 12 columns by 2 lines, 5 × 8-dot matrix segments and symbols S1D12202 LCD panel 1 • • • • • • • • • • • • • • 12 static icon COMSA .. SEGSA SEGSE symbol COMS1 COMS2 COM1 2 3 4 5 6 7 8 COM9 10 11 12 13 14 15 16 character .. SEG1 2 3 4 5 SEG60 2–40 EPSON Rev. 1.
S1D12200 Series 12 columns by 2 lines, 5 × 8-dot matrix segments and symbols S1D12210 LCD Panel 1 • • • • • • • • • • • • • • 12 Static icon S1D12200 Series COMSA • • SEGSA SEGSJ Symbol COMS1 COMS2 Signal Signal COM1 2 3 4 5 6 7 8 COM9 10 11 12 13 14 15 16 Character SEGS1 SEGS2 • • SEG1 2 3 4 5 SEG60 SEGS4 SEGS5 Rev. 1.
S1D12200 Series 14. LCD DRIVE WAVEFORMS (B WAVEFORMS) COM 1 COM 2 COM 3 COM 4 COM 5 COM 6 COM 7 COM 8 VDD V1 V2 V3 V4 V5 COM 1 VDD V1 V2 V3 V4 V5 COM 2 COM 9 COM 10 COM 11 COM 12 COM 13 COM 14 COM 15 COM 16 SEG 1 SEG 2 SEG 3 SEG 4 SEG 5 VDD V1 V2 V3 V4 V5 COM 3 VDD V1 V2 V3 V4 V5 SEG 1 VDD V1 V2 V3 V4 V5 SEG 2 V5 V4 V3 V2 V1 VDD -V1 -V2 -V3 -V4 -V5 COMO -SEG 1 V5 V4 V3 V2 V1 VDD -V1 -V2 -V3 -V4 -V5 COMO -SEG 2 2–42 EPSON Rev. 1.
S1D12200 Series 15. INSTRUCTION SETUP EXAMPLE (REFERENCE) (2) Display mode VDD-VSS power ON S1D12200 Series (1) Initial setup End of initialization Power regulation Input of RAM address setup command Input of reset signal Input of RAM (data) write command Command status • Static display control: Off • Display on/off control: Off • Power save: Off • Power control: Off • System setup: Off • Electronic volume (0, 0, 0, 0, 0) • Static icon (0, 0, 0, 0, 0) • Others are undefined.
S1D12200 Series (3-1) Selecting the Standby mode (3-2) Releasing the Standby mode Standby mode End of initialization Normal operation (Power Save is released and oscillator circuit is turned ON.
S1D12200 Series Instruction Setup Example of S1D12200 series Initial setup display ON “EPSON” Display ON the Icon Standby Mode sequence Releasing the Standby Mode sequence S1D12200 Series (1) (2) (3) (4) (5) .. SEGSE .. COM9 COMS2 SEGSA ............................. SEG60 SEGS4 SEGS5 COM24 ..
S1D12200 Series (1) Initial setup (1.1) VDD–VSS Power ON (1.2) Power regulation (1.3) Input of RESET signal (1.4) Command Status • Display ON/OFF • Power save • Power control • System reset • Electronic Volume • Static display control • Others are undefined. :OFF :OFF :OFF :OFF :(0, 0, 0, 0, 0) :OFF (1.5) Waiting for 10µ sec or more (1.6) Command Input: ((*) indicates any command sequence.
S1D12200 Series A0 WR D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 S1D12200 Series • Data writing: All data→20H (for 1 Line) • RAM
S1D12200 Series • Data writing: All data →20H (for 3 Line) A0 WR D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 • End of Initialization
S1D12200 Series A0 WR D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 1 1 0 0 0 0 S1D12200 Series (3) Display ON The Icon: Valid in Standby mode only (3.1) Display ON/OFF command: D→OFF (3.2) Static display control command: 1 ~ 2Hz Blink A0 WR D7 D6 D5 D4 D3 D2 D1 D0 0 0 1 0 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 1 0 1 0 0 0 0 1 1 0 0 0 0 1 0 0 0 0 (3.
S1D12200 Series 16. OPTION LIST S1D12200 Series provides the optional functions as described in the following. Being adaptable to the customer’s optional demand, contact the Business Department of our company when installed. o Our product name corresponding to a customer’s option is defined as shown below: (Example) S1D12200D **B* 4. Power Supply to Booster Circuit S1D12200 Series integrates a booster circuit.
EPSON S1D12200 S1D12205 Rev. 1.4 S1D12400 System set • S1 = 0 • S2 = 0 System set • CS = 0 • SS = 0 System set • CS = 0 • SS = 1 (SEG-reversed) However, the input of DDRAM address of "S1D12 ***" from the first digit of the first line shall be 3FH and 3EH, in this order (as it is reversed in the unit of character). System set • S=0 System set • S1 = 0 • S2 = 1 (Horizontally-reversed) • Unable to correspond with commands. • Only able to correspond with custom fonts.
S1D12205 Series Rev. 1.
Contents 1. DESCRIPTION ............................................................................................................................................. 3–1 2. FEATURES .................................................................................................................................................. 3–1 3. BLOCK DIAGRAM ....................................................................................................................................... 3–2 4. PIN LAYOUT ........
1. DESCRIPTION The S1D12205 Series dot-matrix LCD Controller Driver receives 4-bit, 8-bit, or serial data from the microprocessor and displays up to 36 characters, four user-defined characters, and up to 120 symbols. Up to 256 types of built-in character generator ROMs are provided. Each character font has a 5×8-dot structure. Also, the user-defined character RAM contains four 5×8-dot characters. In addition, a symbolic register can be used for flexible symbol display.
S1D12205 Series 3. BLOCK DIAGRAM D0 OSC D1 VS1 Input Buffer D2 D3 D4 D5 Address Counter D6(SCL) DDRAM Symbol Register Refresh Address Counter D7(SI) Timing Generator CK CGROM CGRAM OCA LCD Driver IF MPU Interface RES CS WR(E) PS C86 Command Decoder Cursor Control OCB OCC OCD OCE VREG1 VREG2 A0 V1 V3 LED Driver LE1 3–2 LE2 Static Icon Driver COMSA SEGSA to J V4 Segment Driver SEG1 to 60 SEGS1,2,4,5 EPSON COM Driver V5 COM1 to 24 COMS1,2 Rev. 1.
S1D12205 Series 4. PIN LAYOUT 154 73 .. .................... 155 72 X Top View 171 S1D12205 Series (0,0) ............. ............. Y 59 .................................... 1 58 : Dummy PAD : PAD S1D12205D **** ↑ CGROM pattern version number Chip size: 7.85 × 1.97 mm Pad pitch: 90 µm (min) Chip thickness (Reference): 625 µm Au bump specifications Bump size: Pad Nos. 59 to 72, and 155 to 171: 78 µm × 59 µm Pad Nos. 1 to 58, and 73 to 154: 59 µm × 78 µm Bump height (Reference): 22.
S1D12205 Series Pad Center Coordinates No.
S1D12205 Series No. Rev. 1.
S1D12205 Series 5. PIN DESCRIPTION Power Supply Pins Pin Name VDD VSS V1, V3 V4, V5 VS1 I/O Description Connects to the logic power supply. This is common to the Vcc power pin of Power supply the MPU. Power supply 0V power pin connected to system ground (GND) Multi-level LCD drive power supplies. A capacitor is required for external Power supply stabilization. Output pin of oscillator (OSC) power voltage. Do not connect any external O load to this pin. No.
S1D12205 Series System Bus Connector Pins Pin Name I/O Descrition No. of Pins An 8-bit input data bus to be connected to the standard 8- or 16-bit MPU data bus. Pins D7 and D6 function as the serial data and clock inputs respectively if PS is logical low.
S1D12205 Series LCD Driver Signals Dynamic drive pins Pin I/O Name COM1 to O COM24 COMS1, O COMS2 SEG1 to O SEG60 SEGS1, 2 O 4, 5 Description No.
S1D12205 Series 6. FUNCTION DESCRIPTION The S1D12205 Series can transfer data via the 4- or 8-bit data bus or via the serial data input (SI). The parallel or serial data input can be selected by setting the PS pin to HIGH or LOW (see Table 1). MPU Interfaces Interface type selection Table 1 CS CS CS A0 A0 A0 WR WR HIGH, LOW SI – SI The S1D12205 Series has the C86 pin for MPU selection.
S1D12205 Series CS SI D7 SCL 1 D6 2 D5 D4 3 D3 4 5 D2 D1 6 7 A0 D0 8 D7 1 A0 Figure 1 Data bus signal identification The S1D12205 Series identifies the data bus based on a combination of A0, WR and E signals as defined on Table 3. Table 3 Common 68 Series 80 Series A0 E WR 1 1 0 0 1 0 Function Writes to the RAM and symbol register. Writes to the internal (commands) register. Chip Select The S1D12205 Series has an Chip Select pin (CS) to allow an MPU interface input only if CS=LOW.
Voltage regulator Power Save mode • Voltage regulator using the electronic control function Use the electronic control function and set the voltages appropriate to the LCD panel driving. When a 5-bit data is set in the electronic control register, one of 32-state voltages can be set for LCD driving. Before using the electronic control function, turn ON the power circuit by issuing the power control command. The following explains how to calculate the voltages using the electronic control function.
S1D12205 Series Reset Circuit When the RES input is made active, this LSI is initialized.
S1D12205 Series 7. COMMAND Table 4 lists the supported commands. The S1D12205 Series identifies a data bus by a combination of A0, WR and E signals. It features HIGH-speed processing as the commands are analyzed and executed in the internal timing only.
S1D12205 Series The character on the 3rd line will be displayed in double size on the second and third lines by setting DC=1. (2) N=1 (1/18 duty) DC=0 DC=1 (5) System Reset The System Reset command sets the display direction, the display line, and the use or no use of CGRAM. This command must first be executed after the power-on or reset. A0 WR D7 D0 COM1– ... 1st line 0 0 0 1 1 ...
S1D12205 Series SEG60 ... SEG1 (6) RAM Address Setup The RAM Address Setup command sets an address into the Address counter to write data into DDRAM, CGRAM and Symbol register. When the cursor display is ON, the cursor is located at a position corresponding to the DDRAM address set by this command. COM1 ..... A0 WR D7 COM16 (N=1) COM24 (N=0) 0 0 D0 1 ADDRESS ✽ : Don’t Care 1 The 00H to 7FH address length can be set. To write data in the RAM, set the data write address by this command.
3–16 0 0 1 0 0 (5) System Reset (6) RAM Address Setup (7) RAM Write (8) NOP (9) Test Mode 0 (3) Power Save 0 0 (2) Display On/Off Control (4) Power Control 0 EPSON 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 A0 WR D7 (1) Cursor Home Command Table 4 S1D12205 Series command list 0 0 1 1 1 0 0 D6 0 0 1 0 0 1 0 N S2 0 ✽ ✽ 0 B ✽ ✽ C D2 D3 0 0 0 ✽ 0 ✽ DATA ADDRESS 0 1 0 1 1 D4 Code D5 ✽ 0 S1 0 0 DC ✽ D1 ✽ 0 CG P PS D ✽ D0 This is an I
S1D12205 Series 8. BUILT-IN MEMORIES Character Generator ROM (CGROM) The S1D12205 Series contains up to 126 types of CGROMs. Each character has a 5×8-dot structure. character Tables 5 to 8 defines the S1D12205D codes. Four characters (00H to 03H) of character codes are used for the CGROM or CGRAM by the System Setup command. * S1D12205 Series **** The S1D12205’s CGROM is a mask ROM and it can be used as a custom CGROM. Consult to our sales agency for details.
S1D12205 Series Table 5 S1D12205D10B * Lower 4 Bit of Code 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 Higher 4 Bit of Cord 6 7 8 9 A B C D E F 3–18 EPSON Rev. 1.
S1D12205 Series Table 6 S1D12205D11B * Lower 4 Bit of Code 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 S1D12205 Series 1 2 3 4 5 Higher 4 Bit of Cord 6 7 8 9 A B C D E F Rev. 1.
S1D12205 Series Table 7 S1D12205D16B * Lower 4 Bit of Code 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 Higher 4 Bit of Cord 6 7 8 9 A B C D E F 3–20 EPSON Rev. 1.
S1D12205 Series Character Generator RAM (CGRAM) store up to four 5×8-dot character patterns. The following provides the relationship between CGRAM character patterns and CGRAM addresses and character codes.
S1D12205 Series Symbol Register The S1D12205 Series has a built-in Symbol register to allow separate symbol setup on the display panel. The Symbol register has the 120-bit storage capacity, and it can display 120 symbols. Also, the S1D12205 Series contains a Blink register for every 5-dot blinking. 13 The following provides the relationship between the Symbol register display patterns, RAM addresses and write data. 12 1 13 1 ..... 5 56 ..... 60 61 ..... 65 116 ..... 120 2 5 .....
S1D12205 Series Static Icon RAM The S1D12205 Series has a built-in Static Icon RAM to display a static icon separately from the dynamic icon. The Static Icon RAM has the 20-bit storage capacity, and it can display 10 icons. The following provides the relationship between the static icon functions and the static icon, RAM address and write data.
S1D12205 Series Electronic Control RAM (Register) The S1D12205 SERIES has the electronic control functions to control LCD drive voltages and to adjust the LCD display density. One of 32-state LCD voltages can be selected when the 5-bit data is written in the Electronic Control RAM. The following provides the relationship between the RAM address and write data by electronic control setup.
S1D12205 Series 9. ABSOLUTE MAXIMUM RATINGS Symbol VSS V5 V1, V2, V3, V4 VIN VO Topr Tstr (VCC) VDD Rating –0.6 to +0.3 –7.0 to +0.3 V5 to +0.3 VSS–0.3 to +0.3 VSS–0.3 to +0.3 –30 to +85 –55 to +100 –65 to +125 Unit V V V V V °C S1D12205 Series Item Power voltage (1) Power voltage (2) Power voltage (3) Input voltage Output voltage Operating temperature TCP Storage temperature Bare chip °C VDD (GND) VSS V5 Notes: 1. All voltages are referenced to VDD=0 V. 2.
S1D12205 Series 10. DC CHARACTERISTICS (VSS = –3.6 to –1.7 V, Ta = –30 to +85°C unless otherwise noted.) Item Power voltage (1) Power voltage (2) Symbol Operable Data hold voltage VSS Min. Typ. Max. 1/4 bias Conditions –3.6 –3.0 –1.7 1/5 bias –3.6 –3.0 –2.7 –3.6 –1.5 Unit Pin V VSS Operable V5 –6.0 –3.0 V V5 Operable V1, V2 0.5 × V5 VDD V V1, V2 Operable V3, V4 V5 0.5 × V5 V V3, V4 HIGH input voltage VIHC 0.2 × VSS VDD V *2 LOWinput voltage VILC VSS 0.
S1D12205 Series S1D12205 Series *1 Although the wide operating character range is guaranteed, a quick and excessive voltage variation may not be guaranteed during access by the MPU. The low-voltage data hold characteristics are valid during Sleep mode. No access by the MPU is allowed during this time. *2 D0 to D5, D6 (SCL), D7 (SI), A0, RES, CS, WR (E), PS, IF, C86 *3 The resistance if a 0.1-volt voltage is supplied between the SEGn, SEGSn, COMn or COMSn output pin and each power pin (V1, V2, V3 or V4).
S1D12205 Series 11. TIMING CHARACTERISTICS (1) MPU bus write timing (80 series) A0 tAC8 tAH8 CS tCYC8 tAW8 tCCL WR tCCH tDS8 tDH8 D0 to D7 (Ta = –30 to +85°C, VSS = –3.6V to –1.7V) Item Address setup time Address hold time CS setup time Signal Symbol A0 CS System cycle time Write LOW pulse width (Write) WR Write HIGH pulse width (Write) Data setup time Data hold time D0 to D7 Conditions Min. tAW8 tAH8 tAC8 tCYC8 tCCL tCCH tDS8 tDH8 All timing must be based on 20% and 80% of VSS.
S1D12205 Series (2) MPU bus write timing (68 series) A0 tAH6 tAC6 CS tCYC6 S1D12205 Series tEWH tEWL E tDS6 tDH6 tAW6 D0 to D7 (Ta = –30 to +85°C, VSS = –3.6V to –1.7V) Item Address setup time Address hold time CS setup time Signal Symbol A0 CS System cycle time Enable LOW pulse width (Write) WR Enable HIGH pulse width (Write) Data setup time Data hold time D0 to D7 Conditions Min. tAW6 tAH6 tAC6 tCYC6 tEWL tEWH tDS6 tDH6 All timing must be based on 20% and 80% of VSS.
S1D12205 Series (3) Serial interface tCSS tCSH CS tSAS tSAH A0 tSCYC tSLW SCL tSHW tSDS tSDH SI (Ta = –30 to +85°C, VSS = –3.6V to –1.7V) Item System clock cycle SCL HIGH pulse width SCL LOW pulse width Signal Symbol tSCYC tSHW tSLW tSAS tSAH tSDS tSDH tCSS tCSH SCL Address setup time Address hold time A0 Data setup time Data hold time SI CS-to-SCL time CS Conditions Min. All timing must be based on 20% and 80% of VSS. Max.
S1D12205 Series 12. MPU INTERFACES (REFERENCE) The S1D12205 Series can be connected to the 80-series or 68-series MPU. Also, it can operate with a less number of signal lines via the serial interface. If the MPU buses and ports are set to HIGH impedance for a certain time due to RESET, the RESET signal must be entered in the S1D12205 Series after the S1D12205’s inputs have been determined.
S1D12205 Series 13. LCD CELL INTERFACE 12 columns by 3 lines, 5×8 dots + Symbols S1D12205 LCD panel 1 ................. 12 columns Static Icon COMSA .. SEGSA SEGSJ Symbols Symbols COMS1 Signals Signals COMS2 COM1 2 3 4 5 6 7 8 COM9 10 11 12 13 14 15 16 COM17 18 19 20 21 22 23 24 Character SEGS1 SEGS2 ... SEG1 2 3 4 5 SEG60 SEGS4 SEGS5 3–32 EPSON Rev. 1.
S1D12205 Series 12 columns by 2 lines (N=1), 5×8 dots + Symbols S1D12205 LCD panel 1 • • • • • • • • • • • • • 12 columns Static icon COMSA SEGSA .. SEGSJ COMS1 Signal S1D12205 Series Symbol Signal COMS2 COM1 2 3 4 5 6 7 8 COM9 10 11 12 13 14 15 16 COM17 18 19 20 21 22 23 24 Character SEGS1 SEGS2 SEG1 2 3 4 5 ... SEG60 SEGS4 SEGS5 Rev. 1.
S1D12205 Series 14. LCD DRIVE WAVEFORMS (B WAVEFORMS) COM 1 COM 2 COM 3 COM 4 COM 5 COM 6 COM 7 COM 8 VDD V1 V2 V3 V4 V5 COM 1 VDD V1 V2 V3 V4 V5 COM 2 COM 9 COM 10 COM 11 COM 12 COM 13 COM 14 COM 15 COM 16 SEG 1 SEG 2 SEG 3 SEG 4 SEG 5 VDD V1 V2 V3 V4 V5 COM 3 VDD V1 V2 V3 V4 V5 SEG 1 VDD V1 V2 V3 V4 V5 SEG 2 V5 V4 V3 V2 V1 VDD –V1 –V2 –V3 –V4 –V5 COM1 - SEG 1 V5 V4 V3 V2 V1 VDD –V1 –V2 –V3 –V4 –V5 COM1 - SEG 2 3–34 EPSON Rev. 1.
S1D12205 Series 15. EXAMPLE OF INSTRUCTION SETUP (REFERENCE) Initialization VDD-VSS power on Power stable Command status - Static display control - Display on/off control - Power save - Power supply control - System setup - Electronic volume - Static icon Others are undefined. S1D12205 Series Reset input - off - off - off - off - 3-digit display, CGRAM unused. normal display - (0, 0, 0, 0, 0) - (0, 0, 0, 0, 0) Wait for 10 microseconds or more.
S1D12205 Series Display Mode End of initialization RAM address set input RAM (data) write input Display the written contents. Standby Mode (1) Setting the standby mode End of initialization Normal operation - Power save is cleared and oscillating circuit turns on. <1> Display on/off control command input - D off (display) <2> Power save command input - PS on (power save) O on (oscillation) <3> Power supply control command input - P off Starts the standby mode. Displays only the static icon.
S1D12205 Series Sleep Mode (1) Setting the Sleep mode. End of initialization Normal operation (Power save is cleared and oscillating circuit turns on.) (See Note 3) (See Note 3) S1D12205 Series <1> Display on/off control command input - D off (display) <2> Power save icon control - Address 20H, 22H Data (0, 0, 0, 0, 0) - Address 21H, 23H Data (0, 0, 0, 0, 0) <3> Power save command input - PS on (power save) O off (oscillating) <4> Power supply control command input - P off Starts the sleep mode.
S1D12205 Series 16. OPTION LIST The S1D 12205 Series has the following options. Options are available exclusively for users. Please contact our Sales Department for information. • The following shows how to define the name of the product compatible with options: Example: S1D12205D B* ** ↑ Option code Specification of character generator ROM (CGROM) The S1D12205 Series incorporates a characters generator ROM consisting of up to 256 types of characters, with each character size featuring 5 × 7 (8) dots.
EPSON S1D12200 S1D12205 Rev. 1.1 S1D12400 *** System set • S1 = 0 • S2 = 0 System set • CS = 0 • SS = 0 System set • CS = 0 • SS = 1 (SEG-reversed) However, the input of DDRAM address of "S1D12***" from the first digit of the first line shall be 3FH and 3EH, in this order (as it is reversed in the unit of character). System set • S=0 System set • S1 = 0 • S2 = 1 (Horizontally-reversed) • Unable to correspond with commands. • Only able to correspond with custom fonts.
S1D12205 Series 17. CAUTIONS The following points should be noted when this Development Specification is used: 1. This Development Specification is subject to modification for improvement without prior notice. 2. This Development Specification is not intended to guarantee enforcement of industrial property and other rights, or to grant license for the use of this product. Examples of applications mentioned in this Development Specification are given for effective understanding of the product.
S1D12300 Series Rev. 1.
Contents 1. DESCRIPTION ............................................................................................................................................. 4–1 2. FEATURES .................................................................................................................................................. 4–1 3. BLOCK DIAGRAM ...................................................................................................................................... 4–3 4. PAD ................
1. DESCRIPTION The S1D12300 Series is a dot matrix LCD controller driver for character display, and can display a maximum of 48 characters, 4 user-defined characters, and a maximum of 64 symbols by means of 4-bit, 8-bit or serial data sent from a microcomputer. A built-in character generator ROM is prepared for 256 character types, and each character font consists of 5 × 7 dots. A user-defined character RAM for four characters of 5 × 7 dots are incorporated, and a symbol register is also incorporated.
S1D12300 Series S1D12300 Series Chip Specifications Product name Duty S1D12300D11B * 1/30 S1D12300D16B 1/30 * S1D12300D16E 1/30 * S1D12300D19B 1/30 * S1D12300D27E 1/30 * S1D12301D10B * 1/23 S1D12301D11E 1/23 * S1D12301D19B 1/23 * S1D12302D10B * 1/16 S1D12302D11B 1/16 * S1D12302D16B 1/16 * S1D12302D22B 1/16 * S1D12303D10E S1D12303D11B S1D12303D16B S1D12303D16E S1D12303D22B S1D12303D27A S1D12303D02E S1D12303D03E * 1/16 * 1/16 * 1/16 * 1/16 * 1/16 * 1/16 * 1/16 * 1/16 No. of digits No.
Rev. 1.9 EPSON A0 SEG1~60 SEGS1~6 SEG driving circuit V1 V2 V3 Power circuit Timing generating circuit S1D12300 Series COM1~28 COMS1~3 COM driving circuit Refresh address counter P/S Command decoder Address counter WR (E) Input buffer CS CG ROM Cursor control Oscillator RES IF RAM DD RAM CG RAM D7 (SI) D6 (SCL) D5 D4 D3 D2 D1 D0 V4 V5 VOUT VR CAP2– CAP2+ CAP1– CAP1+ VS1 S1D12300 Series 3.
S1D12300 Series 4. PAD Pad layout 173 86 174 85 (0,0) 193 69 1 58 S1D12300D S1D12301D S1D12302D S1D12303D **** **** **** **** ↑ 1/30 duty 1/23 duty 1/16 duty 1/16 duty 12 columns + 1 signal column 12 columns + 1 signal column 12 columns + 1 signal column 16 columns #1 Column for CG ROM pattern change Chip size: Pad pitch: Chip thickness: 10.23 × 3.11 mm 110 µm (Min.
S1D12300 Series PAD No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 Rev. 1.
S1D12300 Series PAD No.
S1D12300 Series No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 Rev. 1.
S1D12300 Series PAD No.
S1D12300 Series No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 Rev. 1.
S1D12300 Series PAD No.
S1D12300 Series No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 Rev. 1.
S1D12300 Series PAD No.
S1D12300 Series 5. PIN DESCRIPTION Power Supply Pins VS1 I/O Description Power supply Logic + power pin. Also used as MPU power pin VCC. Power supply Logic – power pin. Connected to the system GND. Power supply Multi-level power supply for liquid crystal drive. The voltage determined in the liquid crystal cell is resistancedivided or impedance-converted by operational amplifier, and the resultant voltage is applied.
S1D12300 Series Pins for System Bus Connection Pin name D7 (SI) D6 (SCL) D5 to D0 I/O I Description No. of Pins 8-bit input data bus. These pins are connected to a 8-bit or 16-bit 8 standard MPU data bus. When P/S = LOW, the D7 and D6 pins are operated as a serial data input and a serial clock input respectively. P/S LOW HIGH A0 I RES I CS I WR I (E) P/S I 4–14 I D6 D5 to D0 SCL — D6 D5 to D0 CS CS CS A0 A0 A0 When P/S = LOW, be sure to fix D5 to D0 to HIGH or LOW.
S1D12300 Series Liquid Crystal Drive Circuit Signals S1D12300, S1D12301, S1D12302 Pin name COM1 to COM28 I/O Description No. of Pins Common signal output pin (for characters) 28 COMS1 to CMOS3 O Common signal output pin (except for characters) CMOS1: Common output for static drive. In the standby mode only, a VSS amplitude is output.
S1D12300 Series 6. FUNCTIONAL DESCRIPTION MPU Interface Selection of interface type In the S1D12300 Series, data transfer is performed through a 8-bit or 4-bit data bus or a serial data input (SI). By selecting HIGH or LOW as P/S pin polarity, a parallel data input or a serial data input can be selected as shown in Table 1.
S1D12300 Series CS D7 S1 SCL 1 D6 2 D5 3 D4 4 D3 5 D2 6 D1 7 D0 8 D7 9 A0 Fig. 1 Identification of data bus signals The S1D12300 series identifies data bus signals, as shown in Table 3, by combinations of A0 and WR (E). Common A0 1 0 68 series E 1 1 80 series WR 0 0 S1D12300 Series Table 3 Function Writing to RAM and symbol register Writing to internal register (command) Chip select The S1D12300 series has a chip select pin (CS). Only when CS = LOW, MPU interfacing is enabled.
S1D12300 Series Triple boosting circuit When a capacitor is connected between CAP1+ and CAP1-, between CAP2+ and CAP2-, and between VSS pin and VOUT pin respectively, the potential between the VDD pin and VSS pin is boosted triple and output to the VOUT pin. In case of double boosting, remove the capacitor between CAP2+ and CAP2- in connection for triple boosting operation and strap between CAP2- and VOUT pin. Then, a double boosted output can be obtained from the VOUT pin (CAP2-).
S1D12300 Series ● Voltage Regulation Circuit Using Electronic Contrast Control Register The contrast control register controls the liquid crystal driving voltage (V5). This is accomplished by an electronic volume control register set command that adjusts the contrast of the liquid crystal display (see section 122). The commands provide 4-bits of voltage level data to the electronic volume control register.
S1D12300 Series Liquid crystal voltage generating circuit The V5 potential is resistance-divided inside the IC so that V1, V2, V3 and V4 potentials are generated for liquid crystal drive. Furthermore, the V1, V2, V3 and V4 are impedanceconverted by voltage follower and the then supplied to the liquid crystal drive circuit. The liquid crystal drive voltage is fixed to 1/5 bias.
When a built-in power supply is not used S1D123 VSS ecuted, the sleep mode is set. This mode permits reducing current consumption nearly to the static current value. 1. Liquid crystal display output COM1 ~ COM28, COMS2, COMS3 : VDD level SEG1 ~ SEG60, SEGS2 ~ SEGS6 : VDD level COMS1 ~ SEGS1 : VDD level 2. DD RAM, CG RAM and symbol register Written contents do not change and are stored regardless of whether the sleep mode is turned on or off. 3.
S1D12300 Series 7. COMMANDS (3) Table 4 shows a command list. In the S1D12300 Series, each data bus signal is identified by a combination of A0 and WR (E). Command interpretation and execution are performed by only internal timing. This permits high-speed processing. Note: Control the symbols that are driven by COMS1 and SEGS1, by the Static Display Control command.
S1D12300 Series Power Save This command is used to control the oscillating circuit and set and reset the standby mode or sleep mode. (7) Electronic Volume Register Set This command controls the liquid crystal driving voltage V5 output from the voltage regulating circuit of the built-in liquid crystal power supply, thereby adjusting the gradation of liquid crystal display. When data is set in the 4-bit register, the liquid crystal driving voltage can take one of 16 voltage states.
S1D12300 Series RAM Map (S1D12300, S1D12301, S1D12302) 00H 10H 20H 30H 40H 50H 60H 70H 1 2 3 4 5 C G R A M (0 0 H) C G R A M (0 2 H) 6 7 8 – – Unused DDRAM line 1 DDRAM line 2 DDRAM line 3 DDRAM line 4 Symbol register 9 A B C D C G R A M (0 1 H) C G R A M (0 3 H) For signals E F – – Unused " " " " ------------- 0 – : Unused For signals : Output from SEGS2 to SEGS6.
S1D12300 Series Table 4 S1D12300 Series Command List Code Function A0 WR D7 D6 D5 D4 D3 D2 D1 D0 (1) Cursor Home 0 0 0 0 0 1 * * (2) Static Display Control 0 0 0 0 1 0 * * SD1 Sets the display mode of static display symbol SD0 SD1, SD0 = 0, 0 (display OFF), 0, 1 (1 - 2 Hz blink), 1, 0 ( 3 4 Hz blink), 1, 1 (all display ON) (3) Display ON/OFF 0 Control 0 0 0 1 1 C B DC D Sets cursor ON/OFF (C), cursor blink ON//OFF (B), double cursor ON/OFF (DC) and display ON/OFF (D).
S1D12300 Series 8. CHARACTER GENERATOR Character Generator ROM (CG ROM) The CG ROM of the S1D12300 Series is a mask ROM and compatible with the user-dedicated CG ROM. Please ask us for further information of it. The S1D12300 Series is provided with a character generator ROM consisting of a up to 256-type characters. Each character size is 5 × 7 dots. Regarding changed CG ROM, it is defined in product name as follows: Table 5 shows a character code table of the S1D12300 Series.
S1D12300 Series S1D123**D10** Table 5 Lower 4 Bit of Code 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 S1D12300 Series 3 4 5 Higher 4 Bit of Cord 6 7 8 9 A B C D E F Rev. 1.
S1D12300 Series S1D123**D11** Lower 4 Bit of Code 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 Higher 4 Bit of Cord 6 7 8 9 A B C D E F 4–28 EPSON Rev. 1.
S1D12300 Series S1D123**D16** Lower 4 Bit of Code 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 S1D12300 Series 3 4 5 Higher 4 Bit of Cord 6 7 8 9 A B C D E F Rev. 1.
S1D12300 Series Character Generator RAM (CG RAM) The S1D12300 Series is provided with a CG RAM that permits user-programming character patterns so that they can be displayed with a high degree of freedom for signal display. Before using the CG RAM, select the use of CG RAM by the System Set command. The capacity of the CG RAM is 140 bits and arbitrary patterns of 4 types consisting of 5 × 7 dots can be registered. The relationship among CG RAM patterns, CG RAM addresses, and character codes is shown below.
S1D12300 Series Symbol Register The S1D12300 Series is provided with a symbol register that permits displaying each symbol so that symbol display may be performed on the screen. The capacity of the symbol register is 64 bits. In case of 12 digits, 48 symbols can be displayed. In case of 16 digits, 64 symbols can be displayed. The relationship among symbol register display patterns, RAM addresses and write data is shown below.
S1D12300 Series (2) S1D12303 1 2 Symbol 1 2 E 3 4 31 32 35 36 63 64 COMS2 COMS3 33 34 SEG2 SEG4 RAM address 70H to 7FH Notes 4–32 SEG7 SEG9 SEG77 SEG79 Symbol Bits D7 D6 D5 D4 D3 D2 0 * * * 33 1 34 1 * * * 35 3 36 : : E * * * 61 29 62 F * * * 63 31 64 D1 D0 Bit 2 * 1: Display 4 * 0: Not display 30 32 * * 1: If the symbol segment size is 1.5 times or more greater than the other dots, it is recommended to be divided into COMS2 and COMS3 and driven separately.
S1D12300 Series Item Symbol Standard value Unit Power supply voltage (1) VSS –6.0 to +0.3 V Power supply voltage (2) V5 –12.0 to +0.3 V Power supply voltage (3) V1, V2, V3, V4 V5 to +0.3 V Input voltage VIN VSS–0.3 to +0.3 V Output voltage VO VSS–0.3 to +0.3 V Operating temperature Topr –30 to +85 °C –55 to +100 °C Storage temperature TCP Bare chip Tstr (VCC) VDD –65 to +125 S1D12300 Series 9. ABSOLUTE MAXIMUM RATINGS VDD (GND) VSS V5 Notes: 1.
S1D12300 Series 10. DC CHARACTERISTICS VDD = 0 V, VSS = –3.6 V to –2.4 V, Ta = –30 to 85°C unless otherwise specified. Item Symbol Condition min Recommended –3.6 operation VSS Operable –5.5 Recommended –8.0 operation V5 Operable –11.0 Operable V1, V2 0.6×V5 Operable V3, V4 VDD HIGH-level input voltage VIHC 0.2×VSS LOW-level input voltage VILC VSS Input leakage current ILI VIN = VDD or VSS –1.0 LC driver ON resistance RON Ta=25°C V5=–7.0V ∆V=0.
S1D12300 Series *11: The fOSC frequency of the oscillator circuit for internal circuit drive may differ from the fBST boosting clock on some models. The following provides the relationship between the fOSC frequency, fBST boosting clock, and fFR frame frequency. fOSC = (No. of digits) × (1/Duty) × fFR fBST = (1/2) × (1/No. of digits) × fOSC Example: The S1D12300 has 13 digits of display and 1/30 duty. fOSC = 13 × 30 × 100 = 39 kHz fBST = (1/2) × (1/13) × 39 K = 1.
S1D12300 Series 11. TIMING CHARACTERISTICS (1) System Bus Write Characteristic I (80 series MPU) tAH8 A0, CS tAW8 tCYC8 tCC WR tDS8 tDH8 D0 to D7 Item Address hold time Address setup time System cycle time Control pulse width (Write) Data setup time Data hold time [VSS = –3.6 V to –2.4 V, Ta = –30 to 85°C unless otherwise specified] Measuring Signal Symbol Min. Max. Unit condition A0, CS t AH8 30 ns t AW8 60 ns WR t CYC8 VSS = –3.0 500 ns –2.7 550 –2.4 650 t CC VSS = –3.0 100 ns –2.7 120 –2.
S1D12300 Series (2) System Bus Write Characteristic II (68 series MPU) tCYC6 E tAW6 tEW tAH6 tDS6 tDH6 D0 to D7 Item System cycle time Address setup time Address hold time Data setup time Data hold time Enable pulse width [VSS = –3.6 V to –2.4 V, Ta = –30 to 85°C unless otherwise specified] Measuring Signal Symbol Min. Max. Unit condition A0, CS t CYC6 VSS = –3.0 500 ns –2.7 550 –2.4 650 t AW6 60 t AH6 30 ns D0 to D7 t DS6 100 ns t DH6 50 ns E t EW VSS = –3.0 100 ns –2.7 120 –2.
S1D12300 Series (3) Serial Interface tCSS tCSH CS tSAS tSAH A0 tSCYC tSLW SCL tSHW tSDS tSDH SI Item System clock cycle SCL HIGH pulse width SCL LOW pulse width Address setup time Address hold time Data setup time Data hold time CS-SCL time Signal Symbol SCL tSCYC A0 SI CS tSHW tSLW tSAS tSAH tSDS tSDH tCSS tCSH [VSS = –3.6 V to –2.4 V, Ta = –30 to 85°C] Measuring Min. Max. Unit condition VSS = –3.0 700 ns –2.7 800 ns –2.4 1000 ns 300 ns 300 ns 50 ns VSS = –3.0 350 ns –2.7 400 ns –2.
S1D12300 Series 12. MPU INTERFACE (REFERENCE EXAMPLES) The S1D12300 Series can be connected to the 80 series MPU and 68 series MPU. When an serial interface is used, the S1D12300 Series can be operated by less signal lines.
S1D12300 Series 13. INTERFACE TO LCD CELLS (REFERENCE) 12 columns by 2 lines, 5 × 7-dot matrix segments and symbols 1 • • • • • • • • • • • • • • 12 S1D12302 COMS1 SEGS1 COMS2 COMS3 COM1 2 3 4 5 6 7 COM8 9 10 11 12 13 14 SEGS2 3 4 SEG1 2 3 4 5 : : SEG60 SEGS4 5 6 ■ System Setup 4–40 N2 0 N1 0 EPSON Rev. 1.
S1D12300 Series 14. LCD DRIVE WAVEFORMS (B WAVEFORMS) COM 8 COM 9 COM 10 COM 11 COM 12 COM 13 COM 14 VDD V1 V2 V3 V4 V5 COM 1 VDD V1 V2 V3 V4 V5 COM 2 VDD V1 V2 V3 V4 V5 COM 3 SEG 1 SEG 2 SEG 3 SEG 4 SEG 5 VDD V1 V2 V3 V4 V5 SEG 1 VDD V1 V2 V3 V4 V5 SEG 2 V5 V4 V3 V2 V1 VDD -V1 -V2 -V3 -V4 -V5 COMO -SEG 1 V5 V4 V3 V2 V1 VDD -V1 -V2 -V3 -V4 -V5 COMO -SEG 2 Rev. 1.
S1D12300 Series 15. INSTRUCTION SETUP EXAMPLE (REFERENCE) (1) (2) Initial setup Display mode VDD-VSS power ON End of initialization Power regulation Input of RAM address setup command Input of reset signal Input of RAM (data) write command Command status • Static display control • Display on/off control • Power save • Power control • System reset • Others are undefined.
S1D12300 Series (3-1) Selecting the Standby mode (3-2) Releasing the Standby mode End of initialization Standby mode Normal operation (Power Save is released and oscillator circuit is turned ON.
S1D12304/12305 Series Rev. 2.
Contents 1.DESCRIPTION ............................................................................................................................................... 5–1 2.FEATURES ..................................................................................................................................................... 5–1 3.BLOCK DIAGRAM ......................................................................................................................................... 5–2 4.PAD ............
1. DESCRIPTION The S1D12304/12305 Series is a dot matrix LCD controller driver for character display, and can display a maximum of 48 characters, 4 user-defined characters, and a maxi-mum of 48 symbols by means of 4-bit, 8-bit or serial data sent from a microcomputer. A built-in character generator ROM is prepared for 256 character types, and each character font consists of 5 × 7 dots.
5–2 EPSON A0 Input buffer SEG1 to 60 SEGS2, 6 SEG driving circuit COM1 to 28 COMS2, 3 COM driving circuit Refresh address counter P/S Command decoder Address counter WR (E) CG ROM CS RAM Cursor control V1 V2 Oscillator RES IF D7 (SI) D6 (SCL) D5 D4 D3 D2 D1 D0 Power circuit V3 V4 V5 VOUT VR CAP2– CAP2+ CAP1– CAP1+ VS1 S1D12304/12305 Series 3. BLOCK DIAGRAM Timing generating circuit MPU interface Rev. 2.
S1D12304/12305 Series 4. PAD Pad Layout 109 33 · · · · · · · · · · · 110 32 ····· (0, 0) ·· Y X 22 127 · · · · · · 1 2 3 17 14 15 16 : NC (Make it floating.) S1D12304D S1D12305D **** **** ↑ 1/30 duty 1/16 duty #1 Column for CG ROM pattern change Chip size: Pad pitch: Chip thickness: 1) A1 pad specification Pad size: Rev. 2.4 10.23 × 3.11 mm 126 µm (Min.
S1D12304/12305 Series Pad Center Coordinate PAD No.
S1D12304/12305 Series No. 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 Name COM21 COM20 COM19 COM18 COM17 COM16 COM15 COMS3 A0 WR CS D7 D6 D5 D4 D3 D2 D1 D0 COORDINATES X Y –4933 1405 –4964 1094 966 839 712 584 457 330 202 75 –52 –180 –307 –434 –562 –689 –816 –943 –1071 S1D12304/12305 Series PAD Note 1 : Set the pin (NC) to the floating state. 2 : Be sure to connect the pins VSSL and VSSR outside. They are called VSS in the following text descriptions. Rev. 2.
S1D12304/12305 Series PAD No.
S1D12304/12305 Series No. 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 Name COM14 COM13 COM12 COM11 COM10 COM9 COM8 COMS3 A0 WR CS D7 D6 D5 D4 D3 D2 D1 D0 COORDINATES X Y –4933 1405 –4964 1094 966 839 712 584 457 330 202 75 –52 –180 –307 –434 –562 –689 –816 –943 –1071 S1D12304/12305 Series PAD Note 1 : Set the pin (NC) to the floating state. 2 : Be sure to connect the pins VSSL and VSSR outside. They are called VSS in the following text descriptions. Rev. 2.
S1D12304/12305 Series 5. PIN DESCRIPTION Power Supply Pins Pin name VDD VSS V0, V 1 V2, V 3 V4, V 5 VS1 I/O Description Power supply Logic + power pin. Also used as MPU power pin VCC. Power supply Logic – power pin. Connected to the system GND. Power supply Multi-level power supply for liquid crystal drive. The voltage determined in the liquid crystal cell is resistancedivided or impedance-converted by operational amplifier, and the resultant voltage is applied.
S1D12304/12305 Series Pins for System Bus Connection I/O I Description No. of Pins 8-bit input data bus. These pins are connected to a 8-bit or 16-bit 8 standard MPU data bus. When P/S = LOW, the D7 and D6 pins are operated as a serial data input and a serial clock input respectively. P/S LOW HIGH A0 I RES I CS I WR (E) I P/S I Rev. 2.4 I D6 SCL D6 D5 to D0 — D5 to D0 CS CS CS A0 A0 A0 When P/S = LOW, be sure to fix D5 to D0 to HIGH or LOW.
S1D12304/12305 Series Liquid Crystal Drive Circuit Signals S1D12304 Pin name COM1 to COM28 COMS2, CMOS3 SEG1 to SEG60 SEGS2, SEGS6 S1D12305 Pin name COM1 to COM14 COMS2, CMOS3 SEG2 to SEG60 SEGS2, SEGS6 5–10 I/O Description No.
S1D12304/12305 Series 6. FUNCTIONAL DESCRIPTION MPU Interface Selection of interface type In the S1D12304/12305, data transfer is performed through a 8-bit or 4-bit data bus or a serial data input (SI). By selecting HIGH or LOW as P/S pin polarity, a parallel data input or a serial data input can be selected as shown in Table 1.
S1D12304/12305 Series CS S1 SCL D7 1 D6 2 D5 3 D4 4 D3 5 D2 6 D1 7 D0 8 D7 9 A0 Fig. 1 Identification of data bus signals The S1D12304/12305 series identifies data bus signals, as shown in Table 3, by combinations of A0 and WR (E). Table 3 Common A0 1 0 68 series E 1 1 80 series WR 0 0 Function Writing to RAM and symbol register Writing to internal register (command) Chip select The S1D12304/12305 series has a chip select pin (CS). Only when CS = LOW, MPU interfacing is enabled.
S1D12304/12305 Series Triple boosting circuit When a capacitor is connected between CAP1+ and CAP1-, between CAP2+ and CAP2-, and between VSS pin and VOUT pin respectively, the potential between the VDD pin and VSS pin is boosted triple and output to the V OUT pin. In case of double boosting, remove the capacitor between CAP2+ and CAP2- in connection for triple boosting operation and strap between CAP2- and VOUT pin. Then, a double boosted output can be obtained from the VOUT pin (CAP2-).
S1D12304/12305 Series ● Voltage Regulation Circuit Using Electronic Contrast Control Register The contrast control register controls the liquid crystal driving voltage (V5). This is accomplished by an electronic volume control register set command that adjusts the contrast of the liquid crystal display (see section 122). The commands provide 4-bits of voltage level data to the electronic volume control register.
S1D12304/12305 Series Liquid crystal voltage generating circuit The V5 potential is resistance-divided inside the IC so that V1, V2, V3 and V4 potentials are generated for liquid crystal drive. Furthermore, the V1 , V2 , V3 and V4 are impedanceconverted by voltage follower and the then supplied to the liquid crystal drive circuit. The liquid crystal drive voltage is fixed to 1/5 bias.
S1D12304/12305 Series Low Power Consumption Mode Reset Circuit The S1D12304/12305 Series is provided with the standby mode and sleep mode with the object of low power consumption when the unit is in the standby state. When the RES input goes active, this LSI enters the initialization status. ● Sleep Mode After the power circuit and oscillating circuit are turned off by command and the power save command is executed, the sleep mode is set.
S1D12304/12305 Series 7. COMMANDS B = 0 : Cursor blink OFF 1 : Cursor blink ON In the blink state, display characters in normal video and display characters in monochrome reverse video are displayed alternately. The repetition cycle of alternate display is about 1 second. Table 4 shows a command list. In the S1D12304/12305 Series, each data bus signal is identified by a combination of A0 and WR (E). Command interpretation and execution are performed by only internal timing.
S1D12304/12305 Series (4) Power Control This command is used to control the operation of the built-in power circuit. thereby adjusting the gradation of liquid crystal display. When data is set in the 4-bit register, the liquid crystal driving voltage can take one of 16 voltage states.
S1D12304/12305 Series (8) Data Write RAM Address Set A0 WR D7 D6 D5 D4 D3 D2 D1 D0 1 0 DATA 1 2 This command writes data into the DD RAM, CG RAM or symbol register. After this command is executed, the address counter is automatically incremented by 1. This permits writing data in succession. NO One Line Completed? YES Note: When executing instructions in succession, reserve a time exceeding tCYC and execute the next instruction.
S1D12304/12305 Series Table 4 S1D12304/S1D12305 Command List Command (1) Cursor Home Code A0 WR D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 1 (2) Display ON/OFF 0 0 Control 0 0 1 1 C B DC D (3) Power Save 0 0 0 1 0 0 * (4) Power Control 0 0 0 1 0 1 0 VC VF P (5) System Set 0 0 0 1 1 0 N2 N1 * CG Sets the use or non-use of CG RAM and display lines (N2, N1).
S1D12304/12305 Series 8. CHARACTER GENERATOR Character Generator ROM (CG ROM) The CG ROM of the S1D12304/12305 is a mask ROM and compatible with the use-dedicated CG ROM. Please ask us for further information of it. The S1D12304/12305 is provided with a character generator ROM consisting of a up to 256-type characters. Each character size is 5 × 7 dots. Regarding changed CG ROM, it is defined in product name as follows: Table 5 shows a character code table of the S1D123 D Series.
S1D12304/12305 Series Table 5 S1D123**D10** Lower 4 Bit of Code 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 Higher 4 Bit of Cord 6 7 8 9 A B C D E F 5–22 EPSON Rev. 2.
S1D12304/12305 Series S1D123**D11** Lower 4 Bit of Code 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 S1D12304/12305 Series 4 5 Higher 4 Bit of Cord 6 7 8 9 A B C D E F Rev. 2.
S1D12304/12305 Series S1D123**D16** Lower 4 Bit of Code 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 Higher 4 Bit of Cord 6 7 8 9 A B C D E F 5–24 EPSON Rev. 2.
S1D12304/12305 Series Character Generator RAM (CG RAM) The S1D12304/12035 Series is provided with a CG RAM that permits user-programming character patterns so that they can be displayed with a high degree of freedom for signal display. Before using the CG RAM, select the use of CG RAM by the System Set command. The capacity of the CG RAM is 140 bits and arbitrary patterns of 4 types consisting of 5 × 7 dots can be registered.
S1D12304/12305 Series Symbol Register The S1D12304/12305 provided with a symbol register that permits displaying each symbol so that symbol display may be performed on the screen. The capacity of the symbol register is 48 bits. In case of 48 symbols can be displayed. The relationship among symbol register display patterns, RAM addresses and write data is shown below.
S1D12304/12305 Series 9. ABSOLUTE MAXIMUM RATINGS Item Symbol Standard value Unit Power supply voltage (1) VSS –6.0 to +0.3 V Power supply voltage (2) V5 –16.0 to +0.3 V Power supply voltage (3) V1, V2, V 3, V4 V5 to +0.3 V Input voltage VIN VSS–0.3 to +0.3 V Output voltage VO VSS–0.3 to +0.3 V Operating temperature Topr –30 to +85 °C –55 to +100 °C Storage temperature TCP Bare chip Tstr (VCC) VDD –65 to +125 VDD V5 Notes: 1.
S1D12304/12305 Series 10. DC CHARACTERISTICS VDD = 0 V, VSS = –3.6 V to –2.4 V, Ta = –30 to 85°C unless otherwise specified. Item Symbol Condition Min. Recommended –3.6 operation VSS Operable –5.5 Recommended –8.0 operation V5 Operable –11.0 0.6×V5 Operable V1 , V2 Operable V3 , V4 VDD HIGH-level input voltage VIHC 0.2×VSS V SS Low-level input voltage VILC Input leakage current ILI VIN = VDD or VSS –1.0 V5=–7.0V LC driver ON resistance R ON Ta=25°C ∆V=0.
*6: This is applicable to the case where the built-in power circuit is OFF and the oscillating circuit is in operation in the standby mode. *10: When operating the boosting circuit, the power supply VSS must be used within the input voltage range. *7: Current consumption when data is always written by fcyc. The current consumption in the access state is almost proportional to the access frequency (fcyc). When no access is made, only IDD (I) occurs.
S1D12304/12305 Series 11. TIMING CHARACTERISTICS (1) System Bus Write Characteristic I (80 series MPU) tAH8 A0, CS tAW8 tCYC8 tCC WR tDS8 tDH8 D0 to D7 Item Address hold time Address setup time System cycle time Control pulse width (Write) Data setup time Data hold time [VSS = –3.6 V to –2.4 V, Ta = –30 to 85°C unless otherwise specified] Measuring Signal Symbol Min. Max. Unit condition 30 ns A0, CS t AH8 t AW8 60 ns VSS = –3.0 500 ns WR t CYC8 –2.7 550 –2.4 650 t CC VSS = –3.0 100 ns –2.
S1D12304/12305 Series (2) System Bus Write Characteristic II (68 series MPU) tCYC6 E tAW6 tEW tAH6 A0, CS tDH6 S1D12304/12305 Series tDS6 D0 to D7 Item System cycle time Address setup time Address hold time Data setup time Data hold time Enable pulse width [VSS = –3.6 V to –2.4 V, Ta = –30 to 85°C unless otherwise specified] Measuring Signal Symbol Min. Max. Unit condition VSS = –3.0 500 ns A0, CS t CYC6 –2.7 550 –2.4 650 60 t AW6 t AH6 30 ns 100 ns D0 to D7 t DS6 50 ns t DH6 E t EW VSS = –3.
S1D12304/12305 Series (3) Serial Interface tCSS tCSH CS tSAS tSAH A0 tSCYC tSLW SCL tSHW tSDS tSDH SI [VSS = –3.6 V to –2.4 V, Ta = –30 to 85°C] Measuring Item Signal Symbol Min. Max. Unit condition VSS = –3.0 700 ns System clock cycle SCL tSCYC –2.7 800 ns –2.4 1000 ns 300 ns SCL HIGH pulse width tSHW SCL LOW pulse width tSLW 300 ns 50 ns Address setup time A0 tSAS VSS = –3.0 350 ns Address hold time tSAH –2.7 400 ns –2.
S1D12304/12305 Series 12. MPU INTERFACE (REFERENCE EXAMPLES) The S1D12304/12305 Series can be connected to the 80 series MPU and 68 series MPU. When an serial interface is used, the S1D12304/12305 Series can be operated by less signal lines.
S1D12304/12305 Series 13. INTERFACE TO LCD CELLS (REFERENCE) 12 columns by 2 lines, 5×7-dot matrix segments and symbols 1 • • • • • • • • • • • • • • 12 S1D12305 COMS2 COMS3 COM1 2 3 4 5 6 7 COM8 9 10 11 12 13 14 SEGS2 SEG1 2 3 4 5 ·· ·· SEG60 SEGS4 ■ System Setup 5–34 N2 N1 0 0 EPSON Rev. 2.
S1D12304/12305 Series 14. LCD DRIVE WAVEFORMS (B WAVEFORMS) COM 8 COM 9 COM 10 COM 11 COM 12 COM 13 COM 14 SEG 1 SEG 2 SEG 3 SEG 4 SEG 5 VDD V1 V2 V3 V4 V5 COM 1 VDD V1 V2 V3 V4 V5 COM 2 VDD V1 V2 V3 V4 V5 COM 3 VDD V1 V2 V3 V4 V5 SEG 1 VDD V1 V2 V3 V4 V5 SEG 2 V5 V4 V3 V2 V1 VDD -V1 -V2 -V3 -V4 -V5 COMO -SEG 1 V5 V4 V3 V2 V1 VDD -V1 -V2 -V3 -V4 -V5 COMO -SEG 2 Rev. 2.
S1D12304/12305 Series 15. INSTRUCTION SETUP EXAMPLE (REFERENCE) (1) (2) Initial setup Display mode VDD-VSS power ON End of initialization Power regulation Input of RAM address setup command Input of reset signal Input of RAM (data) write command Command status • Static display control • Display on/off control • Power save • Power control • System reset • Others are undefined.
S1D12304/12305 Series (3-2) Releasing the Standby mode (3-1) Selecting the Standby mode End of initialization Standby mode Normal operation (Power Save is released and oscillator circuit is turned ON.
S1D12400 Series Rev. 2.
Contents 1. DESCRIPTION .............................................................................................................................................. 6-1 2. FEATURES ................................................................................................................................................... 6-1 3. BLOCK DIAGRAM ........................................................................................................................................ 6-2 4. PAD ............
1. DESCRIPTION The S1D12400 Series is a character display dot matrix LCD controller driver. This driver can display up to 64 characters and 6 user-defined characters, and up to 160 symbols according to the 4-bit, 8-bit or serial data which is sent from a microcomputer. The built-in character generator ROM is provided with up to 544 types of character fonts having a structure of 5 × 8 dots. Up to 256 types can be continuously called by register option selection.
S1D12400 Series D0 D1 D2 D3 D4 D5 D6 (SCL) D7 (SI) Input buffer 3.
S1D12400 Series 4. PAD Pad Layout 185 101 ........................ 186 100 S1D12400 Series ..... ..... D124*D** Y Die No. X (0, 0) 210 ........................ 1 2 3 4 5 75 6 74 : DUMMY PAD : PAD ******* ↑ ↑ S1D12400 Series S1D124 Digits for CGROM pattern change Number of display line 00: 4-line display 01: 3-line display 02: 2-line display Chip size: 8.70 × 2.80 mm Pad pitch: 90 µm (Min.
S1D12400 Series Pad Center Coordinate **** No.
PAD COORDINATES PAD X Y No. Name [BUMP TYPE] No.
S1D12400 Series No.
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S1D12400 Series No.
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S1D12400 Series 5. PIN DESCRIPTION Power Supply Pins Pin name I/O Description No. of Pins Substrate potential IC board is based on VDD potential. To lock the board potential with VDD. VDD Power supply Connected to the logic power supply. This is used in common with 6 the MPU power pin VCC. VSS Power supply 0 V power pin that is connected to system GND. 4 V0, V1 Power supply Multi-level power supply for liquid crystal drive.
S1D12400 Series System Bus Connecting Pins I/O I Description 8-bit input data bus which is connected to the 16-bit standard MPU data bus. Pin D7 and pin D6 function as a serial data input and a serial clock input at P/S = LOW, respectively. Pin P/S C86 IF Mode Serial I/F LOW HIGH or LOW — 68I/F 8bit HIGH HIGH HIGH 68I/F 4bit HIGH HIGH LOW 80I/F 8bit HIGH LOW HIGH 80I/F 4bit HIGH LOW LOW A0 I RES I C86 I CS I WR (E) I P/S I IF I CK I Rev. 2.
S1D12400 Series Liquid Crystal Drive Circuit Signals Dynamic Drive Pins [S1D12400] Pin name COM1 to COM32 COMS1, COMS2 SEG1 to SEG80 I/O Description No. of Pins O Common signal output pins (for characters) 32 O Common signal output pins (for others than characters) COMS1, COMS2: Symbol output command output 4 O Segment signal output pins (for characters) 80 Dynamic Drive Pins [S1D12401] Pin name COM1 to COM24 COMS1, COMS2 SEG1 to SEG80 I/O Description No.
S1D12400 Series 6. FUNCTION DESCRIPTION MPU Interfaces In the S1D12400 series, an MPU type, interface bit length and interface method can be selected depending on pins IF, P/ S and C86. Selection of MPU In the S1D12400 series, when parallel input is selected (P/S = HIGH), pin C86 has an MPU selecting function. When either HIGH or LOW is selected as the polarity of pin C86, the 80 series MPU or 68 series MPU can be selected as shown in Table 1.
S1D12400 Series Fig. 1 shows a timing chart of the serial interface. In case of the SCL signal, extreme care should be taken about terminal reflection and external noise due to a wiring length. Accordingly, it is recommended to make an operation check. It is also recommended to periodically refresh the each command write state to prevent a malfunction from being caused by noise. CS D7 (SI) D7 D6 (SCL) D6 1 2 D5 D4 3 4 D3 5 D2 6 D1 7 D0 8 D7 1 A0 Fig.
S1D12400 Series Boosting circuit The S1D12400 series is provided with a boosting circuit for triple boosting and double boosting for the potential between VDD and VSS2. For triple boosting, connect a capacitor between CAP1+ and CAP1–, between CAP2+ and CAP2–, and between VDD and VOUT, and the VDD - VSS2 potential is tripleboosted to the negative side and output to the VOUT pin.
S1D12400 Series Voltage regulating circuit The boosting voltage generated at VOUT is output as a liquid crystal drive voltage of V5 through the voltage regulating circuit. The S1D12400 series is provided with a high-precision constant-voltage source, a 32-step electronic volume function, and a V5 voltage regulating resistor. This permits constructing a high-precision voltage regulating circuit with a small quantity of parts.
S1D12400 Series [When using the V5 voltage regulating built-in resistor (Use of V5 voltage regulating built-in resistor is set by command.)] When the V5 voltage regulating built-in resistor and the electronic volume function are used, the liquid crystal supply voltage V5 can be controlled and the density of liquid crystal display can be controlled by commands only without adding any external resistor.
S1D12400 Series • Voltage regulating circuit using the electronic volume function When the electronic volume function is used, the liquid crystal drive voltage V5 can be controlled by the command to adjust the density of liquid crystal display. Regarding this method, set 5-bit data in the electronic volume register, and the liquid crystal drive voltage V5 can take one of 32 states of voltage value.
S1D12400 Series Liquid crystal voltage generating circuit The V5 potential is resistance-divided by the built-in resistor of the IC or external resistors Ra and Rb, generating potentials V1, V2, V3, and V4 required for liquid crystal drive. Furthermore, potentials V1, V2, V3, and V4 are impedance-converted by the voltage follower and supplied to the liquid crystal drive circuit. Regarding the liquid crystal drive voltage, the 1/5 bias or 1/4 bias can be selected by command.
S1D12400 Series 2 Using only the voltage regulating circuit and the voltage follower.
S1D12400 Series When driving a liquid crystal panel with heavy alternating or direct current load using an internal power supply circuit, we recommend that you connect an external resistance in order to stabilize the level of the internal voltage follower outputs V1, V2, V3 and V4.
S1D12400 Series 3. 4. 5. 6. 7. 8. 9. LB4 = 0 : DDRAM line 4 blink OFF LB3 = 0 : DDRAM line 3 blink OFF LB2 = 0 : DDRAM line 2 blink OFF LB1 = 0 : DDRAM line 1 blink OFF Vertical double-size display register DD4 = 0 : Line 4 is displayed in standard form. DD3 = 0 : Line 3 is displayed in standard form. DD2 = 0 : Line 2 is displayed in standard form. DD1 = 0 : Line 1 is displayed in standard form.
S1D12400 Series 7. COMMANDS Table 7 shows a command table. The S1D12400 series identifies each data/command by a combination of A0 and WR (E). An extended command can be selected by the RE bit in the command. Interpreting and executing commands are performed only at the internal timing. This permits high-speed processing.
S1D12400 Series Table 8 S1D12400 Series Command Table Command (1) Cursor Home/ Line Scroll Control (2) Line Blink/ Vertical Doublesize Display Control 6–24 RE 0 A0 0 WR 0 D7 0 D6 0 1 0 0 0 0 Code D5 D4 0 1 0 1 D3 * D2 * * * Function D0 * Moves the cursor to the home position. (Set the address to 30H.) LS1 LS0 Specifies the number of display scrolls in units of line.
Command (3) Display ON/OFF/ Extended Register ON/OFF Control (4) Power Save Control (5) Power Control (6) System Set Code Function RE A0 WR D7 D6 D5 D4 D3 D2 D1 D0 0/1 0 0 0 0 1 1 C B RE D Sets cursor ON/OFF, cursor blink ON/OFF (B), display ON/OFF (D), use/no-use of extended register (RE), and electronic volume LBS (RE).
S1D12400 Series Command (8) RAM Data Write (9) NOP (10) Test Mode Code Function RE A0 WR D7 D6 D5 D4 D3 D2 D1 D0 0/1 1 0 DATA Writes data into the DDRAM, CGRAM, symbol register RAM, static icon RAM or electronic volume RAM. This is determined by the address set instruction executed immediately before writing data. 0/1 0 0 0 0 0 0 0 0 0 0 A command for NON-OPERATION. This also serves as a test mode clear command, so it is recommended to input it periodically.
S1D12400 Series • When 2-line scroll has been performed upward at the 4-line display [Before line scroll] Display line 1 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH Display line 2 40H 41H 42H 43H 44H 45H 46H 47H 48H 49H 4AH 4BH 4CH 4DH 4EH 4FH Display line 3 50H 51H 52H 53H 54H 55H 56H 57H 58H 59H 5AH 5BH 5CH 5DH 5EH 5FH Display line 4 60H 61H 62H 63H 64H 65H 66H 67H 68H 69H 6AH 6BH 6CH 6DH 6EH 6FH 70H 71H 72H 73H 74H 75H 76H 77H 78H 79H 7AH 7BH 7CH 7DH 7EH 7FH XXH • • DDRAM a
S1D12400 Series • When 2-line scroll has been performed upward at the 2-line display [(LS1, LS2) = (1, 0)] [Before line scroll] Display line 1 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH Display line 2 40H 41H 42H 43H 44H 45H 46H 47H 48H 49H 4AH 4BH 4CH 4DH 4EH 4FH • • DDRAM address area • • Display area 50H 51H 52H 53H 54H 55H 56H 57H 58H 59H 5AH 5BH 5CH 5DH 5EH 5FH 60H 61H 62H 63H 64H 65H 66H 67H 68H 69H 6AH 6BH 6CH 6DH 6EH 6FH 70H 71H 72H 73H 74H 75H 76H 77H 78H 79H 7AH 7BH 7C
S1D12400 Series Vertical double-size display control Function: Displays the specified line in vertical doublesize form. The specified line corresponds to the address of the DDRAM. (Not the display line) RE A0 WR D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 0 0 1 0 DD4 DD3 DD2 DD1 =0 DD3 =1 DD2 =0 DD2 =1 DD1 =0 DD1 =1 : Displays the data for line 3 of the DDRAM in standard form. [DDRAM 50H to 5FH] : Displays the data for line 3 of the DDRAM in vertical doublesize form.
S1D12400 Series • Example of vertical double-size display An example of 4-line display will be cited for explanation. 1 [Initial status] 2 [Set DD4, DD3, DD2, DD1 = 1010.
S1D12400 Series • Example of vertical double-size display (characters) [Standard display] S1D12400 Series [Vertical double-size display] When the under-bar cursor is displayed, this will also be of double-size. Rev. 2.
S1D12400 Series Display ON/OFF control Function: Sets both display and cursor ON/OFF, and extended register access. RE A0 WR D7 D6 D5 D4 D3 D2 D1 D0 0/1 0 0 0 0 1 1 C B RE D • Extended register access is specified by setting RE. RE = 0 : Extended register OFF RE = 1 : Extended register ON • The relation between C/B register and cursor display is shown in the following table. C 0 0 1 1 • Display ON/OFF is specified by setting D.
S1D12400 Series Power control (1) Function: Controls the operation of the built-in power circuit. RE A0 WR D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 1 1 0 R1 R0 CS CG • Boosting circuit ON/OFF is specified by setting P. For operating the boosting circuit, the oscillating circuit must be in operation. P = 0 : Boosting circuit OFF P = 1 : Boosting circuit ON • Voltage follower ON/OFF is specified by setting VF.
S1D12400 Series • Example of display (compared by the same mounting method) ROM font (SS, CS) = (0, 0) (SS, CS) = (1, 0) (SS, CS) = (0, 1) (SS, CS) = (1, 1) RAM address set (1) [DDRAM, static icon RAM, electronic volume RAM] RAM address set (2) [CGRAM, symbol register RAM] Function: Sets the address for writing data into the DDRAM, static icon RAM (including blink control), and electronic volume RAM in the address counter.
S1D12400 Series NO Write in RAM? YES Set RE bit Be sure to set the RE bit and the address in a pair. Set address Write YES Note: When making access to the RAM after a change of the RE bit, be sure to set the address. If not, the contents of the RAM will be abnormal on the display.
S1D12400 Series [S1D12400 Series RAM map] (2-line 16-digit display) Low RE High order order 0XH 0 1 SI 2 3 4 SIB 5 6 Unused 7 8 9 A B Unused 2XH Unused 3XH DDRAM line 1 4XH DDRAM line 2 5XH DDRAM line 3 6XH DDRAM line 4 7XH DDRAM line 5 D E F Unused EV TEST 1XH C Symbol register: COMS1, 2 For static icon: COMSA, SEGSA - J 0 0XH CGROM(00H) CGROM(01H) 1XH CGROM(02H) CGROM(03H) 2XH CGROM(04H) CGROM(05H) 3XH Unused 4XH Unused 5XH Unused 6XH Symbol register
S1D12400 Series RAM data write Function: Writes data in the RAM areas of the DDRAM, CGRAM, symbol register RAM, static icon RAM, and electronic volume RAM. Before this command, be sure to execute the address set command. After that, each time data is written, the address will be automatically incremented. (Regarding the RE bit, the contents set by the command will be kept in memory.) 1 Data is written into the DDRAM, CGRAM, symbol register RAM, static icon RAM, or electronic volume RAM.
S1D12400 Series 8. CHARACTER GENERATOR Character Generator ROM (CGROM) The S1D12400 series is provided with a character generator ROM consisting of up to 544 types of characters. Each character size is of a structure of 5 × 8 dots. A character code table of the S1D12400 series is shown in CGROM Table X to X. In this case, which of CGROM and CGRAM should be used for the 6 characters of 00H to 05H of the character code is specified by the system set command.
S1D12400 Series [JIS1: A Font] Standard ROM Font Lower 4 Bit of Code 0 H i g h e r 4 B i t 1 2 3 4 5 6 7 8 9 A B C D E F 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 C o d e 0 Rev. 2.
S1D12400 Series OPTION ROM1 (when R1, R0 = 0, 0 is selected) Lower 4 Bit of Code 0 1 2 3 4 5 6 7 8 9 A B C D E F A A B B 4 C C B i t D D E E F F H i g h e r o f C o d e 0 1 2 3 4 5 6 7 8 9 A B C D E F 9 A B C D E F OPTION ROM2 (when R1, R0 = 0, 1 is selected) Lower 4 Bit of Code 0 1 2 3 4 5 6 7 8 A A B B 4 C C B i t D D E E F F H i g h e r o f C o d e 0 6–40 1 2 3 4 5 6 7 8 EPSON 9 A B C D E F Rev. 2.
S1D12400 Series OPTION ROM3 (when R1, R0 = 1, 0 is selected) Lower 4 Bit of Code 0 1 2 3 4 5 6 7 8 9 A B C D E F A A B B 4 C C B i t D D E E F F H i g h e r o f C o d e 1 2 3 4 5 6 7 8 9 A B C D E F 9 A B C D E F S1D12400 Series 0 OPTION ROM4 (R1, R0 = 1,1 is selected) Lower 4 Bit of Code 0 1 2 3 4 5 6 7 8 A A B B 4 C C B i t D D E E F F H i g h e r o f C o d e 0 Rev. 2.
S1D12400 Series [CGROM Font (ASCII: Font B)] Standard ROM Font Lower 4 Bit of Code 0 H i g h e r 1 2 3 4 5 6 7 8 9 A B C D E F 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 4 B i t o f C o d e 0 6–42 1 2 3 4 5 6 7 EPSON 8 9 A B C D E F Rev. 2.
S1D12400 Series OPTION ROM1 (when R1, R0 = 0, 0 is selected) Lower 4 Bit of Code 0 H i g 1 2 3 4 5 6 7 8 9 A B C D E F A A h e r B B 4 C C B i t D D E E F F o f 0 1 2 3 4 5 6 7 8 9 A B C D E F 9 A B C D E F S1D12400 Series C o d e OPTION ROM2 (when R1, R0 = 0, 1 is selected) Lower 4 Bit of Code 0 H i g 1 2 3 4 5 6 7 8 A A h e r B B 4 C C B i t D D E E F F o f C o d e 0 Rev. 2.
S1D12400 Series OPTION ROM3 (when R1, R0 = 1, 0 is selected) Lower 4 Bit of Code 0 H i g h e r 1 2 3 4 5 6 7 8 9 A B C D E F A A B B C C D D E E F F 4 B i t o f C o d e 0 1 2 3 4 5 6 7 8 9 A B C D E F 9 A B C D E F OPTION ROM4 (R1, R0 = 1,1 is selected) Lower 4 Bit of Code 0 1 2 3 4 5 6 7 8 H i g h e r A A B B 4 C C B i t D D E E F F o f C o d e 0 6–44 1 2 3 4 5 6 7 8 EPSON 9 A B C D E F Rev. 2.
S1D12400 Series [CGROM Font (JISS2: Font G)] Standard ROM Font Lower 4 Bit of Code 0 H i g h e r 1 2 3 4 5 6 7 8 9 A B C D E F 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 4 o f C o d e 0 Rev. 2.
S1D12400 Series OPTION ROM1 (when R1, R0 = 0, 0 is selected) Lower 4 Bit of Code 0 H i g h e r 4 B i t o f C o d e 1 2 3 4 5 6 7 8 9 A B C D E F A A B B C C D D E E F F 0 1 2 3 4 5 6 7 8 9 A B C D E F 9 A B C D E F OPTION ROM2 (when R1, R0 = 0, 1 is selected) Lower 4 Bit of Code 0 H i g h e r 1 2 3 4 5 6 7 8 A A B B C C D D E E F F 4 B i t o f C o d e 0 6–46 1 2 3 4 5 6 7 8 EPSON 9 A B C D E F Rev. 2.
S1D12400 Series OPTION ROM3 (when R1, R0 = 1, 0 is selected) Lower 4 Bit of Code 0 H i g h e r 1 2 3 4 5 6 7 8 9 A B C D E F A A B B C C D D E E F F 4 o f C o d e 0 1 2 3 4 5 6 7 8 9 A B C D E F S1D12400 Series B i t OPTION ROM4 (R1, R0 = 1,1 is selected) Lower 4 Bit of Code 0 1 2 3 4 5 6 7 8 9 A B C D E F H i g h e r A A B B 4 C C B i t D D E E F F o f C o d e 0 Rev. 2.
S1D12400 Series Character Generator RAM (CGRAM) The S1D12400 series is provided with a CGROM that permits the user to program character patterns so as to attain a character display with a high degree of freedom. When using the CGRAM, select Use of CGRAM by the system set command. The CGRAM capacity is 240 bits having a structure of 5 × 8 dots and optional 6 types of patterns can be registered. The relation among CGRAM character patterns, CGRAM addresses, and character codes is shown below.
S1D12400 Series Symbol Register RAM The S1D12400 series is provided with a symbol register RAM that permits setting each symbol so that symbols may be displayed individually on the screen. The symbol register capacity is 160 bits in both S1D12400, S1D12401 and S1D12402 series and up to 160 symbols can be displayed. Each symbol can be blink-controlled in units of bit by using D7 and D6. The relation among symbol register display patterns, RAM address and write data is shown by citing an example.
S1D12400 Series Note 1: When a symbol is 1.5 times as large as other bits, it is recommended to divide it into COMS1 and COMS2 for driving. D7 (BONF) 0 1 1 6–50 D6 (IORH) * 0 1 Function No blink D4 to D0 blink in black-and-white reverse form. The bits of “1” out of D4 to D0 blink. fBLINK : 1 to 2Hz EPSON Rev. 2.
S1D12400 Series Static Icon RAM The S1D12400 series can display static icons in the standby mode. Each of 10 icons can be set in respect of ON/OFF and blink by using the pins of COMSA to SEGSA to J. The relation between static icon functions and static icon RAM write data is shown below.
S1D12400 Series Electronic Volume RAM The S1D12400 series is provided with an electronic volume function that permits controlling the liquid crystal drive voltage V5 and adjusting the density of liquid crystal display. The electronic volume function can select one of 32 states of the liquid crystal drive voltage by writing 5-bit data into the electronic volume RAM.
S1D12400 Series 9. ABSOLUTE MAXIMUM RATINGS Item Symbol Standard value Unit VSS –7.0 to +0.3 V Supply voltage (1) –7.0 to +0.3 Supply voltage (2) Double boosting VSS2 –7.0 to +0.3 Triple boosting V –6.0 to +0.3 Supply voltage (2) V5, VOUT –18.0 to +0.3 V Supply voltage (3) V1, V2, V3, V4 V5 to +0.3 V Input voltage VIN VSS–0.3 to +0.3 V Output voltage VO VSS–0.3 to +0.
S1D12400 Series 10. DC CHARACTERISTICS [VSS = –5.5 V to –1.8 V, Ta = –30 to 85°C unless otherwise specified] Supply voltage (1) Supply voltage (2) Supply voltage (3) Item Recommended operation Recommended operation Recommended operation Symbol VSS Condition — VSS2 — V5 When 1/4 bias used When 1/5 bias used — — VSS = –2.4V to –1.8V V1, V2 V3, V4 HIGH-level input voltage (1) VIHC LOW-level input voltage (1) VILC HIGH-level input voltage (2) VIHC VSS = –5.5V to –2.
S1D12400 Series Power supply *9: The boosting circuit performs boosting, using voltage between the VDD and VSS2 as source voltage. Check the VSS2 input voltage to ensure that it does not exceed V OUT absolute maximum rating, or the operating voltage range of the VSS system (VSS) and V5 system (V5). *10: Frequency f OSC of the internal circuit drive oscillating circuit and boosting clock fBST vary according to the type.
S1D12400 Series 11. AC CHARACTERISTICS System Bus Write Characteristics I (80 series MPU) tAH8 A0, CS tAH8 tCYC8 tCC WR tDS8 tDH8 D0 to D7 [VSS = –5.5 V to –4.5 V, Ta = –30 to 85°C unless otherwise specified] Measuring Item Signal Symbol Min. Max. Unit condition – 30 – ns Address hold time A0, CS tAH8 – 60 – ns Address setup time tAW8 – 300 – ns System cycle time WR tCYC8 – 60 – ns Control pulse width (Write) tCC – 60 – ns Data setup time D0 to D7 tDS8 – 50 – ns Data hold time tDH8 [VSS = –4.
S1D12400 Series System Bus Write Characteristics II (68 series MPU) tCYC6 E tEWL tAW6 tEWH tAH6 A0,CS tDS6 tDH6 Item System cycle time Address setup time Address hold time Data setup time Data hold time Enable HIGH pulse width Enable LOW pulse width Item System cycle time Address setup time Address hold time Data setup time Data hold time Enable HIGH pulse width Enable LOW pulse width Item System cycle time Address setup time Address hold time Data setup time Data hold time Enable HIGH pulse width E
S1D12400 Series Serial Interface tCSS tCSH CS tSAS tSAH A0 tSCYC tSLW SCL tSHW tSDS tSDH SI Item System clock cycle SCL HIGH pulse width SCL LOW pulse width Address setup time Address hold time Data setup time Data hold time CS-SCL time Item System clock cycle SCL HIGH pulse width SCL LOW pulse width Address setup time Address hold time Data setup time Data hold time CS-SCL time Item System clock cycle SCL HIGH pulse width SCL LOW pulse width Address setup time Address hold time Data setup tim
S1D12400 Series 12. MPU INTERFACE CONNECTION EXAMPLES (FOR REFERENCE) The S1D12400 series can be connected to the 80 series MPU or 68 series MPU. Furthermore, it can be operated with less signal lines if the serial interface is used. When an MPU bus, port, etc. are put into high-impedance for a certain period by RESET, input RESET into this machine after the input to the S1D12400 series becomes definitive.
S1D12400 Series 13. INTERFACE WITH LCD CELL (FOR REFERENCE) [16 digits × 4 line 5 × 8 dots + symbol] S1D12400 LCD panel 1st • • • • • • • • • • • • • • • • • • • 16th digits Static icon COMSA SEGSA • • SEGSJ Symbol COMS1 COMS2 COM1 2 3 4 5 6 7 8 COM9 10 11 12 13 14 15 16 COM17 18 19 20 21 22 23 24 COM25 26 27 28 29 30 31 32 Character SEG1 2 3 4 5 •••• SEG80 6–60 EPSON Rev. 2.
S1D12400 Series [16 digits × 3 line 5 × 8 dots] LCD panel 1 • • • • • • • • • • • • 16 columns S1D12401 COMSA SEGSA • • • SEGSJ Symbol COMS1 COMS2 COM1 2 3 4 5 6 7 8 S1D12400 Series COM9 10 11 12 13 14 15 16 COM17 18 19 20 21 22 23 24 Character SEG1 SEG2 SEG3 SEG4 SEG5 • • SEG80 Rev. 2.
S1D12400 Series [16 digits × 2 line 5 × 8 dots] LCD panel 1 • • • • • • • • • • • • 16 columns S1D12402 COMSA SEGSA • • • SEGSJ Symbol COMS1 COMS2 COM1 2 3 4 5 6 7 8 COM9 10 11 12 13 14 15 16 Character SEG1 SEG2 SEG3 SEG4 SEG5 • • SEG80 6–62 EPSON Rev. 2.
S1D12400 Series 14. LCD DRIVE WAVEFORM (B WAVEFORM) VDD V1 V2 V3 V4 V5 COM 1 VDD V1 V2 V3 V4 V5 COM 2 COM 9 COM 10 COM 11 COM 12 COM 13 COM 14 COM 15 COM 16 SEG 1 SEG 2 SEG 3 SEG 4 SEG 5 VDD V1 V2 V3 V4 V5 COM 3 VDD V1 V2 V3 V4 V5 SEG 1 VDD V1 V2 V3 V4 V5 SEG 2 V5 V4 V3 V2 V1 VDD –V1 –V2 –V3 –V4 –V5 COM1 - SEG 1 V5 V4 V3 V2 V1 VDD –V1 –V2 –V3 –V4 –V5 COM1 - SEG 2 Rev. 2.
S1D12400 Series 15. INSTRUCTION SETUP EXAMPLE (REFERENCE) (1) Initialization This IC has no power-on reset function when power is turned on. Accordingly, the IC internal status is indefinite when the power has been turned on. Be sure to initialize the system. If electric charge remains in the smoothing capacitor connected between the liquid crystal drive voltage output terminal (V1 to V5) and VDD terminal, such a trouble as temporary blackening will occur when power is turned on.
S1D12400 Series (2-1) Setting the Standby mode (2-1) Resetting the Standby mode End of initialization Standby mode Normal operation (Power save is cleared and oscillating circuit is on.
S1D12400 Series (4) Power off sequence Similar to the case of power on sequence, if this IC power is turned off when the built-in power is on, power supply to the built-in liquid crystal drive circuit may continue for a very little time, adversely affecting the liquid crystal panel display quality. To prevent this, strictly follow the power off sequence. 16. OPTIONS LIST The S1D 12400 series has the following options. Options are available exclusively for users. Please contact our Sales Department.
S1D12400 Series 17. EXAMPLE OF TCP ARRANGEMENT Note: The following does not specify the TCP external view. REFERENCE NC NC NC COMSA SEGSF SEGSG SEGSH SEGSJ IF COMS1 P/S COM1 V S1 . CK . V SS2 . V SS . CAP1+ COM16 CAP1– COMS1 CAP2+ SEG1 CAP2– . V OUT . VR V0 V1 V2 V4 V5 D1 D2 CHIP V DD D0 . . . . TOP V3 S1D12400 Series SEGSI C86 VIEW RES SEG80 COMS2 [COM32] [.] [.] [COM25] D3 (COM24) (.) D4 (.
Output terminal section pattern shape Specification: • Base Yurex 75µm • Copper foil electrolytic foil 25µm • Sn coating • Resist position tolerance ±0.3 • Pitch 4IP (19mm) TCP External View 6–68 EPSON Note 1: The dimensions are measured after placing the product in the environment of 25°C x 60% x 72H. *Punching for nonconformance A hole of 4 x 10mm or more shall be punched at a point near (0,0). (Mold, marking area) S1D12400 Series 18. EXAMPLE OF TCP REFERENCE Rev. 2.
EPSON S1D12200 S1D12205 Rev. 2.1 S1D12400 *** System set • S1 = 0 • S2 = 0 System set • CS = 0 • SS = 0 System set • CS = 0 • SS = 1 (SEG-reversed) However, the input of DDRAM address of "S1D12***" from the first digit of the first line shall be 3FH and 3EH, in this order (as it is reversed in the unit of character). System set • S=0 System set • S1 = 0 • S2 = 1 (Horizontally-reversed) • Unable to correspond with commands. • Only able to correspond with custom fonts.
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NOTICE No parts of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice.
MF423-11 S1D12000 Series Technical Manual IEEE1394 LCD DRIVER Controller IC S1R72801F00A S1D12000 Series Technical Manual S1D12000 Series Technical Manual ELECTRONIC DEVICES MARKETING DIVISION EPSON Electronic Devices Website http://www.epson.co.jp/device/ This manual was made with recycle paper, and printed using soy-based inks. First issue November,1990 U Printed May,2001 in Japan H B 4.
